JP6027738B2 - COMPOUND SEMICONDUCTOR LAYER AND METHOD FOR PRODUCING SAME, COMPOUND THIN FILM SOLAR CELL AND METHOD FOR PRODUCING SAME - Google Patents
COMPOUND SEMICONDUCTOR LAYER AND METHOD FOR PRODUCING SAME, COMPOUND THIN FILM SOLAR CELL AND METHOD FOR PRODUCING SAME Download PDFInfo
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- JP6027738B2 JP6027738B2 JP2011270109A JP2011270109A JP6027738B2 JP 6027738 B2 JP6027738 B2 JP 6027738B2 JP 2011270109 A JP2011270109 A JP 2011270109A JP 2011270109 A JP2011270109 A JP 2011270109A JP 6027738 B2 JP6027738 B2 JP 6027738B2
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- compound semiconductor
- semiconductor layer
- organic polymer
- compound
- solar cell
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- 238000010304 firing Methods 0.000 claims description 24
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- -1 n-octaneselenal Chemical compound 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 229910052711 selenium Inorganic materials 0.000 claims description 9
- 229910052717 sulfur Inorganic materials 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 7
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- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 2
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- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
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- DOEHJNBEOVLHGL-UHFFFAOYSA-N trichloro(propyl)silane Chemical compound CCC[Si](Cl)(Cl)Cl DOEHJNBEOVLHGL-UHFFFAOYSA-N 0.000 description 1
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- ZNOCGWVLWPVKAO-UHFFFAOYSA-N trimethoxy(phenyl)silane Chemical compound CO[Si](OC)(OC)C1=CC=CC=C1 ZNOCGWVLWPVKAO-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/032—Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312
- H01L31/0322—Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312 comprising only AIBIIICVI chalcopyrite compounds, e.g. Cu In Se2, Cu Ga Se2, Cu In Ga Se2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02568—Chalcogenide semiconducting materials not being oxides, e.g. ternary compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02601—Nanoparticles
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02623—Liquid deposition
- H01L21/02628—Liquid deposition using solutions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/032—Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312
- H01L31/0326—Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312 comprising AIBIICIVDVI kesterite compounds, e.g. Cu2ZnSnSe4, Cu2ZnSnS4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
- H01L31/0384—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including other non-monocrystalline materials, e.g. semiconductor particles embedded in an insulating material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
- H01L31/0749—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type including a AIBIIICVI compound, e.g. CdS/CulnSe2 [CIS] heterojunction solar cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/541—CuInSe2 material PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Description
本発明は、化合物半導体層と、化合物半導体層を備えた化合物薄膜太陽電池とに関し、さらにはこれらの製造方法に関する。 The present invention relates to a compound semiconductor layer and a compound thin film solar cell including the compound semiconductor layer, and further relates to a method for manufacturing these.
ＣＩＧＳまたはＣＺＴＳに代表される化合物薄膜太陽電池には、光吸収層となる化合物半導体層の材料特性による高性能化、および化合物半導体層の数μｍオーダーへの薄膜化による低コスト化が見込めるため、近年、活発に開発が進められている。 In compound thin-film solar cells represented by CIGS or CZTS, high performance due to the material characteristics of the compound semiconductor layer serving as the light absorption layer and cost reduction due to thinning of the compound semiconductor layer to the order of several μm can be expected. In recent years, development has been actively promoted.
一般に、化合物薄膜太陽電池の製造方法は、真空プロセスを用いて化合物半導体層を作製する真空成膜法と、非真空プロセスを用いて化合物半導体層を作製する非真空成膜法とに分けられる。真空成膜法は、真空下で化合物半導体層を構成する元素（Ｃｕ、Ｉｎ、Ｇａなど）を蒸着またはスパッタリングにより堆積させる工程を含む。そのため、真空成膜法では、材料利用効率が低く、また真空設備の導入およびその維持に多額の費用が必要である。 In general, a method for manufacturing a compound thin film solar cell can be divided into a vacuum film forming method in which a compound semiconductor layer is formed using a vacuum process and a non-vacuum film forming method in which a compound semiconductor layer is formed using a non-vacuum process. The vacuum film-forming method includes a step of depositing elements (Cu, In, Ga, etc.) constituting the compound semiconductor layer under vacuum by vapor deposition or sputtering. Therefore, the vacuum film forming method has low material utilization efficiency, and requires a large amount of money for the introduction and maintenance of the vacuum equipment.
一方、非真空成膜法は、化合物半導体層を構成する元素を含んだ溶液を基板上に塗布してから焼成するものであり、真空成膜法と比べて材料利用効率が高く且つ設備費用が安価であるというメリットを有する。 On the other hand, the non-vacuum film-forming method is a method in which a solution containing an element constituting the compound semiconductor layer is applied onto a substrate and then baked, and has higher material utilization efficiency and equipment cost than the vacuum film-forming method. It has the merit of being inexpensive.
非真空成膜法の中でも、Ｃｕ、Ｉｎ、Ｇａ、またはＳｅなどの化合物半導体材料の核部分の周囲が有機配位子で取り囲まれてなるナノ粒子を基板上に塗布してから焼成処理を行うことで化合物半導体層を形成する手法（以下、ナノ粒子塗布焼成法と記載）が好適である。その理由は、ナノ粒子が有機配位子によって溶媒中に凝集することなく良好に分散するからであり、またナノ粒子を用いることによって焼成温度を低くすることができるからである。 Among non-vacuum film forming methods, a nanoparticle in which the periphery of a core portion of a compound semiconductor material such as Cu, In, Ga, or Se is surrounded by an organic ligand is applied on a substrate and then subjected to a baking treatment. Thus, a method of forming a compound semiconductor layer (hereinafter referred to as a nanoparticle coating and firing method) is suitable. The reason is that the nanoparticles are well dispersed without being aggregated in the solvent by the organic ligand, and the firing temperature can be lowered by using the nanoparticles.
ところで、太陽光を十分に吸収する化合物半導体層の膜厚としては２〜３μｍが必要である。しかし、一般にナノ粒子塗布焼成法を用いた場合、１回の塗布焼成処理では、１００ｎｍ程度の膜厚しか得られない。この理由は、粒子の微細化に伴って核部分に対する有機配位子の体積比が増えるので、焼成時に生ずる配位子の脱離により化合物半導体層の体積が収縮し、化合物半導体層にクラックが発生するからである。化合物半導体層にクラックが発生すると、積層方向のリークパスの原因となってしまう。そして、この問題は、化合物半導体層の膜厚の増加に伴ってより一層顕在化するために、１回の塗布焼成処理でクラックの発生を抑えた厚膜を得ることは難しい。 By the way, the film thickness of the compound semiconductor layer that sufficiently absorbs sunlight needs to be 2 to 3 μm. However, in general, when the nanoparticle coating and baking method is used, only a film thickness of about 100 nm can be obtained by one coating and baking process. The reason for this is that the volume ratio of the organic ligand to the core increases as the particles become finer, so the volume of the compound semiconductor layer shrinks due to the elimination of the ligand that occurs during firing, and cracks occur in the compound semiconductor layer. This is because it occurs. If a crack occurs in the compound semiconductor layer, it causes a leak path in the stacking direction. And since this problem becomes more apparent as the thickness of the compound semiconductor layer increases, it is difficult to obtain a thick film in which the generation of cracks is suppressed by a single coating and baking process.
焼成時におけるクラックの発生を防止する手法としては、たとえば特許文献１に、化合物半導体からなる微細粒子を含む有機溶媒中にＮａを混合して薄膜太陽電池を製造することが記載されている。この手法では、Ｎａが欠陥の起点において結着剤として作用するため、焼成時に発生する欠陥を抑制できる。 As a technique for preventing the occurrence of cracks during firing, for example, Patent Document 1 describes that a thin film solar cell is manufactured by mixing Na in an organic solvent containing fine particles made of a compound semiconductor. In this method, since Na acts as a binder at the starting point of defects, defects generated during firing can be suppressed.
しかしながら、特許文献１に記載の方法を用いて得られたＮａ添加の化合物半導体層においても、クラックの発生が抑えられるのは当該化合物半導体層の膜厚が数百ｎｍ以下である場合に限られる。実際、特許文献１の実施例においても、１．４μｍの膜厚の化合物半導体層を形成するために、塗布工程および焼成工程を７回行なっている。このように、従来技術においては、クラックの発生が抑制され且つ太陽光を十分に吸収できる化合物半導体層には、塗布工程および焼成工程を複数回行って形成する必要があるためにスループットが低いという課題があった。 However, even in the Na-added compound semiconductor layer obtained using the method described in Patent Document 1, the occurrence of cracks can be suppressed only when the thickness of the compound semiconductor layer is several hundred nm or less. . Actually, also in the example of Patent Document 1, in order to form a compound semiconductor layer having a film thickness of 1.4 μm, the coating process and the baking process are performed seven times. Thus, in the prior art, the compound semiconductor layer that suppresses the generation of cracks and can sufficiently absorb sunlight has to have a low throughput because it needs to be formed by performing a coating process and a baking process multiple times. There was a problem.
本発明は、かかる課題を鑑み、スループットの低下を招くことなくナノ粒子塗布焼成法を用いて作製され、太陽光を十分に吸収できる膜厚を有し、かつクラックの発生が抑制された化合物半導体層を提供する。 In view of such problems, the present invention is a compound semiconductor that is produced using a nanoparticle coating and firing method without causing a decrease in throughput, has a film thickness that can sufficiently absorb sunlight, and has cracks suppressed. Provide a layer.
本発明者らは鋭意検討の結果、以下のような化合物半導体層によって上記課題を解決できることを見出した。 As a result of intensive studies, the present inventors have found that the above-described problems can be solved by the following compound semiconductor layer.
本発明に係る化合物半導体層は、化合物半導体材料からなる化合物半導体部分と、有機高分子材料からなる有機高分子部分とから構成されている。 The compound semiconductor layer according to the present invention includes a compound semiconductor portion made of a compound semiconductor material and an organic polymer portion made of an organic polymer material.
化合物半導体部分は化合物半導体材料からなる複数の結晶粒からなり、有機高分子部分は隣り合う結晶粒の間に充填されていることが好ましい。 The compound semiconductor portion is preferably composed of a plurality of crystal grains made of a compound semiconductor material, and the organic polymer portion is preferably filled between adjacent crystal grains.
有機高分子部分の化合物半導体部分に対する質量比は、０．１以上であることが好ましい。また、この質量比は、０．３以下であることが好ましい。 The mass ratio of the organic polymer portion to the compound semiconductor portion is preferably 0.1 or more. Moreover, it is preferable that this mass ratio is 0.3 or less.
有機高分子材料は、導電性有機高分子材料であることが好ましい。
化合物半導体材料は、Ｃｕと、ＩｎおよびＧａの少なくとも一方と、ＳｅおよびＳの少なくとも一方とを含んでも良く、またはＣｕと、Ｚｎと、Ｓｎと、ＳｅおよびＳの少なくとも一方とを含んでも良い。
The organic polymer material is preferably a conductive organic polymer material.
The compound semiconductor material may include Cu, at least one of In and Ga, and at least one of Se and S, or may include Cu, Zn, Sn, and at least one of Se and S.
本発明に係る化合物薄膜太陽電池は、基板と、基板上に設けられた第１電極、化合物半導体層、および第２電極とを備えている。ここで、化合物半導体層は、本発明に係る化合物半導体層である。 The compound thin film solar cell according to the present invention includes a substrate, a first electrode, a compound semiconductor layer, and a second electrode provided on the substrate. Here, the compound semiconductor layer is a compound semiconductor layer according to the present invention.
本発明に係る化合物半導体層の製造方法は、化合物半導体材料からなる核部分と核部分の周囲を取り囲む配位子部分とを含むナノ粒子と、有機高分子材料とが分散された溶液を調製する工程と、溶液を基板上に塗布してから焼成する工程とを備えている。 The method for producing a compound semiconductor layer according to the present invention prepares a solution in which a nanoparticle including a core portion made of a compound semiconductor material and a ligand portion surrounding the core portion and an organic polymer material are dispersed. And a step of applying the solution onto the substrate and then baking.
焼成工程は、核部分と配位子部分との間に働く結合力が解離する温度以上の温度で行われることが好ましく、たとえば１５０℃以上５００℃以下で行なわれれば良い。 The firing step is preferably performed at a temperature equal to or higher than the temperature at which the binding force acting between the nucleus portion and the ligand portion is dissociated, and may be performed at, for example, 150 ° C. or more and 500 ° C. or less.
ナノ粒子の直径は、１ｎｍ以上１００ｎｍ以下であることが好ましい。ここで、ナノ粒子の直径とは、核部分の中心と配位子部分のうち核部分の中心から最も遠くに位置する部分との径方向における距離の２倍の距離を意味し、たとえば透過型電子顕微鏡（ＴＥＭ）でナノ粒子を観察する方法により測定される。 The diameter of the nanoparticles is preferably 1 nm or more and 100 nm or less. Here, the diameter of the nanoparticle means a distance twice the radial distance between the center of the core portion and the portion of the ligand portion that is farthest from the center of the core portion. It is measured by a method of observing nanoparticles with an electron microscope (TEM).
本発明に係る化合物薄膜太陽電池を製造する方法では、基板上に第１電極、化合物半導体層、および第２電極を形成し、化合物半導体層は本発明に係る化合物半導体層の製造方法によって形成される。 In the method for producing a compound thin film solar cell according to the present invention, a first electrode, a compound semiconductor layer, and a second electrode are formed on a substrate, and the compound semiconductor layer is formed by the method for producing a compound semiconductor layer according to the present invention. The
本発明に係る化合物半導体層によれば、スループットの低下を招くことなくナノ粒子塗布焼成法を用いて作製され、太陽光を十分に吸収できる膜厚を有し、かつクラックの発生が抑制されている。 The compound semiconductor layer according to the present invention is produced using a nanoparticle coating and baking method without causing a decrease in throughput, has a film thickness that can sufficiently absorb sunlight, and the generation of cracks is suppressed. Yes.
以下、本発明の化合物半導体層および化合物薄膜太陽電池について図面を用いて説明する。なお、本発明の図面において、同一の参照符号は、同一部分または相当部分を表すものである。また、長さ、幅、厚さ、深さなどの寸法関係は図面の明瞭化と簡略化のために適宜変更されており、実際の寸法関係を表すものではない。 Hereinafter, the compound semiconductor layer and the compound thin film solar cell of the present invention will be described with reference to the drawings. In the drawings of the present invention, the same reference numerals represent the same or corresponding parts. In addition, dimensional relationships such as length, width, thickness, and depth are changed as appropriate for clarity and simplification of the drawings, and do not represent actual dimensional relationships.
〔化合物半導体層の構成〕
図１を参照して本発明に係る化合物半導体層を説明する。図１は、本発明の一実施形態に係る化合物半導体層１００の概略断面図である。
[Configuration of Compound Semiconductor Layer]
The compound semiconductor layer according to the present invention will be described with reference to FIG. FIG. 1 is a schematic cross-sectional view of a compound semiconductor layer 100 according to an embodiment of the present invention.
化合物半導体層１００は、化合物半導体材料からなる化合物半導体部分１１と、有機高分子材料２２（図３参照）からなる有機高分子部分１２とで構成されている。 The compound semiconductor layer 100 includes a compound semiconductor portion 11 made of a compound semiconductor material and an organic polymer portion 12 made of an organic polymer material 22 (see FIG. 3).
化合物半導体部分１１は、化合物半導体材料からなる複数の結晶粒からなり、その結晶粒のサイズは、例えば１〜５０００ｎｍである。ここで、化合物半導体材料とは、２つ以上の原子が共有結合またはイオン結合により結合された半導体材料であり、本発明ではＣｕとＩｎおよびＧａの少なくとも一方とＳｅおよびＳの少なくとも一方とがイオン結合により結合された半導体材料であっても良く、ＣｕとＺｎとＳｎとＳｅおよびＳの少なくとも一方とがイオン結合により結合された半導体材料であっても良い。このような化合物半導体材料としては、例えば、ＣｕＩｎxＧａ1-x（ＳｅyＳ1-y）2（０≦ｘ≦１、０≦ｙ≦１）、ＣｕＡｌxＩｎ1-x（ＳｅyＳ1-y）2（０≦ｘ≦１、０≦ｙ≦１）、ＣｕＡｌxＧａ1-x（ＳｅyＳ1-y）2（０≦ｘ≦１、０≦ｙ≦１）、ＡｇＩｎxＧａ1-x（ＳｅyＳ1-y）2（０≦ｘ≦１、０≦ｙ≦１）、ＡｇＡｌxＩｎ1-x（ＳｅyＳ1-y）2（０≦ｘ≦１、０≦ｙ≦１）、ＡｇＡｌxＧａ1-x（ＳｅyＳ1-y）2（０≦ｘ≦１、０≦ｙ≦１）、Ｃｕ2ＺｎＳｎ（ＳｅxＳ1-x）4（０≦ｘ≦１）、ＣｄＳ、ＣｄＳｅ、ＣｄＴｅ、ＺｎＳ、ＺｎＳｅ、ＺｎＴｅ、ＨｇＳ、ＨｇＳｅ、ＨｇＴｅ、ＰｂＳｅ、ＰｂＳ、ＧａＮ、ＧａＰ、ＧａＡｓ、ＡｌＮ、ＡｌＰ、ＡｌＡｓ、ＩｎＮ、ＩｎＰ、ＩｎＡｓ、ＣｄＳｅＳ、ＣｄＳｅＴｅ、ＣｄＳＴｅ、ＺｎＳｅＳ、ＺｎＳｅＴｅ、ＺｎＳＴｅ、ＨｇＳｅＳ、ＨｇＳｅＴｅ、ＨｇＳＴｅ、ＣｄＺｎＳ、ＣｄＺｎＳｅ、ＣｄＺｎＴｅ、ＣｄＨｇＳ、ＣｄＨｇＳｅ、ＣｄＨｇＴｅ、ＨｇＺｎＳ、ＨｇＺｎＳｅ、ＨｇＺｎＴｅ、ＣｄＺｎＳｅＳ、ＣｄＺｎＳｅＴｅ、ＣｄＺｎＳＴｅ、ＣｄＨｇＳｅＳ、ＣｄＨｇＳｅＴｅ、ＣｄＨｇＳＴｅ、ＨｇＺｎＳｅＳ、ＨｇＺｎＳｅＴｅ、ＨｇＺｎＳＴｅ、ＧａＮＰ、ＧａＮＡｓ、ＧａＰＡｓ、ＡｌＮＰ、ＡｌＮＡｓ、ＡｌＰＡｓ、ＩｎＮＰ、ＩｎＮＡｓ、ＩｎＰＡｓ、ＩｎＧａＮ、ＧａＡｌＮＰ、ＧａＡｌＮＡｓ、ＧａＡｌＰＡｓ、ＧａＩｎＮＰ、ＧａＩｎＮＡｓ、ＧａＩｎＰＡｓ、ＩｎＡｌＮＰ、ＩｎＡｌＮＡｓ、またはＩｎＡｌＰＡｓなどが挙げられる。結晶粒のサイズの測定方法は、たとえば走査型電子顕微鏡（ＳＥＭ）または透過型電子顕微鏡（ＴＥＭ）で化合物半導体層を観察する方法であれば良い。 The compound semiconductor portion 11 is composed of a plurality of crystal grains made of a compound semiconductor material, and the size of the crystal grains is, for example, 1 to 5000 nm. Here, the compound semiconductor material is a semiconductor material in which two or more atoms are bonded by a covalent bond or an ionic bond. In the present invention, at least one of Cu, In and Ga and at least one of Se and S are ions. A semiconductor material bonded by bonding may be used, or a semiconductor material in which Cu, Zn, Sn, Se, and S are bonded by ionic bonding may be used. As such a compound semiconductor material, for example, CuIn x Ga 1-x (Se y S 1-y ) 2 (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), CuAl x In 1-x (Se y S). 1-y ) 2 (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), CuAl x Ga 1-x (Se y S 1-y ) 2 (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), AgIn x Ga 1-x (Se y S 1-y ) 2 (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), AgAl x In 1-x (Se y S 1-y ) 2 (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), AgAl x Ga 1-x (Se y S 1-y) 2 (0 ≦ x ≦ 1,0 ≦ y ≦ 1), Cu 2 ZnSn (Se x S 1-x) 4 (0 ≦ x ≦ 1), CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, PbSe, PbS, GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, CdSeS, CdS Te, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, InGaN, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. The crystal grain size may be measured by any method as long as the compound semiconductor layer is observed with, for example, a scanning electron microscope (SEM) or a transmission electron microscope (TEM).
有機高分子部分１２は、有機高分子材料２２（図３参照）からなり、溶融した有機高分子材料が凝固することにより形成されたものであり、隣り合う結晶粒（結晶粒は、化合物半導体部分１１を構成する化合物半導体からなる結晶粒）の間に充填されていることが好ましい。有機高分子材料２２は、例えば、ポリエチレン、ポリプロピレン、またはナイロン６等の絶縁性高分子材料であっても良く、ポリフェニレンビニレン、ポリアニリン、またはポリ(３−ヘキシルチオフェン)等の導電性高分子材料であっても良いが、好ましくは導電性高分子材料である。有機高分子材料２２が導電性を有していれば、有機高分子材料２２が絶縁性を有している場合に比べて、化合物半導体層１００の導電性が向上する。 The organic polymer portion 12 is made of an organic polymer material 22 (see FIG. 3) and is formed by solidification of a molten organic polymer material. Adjacent crystal grains (the crystal grains are compound semiconductor portions). 11 is preferably filled between the crystal grains made of a compound semiconductor constituting 11. The organic polymer material 22 may be, for example, an insulating polymer material such as polyethylene, polypropylene, or nylon 6, or a conductive polymer material such as polyphenylene vinylene, polyaniline, or poly (3-hexylthiophene). Although it may be, it is preferably a conductive polymer material. If the organic polymer material 22 has conductivity, the conductivity of the compound semiconductor layer 100 is improved as compared with the case where the organic polymer material 22 has insulating properties.
化合物半導体部分１１に対する有機高分子部分１２の割合（質量比）は、好ましくは０．１以上０．３以下である。この割合が０．１未満であれば、化合物半導体層１００におけるクラックの発生を抑制できないことがある。一方、この割合が０．３を超えると、化合物半導体層１００が導電性に優れないことがある。しかし、この割合が０．１以上０．３以下であれば、導電性に優れた化合物半導体層１００を形成でき、またクラックの発生を伴うことなく厚膜な化合物半導体層１００を形成できる。 The ratio (mass ratio) of the organic polymer portion 12 to the compound semiconductor portion 11 is preferably 0.1 or more and 0.3 or less. If this ratio is less than 0.1, the occurrence of cracks in the compound semiconductor layer 100 may not be suppressed. On the other hand, when this ratio exceeds 0.3, the compound semiconductor layer 100 may not be excellent in electroconductivity. However, when the ratio is 0.1 or more and 0.3 or less, the compound semiconductor layer 100 having excellent conductivity can be formed, and the thick compound semiconductor layer 100 can be formed without generating cracks.
本発明に係る化合物半導体層１００は、化合物半導体部分１１と有機高分子部分１２とで構成されているので、スループットの低下を招くことなく且つクラックの発生を伴うことなくナノ粒子塗布焼成法を用いて厚膜（太陽光を十分に吸収できる厚さ、たとえば１μｍ以上５μｍ以下）に作製される。本発明に係る化合物半導体層１００は、以下に示す製造方法にしたがって製造される。 Since the compound semiconductor layer 100 according to the present invention is composed of the compound semiconductor portion 11 and the organic polymer portion 12, the nanoparticle coating and firing method is used without causing a decrease in throughput and without causing cracks. To a thick film (thickness that can sufficiently absorb sunlight, for example, 1 μm to 5 μm). The compound semiconductor layer 100 according to the present invention is manufactured according to the following manufacturing method.
〔化合物半導体層の製造方法〕
図２および図３を参照して、本発明に係る化合物半導体層の製造方法（以下、「本発明に係る製造方法」という。）を説明する。図２は、本発明に係る製造方法の概略フロー図である。図３は、本発明に係る製造方法における溶液調製プロセスＳ１および塗布プロセスＳ２で用いる溶液２００の模式図である。
[Method for producing compound semiconductor layer]
With reference to FIG. 2 and FIG. 3, the manufacturing method of the compound semiconductor layer concerning this invention (henceforth "the manufacturing method concerning this invention") is demonstrated. FIG. 2 is a schematic flowchart of the manufacturing method according to the present invention. FIG. 3 is a schematic diagram of a solution 200 used in the solution preparation process S1 and the coating process S2 in the manufacturing method according to the present invention.
図２に示すように、本発明に係る製造方法は、溶液調製プロセスＳ１、塗布プロセスＳ２、乾燥プロセスＳ３、および焼成プロセスＳ４を備える。以下、各プロセスについて詳しく説明する。 As shown in FIG. 2, the manufacturing method according to the present invention includes a solution preparation process S1, a coating process S2, a drying process S3, and a baking process S4. Hereinafter, each process will be described in detail.
−溶液調製プロセス−
溶液調製プロセスＳ１では、ナノ粒子２１および有機高分子材料２２を溶媒２３に分散または溶解させて、溶液２００を調製する。具体的には、必要量のナノ粒子２１および有機高分子材料２２を溶媒２３中に加えて攪拌または加熱を行って、ナノ粒子２１および有機高分子材料２２を溶媒２３中に分散または溶解させる。得られる化合物半導体層１００において有機高分子部分１２の化合物半導体部分１１に対する質量比が０．１以上０．３以下となるように、ナノ粒子２１および有機高分子材料２２の各配合量を設定することが好ましい。
-Solution preparation process-
In the solution preparation process S1, the nanoparticles 21 and the organic polymer material 22 are dispersed or dissolved in the solvent 23 to prepare the solution 200. Specifically, the required amount of nanoparticles 21 and organic polymer material 22 are added to solvent 23 and stirred or heated to disperse or dissolve nanoparticles 21 and organic polymer material 22 in solvent 23. The blending amounts of the nanoparticles 21 and the organic polymer material 22 are set so that the mass ratio of the organic polymer portion 12 to the compound semiconductor portion 11 in the obtained compound semiconductor layer 100 is 0.1 or more and 0.3 or less. It is preferable.
ナノ粒子２１は、核部分２４と、核部分２４の周囲を取り囲む配位子部分２５とを有する。ナノ粒子２１の直径は、およそ１〜１０００ｎｍであれば良く、好ましくは１〜１００ｎｍであり、より好ましくは１〜２０ｎｍである。ナノ粒子２１の直径が１〜１００ｎｍであれば、ナノ粒子２１の表面積が大きくなるため、溶液調製プロセスＳ１での温度を低下させることができる。 The nanoparticle 21 has a core part 24 and a ligand part 25 surrounding the core part 24. The diameter of the nanoparticle 21 should just be about 1-1000 nm, Preferably it is 1-100 nm, More preferably, it is 1-20 nm. If the diameter of the nanoparticle 21 is 1 to 100 nm, the surface area of the nanoparticle 21 increases, so that the temperature in the solution preparation process S1 can be lowered.
核部分２４は、化合物半導体材料からなり、本発明の製造方法により化合物半導体部分１１を構成する。核部分２４を構成する化合物半導体材料としては、例えばＣｕＩｎxＧａ1-x（ＳｅyＳ1-y）2（０≦ｘ≦１、０≦ｙ≦１）、ＣｕＡｌxＩｎ1-x（ＳｅyＳ1-y）2（０≦ｘ≦１、０≦ｙ≦１）、ＣｕＡｌxＧａ1-x（ＳｅyＳ1-y）2（０≦ｘ≦１、０≦ｙ≦１）、ＡｇＩｎxＧａ1-x（ＳｅyＳ1-y）2（０≦ｘ≦１、０≦ｙ≦１）、ＡｇＡｌxＩｎ1-x（ＳｅyＳ1-y）2（０≦ｘ≦１、０≦ｙ≦１）、ＡｇＡｌxＧａ1-x（ＳｅyＳ1-y）2（０≦ｘ≦１、０≦ｙ≦１）、Ｃｕ2ＺｎＳｎ（ＳｅxＳ1-x）4（０≦ｘ≦１）、ＣｄＳ、ＣｄＳｅ、ＣｄＴｅ、ＺｎＳ、ＺｎＳｅ、ＺｎＴｅ、ＨｇＳ、ＨｇＳｅ、ＨｇＴｅ、ＰｂＳｅ、ＰｂＳ、ＧａＮ、ＧａＰ、ＧａＡｓ、ＡｌＮ、ＡｌＰ、ＡｌＡｓ、ＩｎＮ、ＩｎＰ、ＩｎＡｓ、ＣｄＳｅＳ、ＣｄＳｅＴｅ、ＣｄＳＴｅ、ＺｎＳｅＳ、ＺｎＳｅＴｅ、ＺｎＳＴｅ、ＨｇＳｅＳ、ＨｇＳｅＴｅ、ＨｇＳＴｅ、ＣｄＺｎＳ、ＣｄＺｎＳｅ、ＣｄＺｎＴｅ、ＣｄＨｇＳ、ＣｄＨｇＳｅ、ＣｄＨｇＴｅ、ＨｇＺｎＳ、ＨｇＺｎＳｅ、ＨｇＺｎＴｅ、ＣｄＺｎＳｅＳ、ＣｄＺｎＳｅＴｅ、ＣｄＺｎＳＴｅ、ＣｄＨｇＳｅＳ、ＣｄＨｇＳｅＴｅ、ＣｄＨｇＳＴｅ、ＨｇＺｎＳｅＳ、ＨｇＺｎＳｅＴｅ、ＨｇＺｎＳＴｅ、ＧａＮＰ、ＧａＮＡｓ、ＧａＰＡｓ、ＡｌＮＰ、ＡｌＮＡｓ、ＡｌＰＡｓ、ＩｎＮＰ、ＩｎＮＡｓ、ＩｎＰＡｓ、ＩｎＧａＮ、ＧａＡｌＮＰ、ＧａＡｌＮＡｓ、ＧａＡｌＰＡｓ、ＧａＩｎＮＰ、ＧａＩｎＮＡｓ、ＧａＩｎＰＡｓ、ＩｎＡｌＮＰ、ＩｎＡｌＮＡｓ、またはＩｎＡｌＰＡｓなどが挙げられ、最終的に化合物半導体部分１１を構成する材料が選択される。 The core portion 24 is made of a compound semiconductor material, and constitutes the compound semiconductor portion 11 by the manufacturing method of the present invention. Examples of the compound semiconductor material constituting the core portion 24 include CuIn x Ga 1-x (Se y S 1-y ) 2 (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), CuAl x In 1-x (Se y S 1-y ) 2 (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), CuAl x Ga 1-x (Se y S 1-y ) 2 (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), AgIn x Ga 1-x (Se y S 1-y ) 2 (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), AgAl x In 1-x (Se y S 1-y ) 2 (0 ≦ x ≦ 1 , 0 ≦ y ≦ 1), AgAl x Ga 1-x (Se y S 1-y ) 2 (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), Cu 2 ZnSn (Se x S 1-x ) 4 ( 0 ≦ x ≦ 1), CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, PbSe, PbS, GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, CdSeS CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, InGaN, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs, and finally semiconductors Part The material making up the minute 11 is selected.
配位子部分２５は、有機材料からなり、ナノ粒子２１を溶媒２３中に分散させる役割を主に有する。核部分２４と配位子部分２５とは、物理吸着等で接していてもよいし、共有結合または配位結合等で化学的に結合していてもよい。配位子部分２５を構成する有機材料（以下では「配位子材料」と記す）は、例えば、ｎ−ヘキサンセレノール、ｎ−オクタンセレノール、ｎ−デカンセレノール、またはｎ−ドデカンセレノール等のセレノール基を有していれば良く、ｎ−ヘキサンチオール、ｎ−オクタンチオール、ｎ−デカンチオール、ｎ−ドデカンチオール、またはメチルベンゼンチオール等のチオール基を有していれば良く、ｎ−プロピルトリメトキシシラン、ｎ−プロピルトリエトキシシラン、ｎ−プロピルトリクロロシラン、ｎ−アミノプロピルトリメトキシシラン、またはフェニルトリメトシシシラン等のアルコキシシリル基またはクロロシリル基を有していれば良く、ｎ−オクタデシルフォスフォニックアシッド等のホスホン酸基を有していれば良い。 The ligand portion 25 is made of an organic material, and mainly has a role of dispersing the nanoparticles 21 in the solvent 23. The nucleus portion 24 and the ligand portion 25 may be in contact with each other by physical adsorption or the like, or may be chemically bonded by a covalent bond or a coordinate bond. The organic material constituting the ligand portion 25 (hereinafter referred to as “ligand material”) is, for example, n-hexane selenol, n-octane selenol, n-decane selenol, or n-dodecane selenol. As long as it has a thiol group such as n-hexanethiol, n-octanethiol, n-decanethiol, n-dodecanethiol, or methylbenzenethiol. It only needs to have an alkoxysilyl group or a chlorosilyl group such as propyltrimethoxysilane, n-propyltriethoxysilane, n-propyltrichlorosilane, n-aminopropyltrimethoxysilane, or phenyltrimethoxysilane, and n-octadecyl What is necessary is just to have phosphonic acid groups, such as a phosphonic acid.
配位子材料は、核部分２４を構成する化合物半導体材料と結合可能な官能基を有することが好ましく、これにより、核部分２４と配位子部分２５との間に強固な結合が形成される。核部分２４を構成する化合物半導体材料がセレン、硫黄、または銀等を含むときには、配位子材料はセレノール基またはチオール基を有することが好ましい。核部分２４を構成する化合物半導体材料がインジウム、銀、または銅等を含むときには、配位子材料はアルコキシシリル基またはクロロシリル基から生じるシラノール基を有することが好ましい。核部分２４を構成する化合物半導体材料がアルミニウム等を含むときには、配位子材料はホスホン酸基を含むことが好ましい。 The ligand material preferably has a functional group capable of binding to the compound semiconductor material constituting the core portion 24, whereby a strong bond is formed between the core portion 24 and the ligand portion 25. . When the compound semiconductor material constituting the core portion 24 contains selenium, sulfur, silver or the like, the ligand material preferably has a selenol group or a thiol group. When the compound semiconductor material constituting the core portion 24 contains indium, silver, copper, or the like, the ligand material preferably has a silanol group generated from an alkoxysilyl group or a chlorosilyl group. When the compound semiconductor material constituting the core portion 24 contains aluminum or the like, the ligand material preferably contains a phosphonic acid group.
また、配位子材料は、溶媒２３の種類によってナノ粒子２１を分散させる能力が異なるため、以下に述べる溶媒２３の種類に応じて適宜選択されることが好ましい。 In addition, since the ligand material has a different ability to disperse the nanoparticles 21 depending on the type of the solvent 23, it is preferable that the ligand material is appropriately selected according to the type of the solvent 23 described below.
このようなナノ粒子２１の作製方法は特に限定されない。核部分２４の作製手法については、例えば、化合物半導体材料の原料となる各プリカーサ（前駆体）を使って溶媒中でナノサイズの化合物半導体材料を化学合成する方法であってもよいし、化合物半導体材料を物理的に粉砕して微細化する方法であってもよい。また、配位子部分２５の作製方法については、例えば、核部分２４と配位子材料を溶媒中で反応させる液相反応法であってもよいし、核部分２４を配位子材料の蒸気と反応させる気相反応法であっても良い。 The production method of such nanoparticles 21 is not particularly limited. The method for producing the core portion 24 may be, for example, a method of chemically synthesizing a nanosized compound semiconductor material in a solvent using each precursor (precursor) that is a raw material of the compound semiconductor material, or a compound semiconductor A method of physically pulverizing the material to refine it may be used. The method for producing the ligand portion 25 may be, for example, a liquid phase reaction method in which the core portion 24 and the ligand material are reacted in a solvent, or the core portion 24 is vaporized from the ligand material. May be a gas phase reaction method.
溶媒２３は、メタノール、またはエタノール等のアルコール系溶媒であっても良いし、ヘキサン、オクタン、デカン、またはドデカン等のアルキル系溶媒であっても良いし、ベンゼン、またはトルエン等の芳香族系溶媒であってもよい。溶媒２３は、このような有機溶媒に限定されず、酸性、中性、または塩基性を示す水系溶媒であってもよい。溶媒２３の種類は、ナノ粒子２１または有機高分子材料２２などの各特性に応じて選択されればよく、ナノ粒子２１が当該溶媒２３などにより分解または酸化等の反応を起こさないような材料であることが好ましい。例えば、ナノ粒子２１または有機高分子材料２２が酸化されやすい場合には、溶媒２３としては、蒸留等の手法で脱水した有機溶媒、または窒素バブリング等の処理で脱酸素した有機溶媒を用いることが好ましい。 The solvent 23 may be an alcohol solvent such as methanol or ethanol, an alkyl solvent such as hexane, octane, decane, or dodecane, or an aromatic solvent such as benzene or toluene. It may be. The solvent 23 is not limited to such an organic solvent, and may be an aqueous solvent showing acidity, neutrality, or basicity. The kind of solvent 23 should just be selected according to each characteristic, such as the nanoparticle 21 or the organic polymer material 22, and is a material which the nanoparticle 21 does not raise | generate reaction of decomposition | disassembly or oxidation by the said solvent 23, etc. Preferably there is. For example, when the nanoparticles 21 or the organic polymer material 22 are easily oxidized, the solvent 23 may be an organic solvent dehydrated by a technique such as distillation or an organic solvent deoxygenated by a process such as nitrogen bubbling. preferable.
なお、核部分２４と配位子部分２５とが物理吸着等の弱い力で接していた場合、超音波等を用いた強力な撹拌手法を用いて溶液２００を調製すると核部分２４と配位子部分２５との接合が解除されるおそれがある。そのため、溶液調製プロセスＳ１におけるナノ粒子２１と有機高分子材料２２との攪拌手法には留意する必要がある。 When the core portion 24 and the ligand portion 25 are in contact with each other with a weak force such as physical adsorption, the core portion 24 and the ligand portion can be obtained by preparing the solution 200 using a powerful stirring method using ultrasonic waves or the like. There is a possibility that the joint with the portion 25 is released. Therefore, it is necessary to pay attention to the stirring method of the nanoparticles 21 and the organic polymer material 22 in the solution preparation process S1.
溶液調製プロセスＳ１では、最終的に溶液２００が調製できればよく、溶液２００の調製手法および溶液２００を調製する順序は問題とならない。例えば、ナノ粒子２１の溶液と有機高分子材料２２の溶液とを別々に調製してこれらを混合しても良く、ナノ粒子２１と有機高分子材料２２とを同一溶媒中で同時に分散または溶解させて溶液２００を調製しても良い。または、ナノ粒子２１の溶液と有機高分子材料２２の溶液とを別々に調製し、次の塗布プロセスＳ２時にこれらの溶液を別々に塗布して、塗布プロセスＳ２を行うと同時に溶液２００を調製しても良い。 In the solution preparation process S1, it is sufficient if the solution 200 can be finally prepared, and the preparation method of the solution 200 and the order of preparing the solution 200 do not matter. For example, a solution of the nanoparticles 21 and a solution of the organic polymer material 22 may be prepared separately and mixed, and the nanoparticles 21 and the organic polymer material 22 may be simultaneously dispersed or dissolved in the same solvent. The solution 200 may be prepared. Alternatively, the solution of the nanoparticles 21 and the solution of the organic polymer material 22 are separately prepared, and these solutions are separately applied during the next coating process S2, and the solution 200 is prepared simultaneously with the coating process S2. May be.
−塗布プロセス−
続いて、溶液２００を基板に塗布する。塗布前に基板上の不純物を除去することが好ましく、たとえば基板に対して超音波洗浄またはＵＶオゾンアッシング等の洗浄処理を行うことが好ましい。溶液２００の塗布方法には、スクリーン印刷法、キャスト法、ドクターブレードコート法、ディップ法、またはスピンコート法など様々な手法があるが、このいずれの手法を用いても良く、目的に応じた塗布手法を選択すればよい。塗布プロセスＳ２の後、乾燥プロセスＳ３に移る。
-Coating process-
Subsequently, the solution 200 is applied to the substrate. It is preferable to remove impurities on the substrate before coating. For example, it is preferable to perform a cleaning process such as ultrasonic cleaning or UV ozone ashing on the substrate. There are various methods for applying the solution 200, such as a screen printing method, a casting method, a doctor blade coating method, a dip method, or a spin coating method. Any of these methods may be used, and an application according to the purpose is performed. A method may be selected. After the coating process S2, the process proceeds to the drying process S3.
−乾燥プロセス−
乾燥プロセスＳ３は、基板上の塗布膜から溶媒を除去することを目的とする。乾燥プロセスＳ３を経ずに次の焼成プロセスＳ４を行った場合、溶媒の突沸等により、得られた化合物半導体層に多数のボイドが生じてしまう恐れがある。
-Drying process-
The purpose of the drying process S3 is to remove the solvent from the coating film on the substrate. When the next baking process S4 is performed without passing through the drying process S3, a large number of voids may be generated in the obtained compound semiconductor layer due to bumping of the solvent or the like.
乾燥プロセスＳ３では、加熱、減圧、気体によるブロー、または自然乾燥等を行なって、基板上の塗布膜から溶媒を除去する。これらの手法を組み合わせて乾燥プロセスＳ３を行なっても良いし、これらの手法のいずれかを用いて乾燥プロセスＳ３を行なっても良い。しかし、どのような手法を用いて乾燥プロセスＳ３を行なう場合でも、溶媒を緩やかに除去することが肝要である。溶媒を急速に除去すると、溶媒の突沸が起こり、得られた化合物半導体層に多数のボイドが生じてしまう恐れがある。 In the drying process S3, the solvent is removed from the coating film on the substrate by performing heating, decompression, blowing with gas, or natural drying. The drying process S3 may be performed by combining these methods, or the drying process S3 may be performed using any of these methods. However, it is important to remove the solvent gently regardless of which method is used to perform the drying process S3. When the solvent is removed rapidly, the solvent bumps, and there is a possibility that many voids are generated in the obtained compound semiconductor layer.
−焼成プロセス−
最後に、焼成プロセスＳ４を行う。焼成プロセスＳ４では、配位子部分２５の脱離、配位子部分２５の脱離に伴う膜内での空隙の形成、核部分２４の結晶成長、および有機高分子材料２２の軟化による空隙の埋め込みが起こる。
-Baking process-
Finally, a firing process S4 is performed. In the firing process S4, the elimination of the ligand portion 25, the formation of voids in the film accompanying the elimination of the ligand portion 25, the crystal growth of the core portion 24, and the void formation due to the softening of the organic polymer material 22 are performed. Embedding occurs.
詳しくは、配位子部分２５は、加温によって核部分２４から脱離し、ある温度以上で核部分２４から容易に脱離する。配位子部分２５は核部分２４同士の凝集を防ぐ役割を担っているため、配位子部分２５の消失に伴って核部分２４同士が凝集して結晶化が起こる。これにより、核部分２４は大きく成長し、最終的に化合物半導体部分１１を形成する。 Specifically, the ligand portion 25 is desorbed from the nucleus portion 24 by heating, and is easily desorbed from the nucleus portion 24 at a certain temperature or higher. Since the ligand portion 25 plays a role of preventing aggregation between the nucleus portions 24, the nucleus portions 24 aggregate together with the disappearance of the ligand portion 25, and crystallization occurs. As a result, the core portion 24 grows greatly and finally forms the compound semiconductor portion 11.
また、核部分２４からの配位子部分２５の脱離によって、配位子部分２５が存在していた部分が空隙となる。この空隙部分の一部は核部分２４の結晶成長により埋められるが、残りの部分は空隙として残る。ここで、配位子部分２５が核部分２４から脱離する程度の温度になると有機高分子材料２２は軟化するため、軟化した有機高分子材料２２が空隙として残った部分に埋め込まれて当該空隙が消失する。 Further, due to the elimination of the ligand portion 25 from the core portion 24, the portion where the ligand portion 25 was present becomes a void. A part of this void portion is filled by crystal growth of the core portion 24, but the remaining portion remains as a void. Here, since the organic polymer material 22 is softened at a temperature at which the ligand portion 25 is desorbed from the core portion 24, the softened organic polymer material 22 is embedded in the remaining portion as a void. Disappears.
焼成条件は特に限定されない。しかし、焼成温度が５００℃を超えると、有機高分子材料２２の分解または特性劣化が懸念される。よって、焼成温度は５００℃以下が好適である。また、焼成温度は、核部分２４と配位子部分２５との間に働く結合力（上述の物理吸着力または化学結合力）が解離する温度以上であることが好ましい。結合力が解離する温度は核部分２４の材料および配位子部分２５の材料などに依存するため一概に言えないが、概ね１５０℃以上であれば良い。以上を考慮すれば、焼成温度は、１５０℃以上５００℃以下であることが好ましく、より好ましくは２５０℃以上５００℃以下である。焼成温度が２５０℃以上５００℃以下であれば、化合物半導体層の作製時間の長期化を招くことなく比較的良質な化合物半導体層を提供できるという効果も得られる。 The firing conditions are not particularly limited. However, when the firing temperature exceeds 500 ° C., there is a concern that the organic polymer material 22 may be decomposed or deteriorated in characteristics. Therefore, the firing temperature is preferably 500 ° C. or lower. The firing temperature is preferably equal to or higher than the temperature at which the bonding force (the above-described physical adsorption force or chemical bonding force) acting between the core portion 24 and the ligand portion 25 is dissociated. The temperature at which the binding force dissociates cannot be generally described because it depends on the material of the core portion 24 and the material of the ligand portion 25, but may be about 150 ° C. or higher. Considering the above, the firing temperature is preferably 150 ° C. or higher and 500 ° C. or lower, more preferably 250 ° C. or higher and 500 ° C. or lower. When the firing temperature is 250 ° C. or higher and 500 ° C. or lower, an effect that a relatively good quality compound semiconductor layer can be provided without prolonging the manufacturing time of the compound semiconductor layer is also obtained.
焼成プロセスＳ４での加熱方法としては、たとえば、基板をホットプレート上に置いて加熱してもよいし、基板をオーブン中で加熱しても良い。 As a heating method in the baking process S4, for example, the substrate may be placed on a hot plate and heated, or the substrate may be heated in an oven.
焼成プロセスＳ４は、溶液調製プロセスＳ１、塗布プロセスＳ２、および乾燥プロセスＳ３よりも高温で行なわれるので、大気雰囲気下でなく不活性雰囲気下で行なわれることが好ましい。焼成温度が５００℃に近い高温である場合、焼成プロセスＳ４を大気下で行なうと、有機高分子材料２２が酸素と反応して炭化してしまう恐れがあり、また化合物半導体材料からなる核部分２４でも容易に酸化が進んで化合物半導体材料が本来有する特性を失うおそれがある。 Since the baking process S4 is performed at a higher temperature than the solution preparation process S1, the coating process S2, and the drying process S3, it is preferably performed in an inert atmosphere instead of an air atmosphere. When the firing temperature is a high temperature close to 500 ° C., when the firing process S4 is performed in the atmosphere, the organic polymer material 22 may react with oxygen and carbonize, and the core portion 24 made of a compound semiconductor material. However, there is a risk that oxidation proceeds easily and the characteristics inherent to the compound semiconductor material are lost.
なお、焼成プロセスＳ４以外の各プロセスにおいても、必要であれば、窒素またはアルゴン等の不活性雰囲気下で各処理を行ってもよい。不活性雰囲気下での処理が必要な状況としては、例えばナノ粒子２１または有機高分子材料２２として水または酸素に弱い材料を用いた場合等があげられる。 In each process other than the firing process S4, each process may be performed under an inert atmosphere such as nitrogen or argon if necessary. As a situation where treatment under an inert atmosphere is necessary, for example, a case where a material that is weak against water or oxygen is used as the nanoparticle 21 or the organic polymer material 22.
このように、焼成プロセスＳ４において、核部分２４が結晶成長して化合物半導体部分１１を形成するとともに、有機高分子材料２２が軟化して隣り合う結晶粒（結晶粒は化合物半導体部分１１を構成する）の間を充填する。そのため、塗布プロセスＳ２、乾燥プロセスＳ３、および焼成プロセスＳ４を繰り返し行なわずとも、クラックの発生を抑制した膜厚の大きな化合物半導体層１００が得られる。よって、スループットの低下を防止できる。それだけでなく、化合物半導体層１００におけるクラックの発生を防止できるので、面内方向の導電性などの特性に優れた化合物半導体層１００が得られる。このようにして得られた化合物半導体層１００を用いて化合物薄膜太陽電池を作製すれば、リーク電流が抑制された太陽電池を提供できる。以下では、本発明の化合物半導体層１００を化合物薄膜太陽電池に応用した例を示す。 Thus, in the firing process S4, the core portion 24 grows crystals to form the compound semiconductor portion 11, and the organic polymer material 22 softens to make adjacent crystal grains (the crystal grains constitute the compound semiconductor portion 11). ). Therefore, the compound semiconductor layer 100 having a large film thickness in which the generation of cracks is suppressed can be obtained without repeating the coating process S2, the drying process S3, and the baking process S4. Thus, a decrease in throughput can be prevented. In addition, since generation of cracks in the compound semiconductor layer 100 can be prevented, the compound semiconductor layer 100 having excellent characteristics such as in-plane conductivity can be obtained. If a compound thin film solar cell is produced using the compound semiconductor layer 100 obtained in this way, a solar cell in which leakage current is suppressed can be provided. Below, the example which applied the compound semiconductor layer 100 of this invention to the compound thin film solar cell is shown.
〔化合物薄膜太陽電池〕
図４は、本発明の化合物半導体層を用いた、化合物薄膜太陽電池３００の概略断面図である。
[Compound thin film solar cells]
FIG. 4 is a schematic cross-sectional view of a compound thin-film solar cell 300 using the compound semiconductor layer of the present invention.
図４に示す化合物薄膜太陽電池３００は、太陽電池の最小構成である第１電極３２、化合物半導体層３３、および第２電極３６を備え、基板３１、バッファ層３４、および窓層３５をさらに備えている。 A compound thin-film solar cell 300 shown in FIG. 4 includes a first electrode 32, a compound semiconductor layer 33, and a second electrode 36, which are the minimum configuration of the solar cell, and further includes a substrate 31, a buffer layer 34, and a window layer 35. ing.
次に、化合物薄膜太陽電池３００を構成するそれぞれの構成要素について説明する。
第１電極３２、および第２電極３６は、太陽電池内で生成したキャリアを取り出す役割を担っている。これらの電極の材料は、キャリア輸送損失をできるだけ防ぐ目的から、抵抗率が低いものが好ましい。また、同様の理由から、第１電極３２に接する化合物半導体層３３と、第２電極３６に接する窓層３５との間では、良好なオーミック接触を形成するものが好ましい。第１電極３２、および第２電極３６に用いる材料としては、特に制限はない。第１電極３２、および第２電極３６は、例えば、Ｍｏ、Ａｕ、Ａｇ、Ｃｕ、またはＡｌ等の金属電極であっても良いし、ＩＴＯ、またはＺｎＯ等の酸化物電極であっても良い。これらの電極は、抵抗加熱または電子ビームなどの真空蒸着法、スパッタリング法、ＭＯＣＶＤ法、またはＭＢＥ法等によって形成される。
Next, each component which comprises the compound thin film solar cell 300 is demonstrated.
The first electrode 32 and the second electrode 36 have a role of taking out carriers generated in the solar cell. For the purpose of preventing carrier transport loss as much as possible, those electrodes having a low resistivity are preferable. For the same reason, it is preferable to form a good ohmic contact between the compound semiconductor layer 33 in contact with the first electrode 32 and the window layer 35 in contact with the second electrode 36. The material used for the first electrode 32 and the second electrode 36 is not particularly limited. The first electrode 32 and the second electrode 36 may be metal electrodes such as Mo, Au, Ag, Cu, or Al, or may be oxide electrodes such as ITO or ZnO. These electrodes are formed by resistance heating or vacuum deposition such as electron beam, sputtering, MOCVD, MBE, or the like.
化合物半導体層３３は、太陽光を吸収してキャリアを発生させる役割を担っている。この製造方法については、本発明に係る化合物半導体層の製造方法で述べたとおりである。 The compound semiconductor layer 33 has a role of absorbing carriers and generating carriers. This manufacturing method is as described in the method for manufacturing a compound semiconductor layer according to the present invention.
バッファ層３４は、化合物半導体層３３と窓層３５との間の接合を緩衝する役割を果たす。バッファ層３４が形成されていることにより、シャント抵抗の増大および、キャリア再結合の低減等の効果が見込まれる。但し、そのような効果を得るために、化合物半導体層３３または窓層３５とのバンドラインナップ等を考慮して、適切なバッファ層材料を選択する必要がある。バッファ層３４の材料としては、たとえば、ＣｄＳ、ＺｎＯ、ＺｎＳ、ＺｎＭｇＯ、またはＺｎＩｎＳｅ2等が挙げられる。また、バッファ層３４の作製手法としては、たとえば、ＣＢＤ法（Ｃｈｅｍｉｃａｌ Ｂａｔｈ Ｄｅｐｏｓｉｔｉｏｎ法）と呼ばれる溶液成長法、スパッタリング法、またはＭＯＣＶＤ法等が挙げられるが、そのいずれの手法を用いてもよい。 The buffer layer 34 serves to buffer the junction between the compound semiconductor layer 33 and the window layer 35. By forming the buffer layer 34, effects such as an increase in shunt resistance and a reduction in carrier recombination are expected. However, in order to obtain such an effect, it is necessary to select an appropriate buffer layer material in consideration of a band lineup with the compound semiconductor layer 33 or the window layer 35 and the like. Examples of the material of the buffer layer 34 include CdS, ZnO, ZnS, ZnMgO, or ZnInSe 2 . In addition, examples of a method for manufacturing the buffer layer 34 include a solution growth method called a CBD method (Chemical Bath Deposition method), a sputtering method, an MOCVD method, and the like, and any of these methods may be used.
窓層３５は、化合物半導体層３３とは逆の極性を有する半導体材料から形成されており、化合物半導体層３３で吸収される太陽光の大半を透過する。窓層３５の材料としては、たとえばＡｌ、ＢまたはＩｎを適量ドーピングしたＺｎＯ等が用いられる。また、窓層３５の作製手法としては、ＣＢＤ法、スパッタリング法、またはＭＯＣＶＤ法等が挙げられる。 The window layer 35 is formed of a semiconductor material having a polarity opposite to that of the compound semiconductor layer 33 and transmits most of the sunlight absorbed by the compound semiconductor layer 33. As the material of the window layer 35, for example, ZnO doped with an appropriate amount of Al, B, or In is used. Moreover, as a manufacturing method of the window layer 35, CBD method, sputtering method, MOCVD method, etc. are mentioned.
本発明の化合物薄膜太陽電池３００は、基本的には上記構成要素を備えていれば良いが、上記構成要素に加えて、窓層３５上に設けられた反射防止層、または封止層などを備えていても良い。反射防止層はＭｇＦ2またはＳｉＯ2等からなれば良く、封止層はＥＶＡ（エチレンビニルアセテート）樹脂またはエポキシ樹脂等からなれば良い。 The compound thin-film solar cell 300 of the present invention basically only needs to include the above-described components, but in addition to the above-described components, an antireflection layer or a sealing layer provided on the window layer 35 is provided. You may have. The antireflection layer may be made of MgF 2 or SiO 2 , and the sealing layer may be made of EVA (ethylene vinyl acetate) resin or epoxy resin.
図４に示す化合物薄膜太陽電池３００の代表的な構成として、基板３１がガラス板であり、第１電極３２がＭｏからなり、化合物半導体層３３がＣＩＧＳを化合物半導体部分に用いたｐ型半導体層であり、バッファ層３４がＺｎＯからなり、窓層３５がＡｌドープＺｎＯからなり、第２電極３６がＡｌからなるものが挙げられる。このような構造は、基板に対して上部から入射した光を吸収できるサブストレイト型といわれる構造である。 As a typical configuration of the compound thin film solar cell 300 shown in FIG. 4, the substrate 31 is a glass plate, the first electrode 32 is made of Mo, and the compound semiconductor layer 33 is a p-type semiconductor layer using CIGS as a compound semiconductor portion. And the buffer layer 34 is made of ZnO, the window layer 35 is made of Al-doped ZnO, and the second electrode 36 is made of Al. Such a structure is a structure called a substrate type that can absorb light incident on the substrate from above.
本発明に係る化合物薄膜太陽電池としては、図４に示す化合物薄膜太陽電池３００に限定されず、図５に示す化合物薄膜太陽電池４００であっても良い。図５は、本発明に係る化合物薄膜太陽電池４００の概略断面図である。 The compound thin film solar cell according to the present invention is not limited to the compound thin film solar cell 300 shown in FIG. 4, and may be a compound thin film solar cell 400 shown in FIG. 5. FIG. 5 is a schematic cross-sectional view of a compound thin film solar cell 400 according to the present invention.
図５に示す化合物薄膜太陽電池４００では、ガラスからなる基板４１上に、ＡｌドープＺｎＯからなる窓層４２、ＺｎＯからなるバッファ層４３、ＣＩＧＳを化合物半導体部分としたｐ型半導体からなる化合物半導体層４４、およびＭｏからなる第２電極４５が順次形成され、キャリア取り出し用電極としてＡｌからなる第１電極４６が窓層４２上に形成されている。このような構造は、基板側から入射した光を吸収するスーパストレイト型構造と呼ばれる。なお、基板４１、窓層４２、バッファ層４３、化合物半導体層４４、第２電極４５、および第１電極４６の各材料は上記材料に限定されない。 In the compound thin-film solar cell 400 shown in FIG. 5, a compound semiconductor layer made of a p-type semiconductor having a window layer 42 made of Al-doped ZnO, a buffer layer 43 made of ZnO, and CIGS as a compound semiconductor portion on a substrate 41 made of glass. 44 and a second electrode 45 made of Mo are sequentially formed, and a first electrode 46 made of Al is formed on the window layer 42 as a carrier extraction electrode. Such a structure is called a super-straight structure that absorbs light incident from the substrate side. In addition, each material of the board | substrate 41, the window layer 42, the buffer layer 43, the compound semiconductor layer 44, the 2nd electrode 45, and the 1st electrode 46 is not limited to the said material.
いずれにしても、本発明の化合物薄膜太陽電池は、先に述べた本発明の化合物半導体層を含んでいればよく、その他の構成によって制限されない。 In any case, the compound thin film solar cell of the present invention is not limited by other configurations as long as it includes the compound semiconductor layer of the present invention described above.
以下、実施例を用いて、本発明の化合物半導体層およびその製造方法についてさらに詳細に説明する。 Hereinafter, the compound semiconductor layer and the manufacturing method thereof of the present invention will be described in more detail using examples.
〔実施例１〕
図６は、実施例１に係る化合物半導体層の製造方法における溶液の調製方法を示す模式図である。図７（ａ）、図７（ｃ）および図７（ｄ）は、実施例１に係る化合物半導体層の製造方法を工程順に示す概略図であり、図７（ｂ）は、図７（ａ）に示すＶＩＩＢ−ＶＩＩＢ線における概略断面図である。
[Example 1]
6 is a schematic diagram illustrating a solution preparation method in the method for manufacturing a compound semiconductor layer according to Example 1. FIG. FIG. 7A, FIG. 7C, and FIG. 7D are schematic views showing the manufacturing method of the compound semiconductor layer according to Example 1 in the order of steps, and FIG. It is a schematic sectional drawing in the VIIB-VIIB line shown to).
まず、図６に示すように、ＣｕＩｎＳｅ2からなる核部分５４と、核部分５４の周囲を取り囲みｎ−オクタンセレノールからなる配位子部分５５とからなるナノ粒子５１（直径が約１０ｎｍである）を準備し、このナノ粒子５１を無水トルエン溶媒５３に加えて３０分間撹拌した。これにより、ナノ粒子５１の濃度が１０ｗｔ％である無水トルエン溶液５０１を調製した。また、無水トルエン溶媒５３にポリ（３−ヘキシルチオフェン）からなる有機高分子材料５２を加えて撹拌し、ポリ（３−ヘキシルチオフェン）の濃度が１ｗｔ％である無水トルエン溶液５０２を調製した。その後、ナノ粒子５１の無水トルエン溶液５０１とポリ（３−ヘキシルチオフェン）の無水トルエン溶液５０２とを混合して、ナノ粒子５１の核部分５４と有機高分子材料５２との質量混合比が１：０．２５である混合溶液５０３を調製した。このようにして溶液調製プロセスを行なった。 First, as shown in FIG. 6, nanoparticles 51 (having a diameter of about 10 nm) comprising a core portion 54 made of CuInSe 2 and a ligand portion 55 surrounding the core portion 54 and made of n-octane selenol. The nanoparticles 51 were added to the anhydrous toluene solvent 53 and stirred for 30 minutes. This prepared the anhydrous toluene solution 501 whose concentration of the nanoparticle 51 is 10 wt%. Further, an organic polymer material 52 made of poly (3-hexylthiophene) was added to the anhydrous toluene solvent 53 and stirred to prepare an anhydrous toluene solution 502 having a poly (3-hexylthiophene) concentration of 1 wt%. Thereafter, the anhydrous toluene solution 501 of the nanoparticles 51 and the anhydrous toluene solution 502 of poly (3-hexylthiophene) are mixed, and the mass mixing ratio of the core portion 54 of the nanoparticles 51 and the organic polymer material 52 is 1: A mixed solution 503 of 0.25 was prepared. Thus, the solution preparation process was performed.
続いて、塗布プロセスを行った。まず、エッチングによって１ｃｍ×１ｃｍの領域に３μｍの深さの開口部が形成されたガラス基板５６を用意し、そのガラス基板５６に対して有機溶媒での超音波洗浄処理とＵＶオゾン洗浄処理とを行ってガラス基板５６上の不純物を完全に除去した。その後、図７（ａ）〜（ｂ）で示すように、ガラス基板５６の開口部に調製された混合溶液５０３を滴下して深さ３μｍの開口部を混合溶液で満たした。 Subsequently, a coating process was performed. First, a glass substrate 56 in which an opening having a depth of 3 μm is formed in a 1 cm × 1 cm region by etching is prepared, and the glass substrate 56 is subjected to an ultrasonic cleaning process using an organic solvent and a UV ozone cleaning process. The impurities on the glass substrate 56 were completely removed. Thereafter, as shown in FIGS. 7A to 7B, the prepared mixed solution 503 was dropped into the opening of the glass substrate 56 to fill the opening having a depth of 3 μm with the mixed solution.
その後、ガラス基板５６を窒素雰囲気下で１５分静置し、無水トルエン溶媒を簡易的に乾燥させた。その後、図７（ｃ）に示すように、ホットプレート５１１上でガラス基板５６を１２０℃で１時間加熱した。これにより、無水トルエン溶媒が完全に除去され、乾燥プロセスが完了した。 Thereafter, the glass substrate 56 was allowed to stand for 15 minutes under a nitrogen atmosphere, and the anhydrous toluene solvent was simply dried. Then, as shown in FIG.7 (c), the glass substrate 56 was heated at 120 degreeC on the hotplate 511 for 1 hour. This completely removed the anhydrous toluene solvent and completed the drying process.
最後に、図７（ｄ）に示すように、窒素雰囲気下、ホットプレート５１１上でガラス基板５６を２５０℃で１時間加熱した。これにより、焼成処理が行なわれ、化合物半導体部分と有機高分子部分とからなる化合物半導体層５０４を作製した。 Finally, as shown in FIG. 7D, the glass substrate 56 was heated on a hot plate 511 at 250 ° C. for 1 hour in a nitrogen atmosphere. As a result, a baking treatment was performed, and a compound semiconductor layer 504 including a compound semiconductor portion and an organic polymer portion was produced.
上記処理のうちガラス基板５６の洗浄処理以外はすべて窒素雰囲気下で行った。
このようにして作製した化合物半導体層５０４を透過型の顕微鏡で観察すると、図１０（ａ）に示すようにクラックのない良好な膜が形成されていることが確認できた。化合物半導体層５０４の膜厚は約２μｍであった。また、化合物半導体層５０４についてホール効果測定による電気的評価を行うと、キャリア密度が４．５×１０14個／ｃｍ3であり、移動度が１．２５×１０1ｃｍ2／Ｖ・ｓであり、良好な特性を示した。
All of the above processes except for the cleaning process of the glass substrate 56 were performed in a nitrogen atmosphere.
When the compound semiconductor layer 504 thus produced was observed with a transmission microscope, it was confirmed that a good film without cracks was formed as shown in FIG. The film thickness of the compound semiconductor layer 504 was about 2 μm. Further, when electrical evaluation is performed on the compound semiconductor layer 504 by Hall effect measurement, the carrier density is 4.5 × 10 14 atoms / cm 3 and the mobility is 1.25 × 10 1 cm 2 / V · s. And showed good characteristics.
〔実施例２〕
ナノ粒子５１の核部分５４と有機高分子材料５２との質量混合比が１：０．５である混合溶液を調製したこと以外は実施例１と同様にして、化合物半導体部分と有機高分子部分とからなる化合物半導体層をガラス基板上に形成した。
[Example 2]
The compound semiconductor portion and the organic polymer portion are the same as in Example 1 except that a mixed solution in which the mass mixing ratio of the core portion 54 of the nanoparticle 51 and the organic polymer material 52 is 1: 0.5 is prepared. A compound semiconductor layer consisting of was formed on a glass substrate.
このようにして作製した化合物半導体層を透過型の顕微鏡で観察すると、図１０（ａ）に示すようにクラックのない良好な膜が形成されていた。化合物半導体層の膜厚は約２μｍであった。また、化合物半導体層についてホール効果測定による電気的評価を行うと、キャリア密度１．２×１０15個／ｃｍ3であり、移動度が３．４×１０-2ｃｍ2／Ｖ・ｓであり、良好な特性を示した。 When the thus prepared compound semiconductor layer was observed with a transmission microscope, a good film without cracks was formed as shown in FIG. The film thickness of the compound semiconductor layer was about 2 μm. Further, when electrical evaluation is performed on the compound semiconductor layer by Hall effect measurement, the carrier density is 1.2 × 10 15 atoms / cm 3 and the mobility is 3.4 × 10 −2 cm 2 / V · s. Showed good properties.
〔比較例１〕
溶液調製プロセスにおいて溶液をナノ粒子１００％で調整したこと以外は実施例１と同様にして、化合物半導体層をガラス基板上に形成した。
[Comparative Example 1]
A compound semiconductor layer was formed on a glass substrate in the same manner as in Example 1 except that the solution was adjusted with 100% nanoparticles in the solution preparation process.
このようにして作製した膜を透過型の顕微鏡で観察すると、図１０（ｂ）に示すように化合物半導体層にはクラック（図１０（ｂ）におけるライン状の灰色部分）が形成されていた。また、化合物半導体層についてホール効果測定による電気的評価を行ったが、面内方向の電流値が測定限界未満であった。この理由としては、クラックの発生により膜のグレイン間の物理的な接合が失われたためと考えられる。 When the film thus produced was observed with a transmission microscope, cracks (line-shaped gray portions in FIG. 10B) were formed in the compound semiconductor layer as shown in FIG. 10B. Moreover, although electrical evaluation by Hall effect measurement was performed about the compound semiconductor layer, the electric current value of the in-plane direction was less than the measurement limit. The reason for this is thought to be that physical bonding between the film grains was lost due to the occurrence of cracks.
〔実施例３〕
実施例３では、本発明の化合物半導体層を化合物薄膜太陽電池の光吸収層に用いた例を示す。
Example 3
Example 3 shows an example in which the compound semiconductor layer of the present invention is used for a light absorption layer of a compound thin film solar cell.
図８（ａ）は本実施例に係る化合物薄膜太陽電池６００の平面図を示し、図８（ｂ）は図８（ａ）に示すＶＩＩＩＢ−ＶＩＩＩＢ線における断面図である。図９（ａ）〜（ｄ）は、本実施例に係る化合物薄膜太陽電池６００の製造方法を工程順に示す平面図である。 FIG. 8A is a plan view of the compound thin film solar cell 600 according to this example, and FIG. 8B is a cross-sectional view taken along the line VIIIB-VIIIB shown in FIG. 9A to 9D are plan views showing a method of manufacturing the compound thin-film solar cell 600 according to this example in the order of steps.
以下、図８および図９を参照して、本実施例に係る化合物薄膜太陽電池６００の構成およびその製造方法を説明する。 Hereinafter, with reference to FIG. 8 and FIG. 9, the structure of the compound thin film solar cell 600 which concerns on a present Example, and its manufacturing method are demonstrated.
まず、図９（ａ）に示すように、１ｃｍ×１ｃｍの領域に３μｍの深さの開口部６０が形成されたガラス基板（２ｃｍ×２ｃｍ）６１上に、スパッタリングによってＭｏ膜を形成して第１電極６２とした。 First, as shown in FIG. 9A, a Mo film is formed by sputtering on a glass substrate (2 cm × 2 cm) 61 in which an opening 60 having a depth of 3 μm is formed in a 1 cm × 1 cm region. One electrode 62 was used.
続いて、実施例１と同様にしてナノ粒子の核部分であるＣｕＩｎＳｅ2と有機高分子材料であるポリ（３−ヘキシルチオフェン）との質量混合比が１：０．２５である混合溶液を調製し、開口部６０内における第１電極６２上を満たすように混合溶液を滴下した。その後、実施例１と同様の方法によって乾燥および焼成処理を行って、厚さ約２μｍの化合物半導体層６３を得た（図９（ｂ））。 Subsequently, in the same manner as in Example 1, a mixed solution having a mass mixing ratio of CuInSe 2 that is a core part of nanoparticles and poly (3-hexylthiophene) that is an organic polymer material is 1: 0.25. Then, the mixed solution was dropped so as to fill the first electrode 62 in the opening 60. Thereafter, drying and firing were performed in the same manner as in Example 1 to obtain a compound semiconductor layer 63 having a thickness of about 2 μm (FIG. 9B).
続いて、図９（ｃ）に示すように、化合物半導体層６３上にＺｎＯからなるバッファ層６４をスパッタリングによって形成してから、バッファ層６４上にＺｎＯ：Ａｌからなる窓層６５をスパッタリングによって形成した。 Subsequently, as shown in FIG. 9C, a buffer layer 64 made of ZnO is formed on the compound semiconductor layer 63 by sputtering, and then a window layer 65 made of ZnO: Al is formed on the buffer layer 64 by sputtering. did.
最後に、図９（ｄ）に示すようにＡｌ電極（第２電極）６６を形成して、図８（ａ）〜（ｂ）に示す化合物薄膜太陽電池６００を作製した。作製された化合物薄型太陽電池６００の面積は２×２ｍｍであった。 Finally, as shown in FIG. 9 (d), an Al electrode (second electrode) 66 was formed, and a compound thin film solar cell 600 shown in FIGS. 8 (a) to 8 (b) was produced. The area of the manufactured compound thin solar cell 600 was 2 × 2 mm.
このようにして作製した化合物薄膜太陽電池６００に対してＡＭ１．５Ｇの擬似太陽光を照射してセル特性を測定すると、変換効率は０．５３％であった。 When the cell characteristics were measured by irradiating the compound thin film solar cell 600 thus produced with AM1.5G pseudo-sunlight, the conversion efficiency was 0.53%.
〔比較例２〕
化合物半導体層を形成するための溶液をナノ粒子１００％で調製したこと以外は実施例３と同様にして、化合物薄膜太陽電池を形成した。
[Comparative Example 2]
A compound thin film solar cell was formed in the same manner as in Example 3 except that the solution for forming the compound semiconductor layer was prepared with 100% nanoparticles.
作製された化合物薄膜太陽電池に対してＡＭ１．５Ｇの擬似太陽光を照射してセル特性を測定すると、リーク電流が大きく、暗状態および光照射状態のいずれの状態においてもダイオード特性が得られなかった。 When the cell characteristics are measured by irradiating the fabricated compound thin film solar cell with AM1.5G pseudo-sunlight, the leakage current is large and the diode characteristics cannot be obtained in either the dark state or the light irradiation state. It was.
実施例１および２と比較例１とから、有機高分子材料を含有する化合物半導体層では、膜厚が約２μｍという厚膜であってもクラックの発生が抑制されていることが分かった。さらに、実施例１と実施例２とを比較すると、ナノ粒子とポリ（３−ヘキシルチオフェン）との質量混合比が１：０．５である実施例２よりも、ナノ粒子とポリ（３−ヘキシルチオフェン）との質量混合比が１：０．２５である実施例１の方が、化合物半導体層は良好な導電性を有することが分かった。 From Examples 1 and 2 and Comparative Example 1, it was found that in the compound semiconductor layer containing an organic polymer material, the occurrence of cracks was suppressed even when the film thickness was about 2 μm. Furthermore, when Example 1 and Example 2 are compared, compared with Example 2 whose mass mixing ratio of a nanoparticle and poly (3-hexyl thiophene) is 1: 0.5, a nanoparticle and poly (3- It was found that the compound semiconductor layer has better conductivity in Example 1 in which the mass mixing ratio with hexylthiophene) is 1: 0.25.
また、実施例３と比較例２とから、本発明の化合物半導体層を用いて作製した化合物薄膜太陽電池は、有機高分子材料を含有しない従来の化合物半導体層を用いた化合物薄膜太陽電池に比べ、リーク電流が抑制された良好な特性を示すことが分かった。 Moreover, the compound thin film solar cell produced using Example 3 and Comparative Example 2 using the compound semiconductor layer of this invention is compared with the compound thin film solar cell using the conventional compound semiconductor layer which does not contain an organic polymer material. As a result, it was found that the leakage current was suppressed and good characteristics were exhibited.
今回開示された実施の形態および実施例はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
１１ 化合物半導体部分、１２ 有機高分子部分、２１，５１ ナノ粒子、２２，５２ 有機高分子材料、２４ 核部分、２５ 配位子部分、３１，４１，６１ 基板、３２，４２，６２ 第１電極、３３，４４，６３，１００，５０４ 化合物半導体層、３６，４５，６６ 第２電極。 11 Compound semiconductor part, 12 Organic polymer part, 21, 51 Nanoparticle, 22, 52 Organic polymer material, 24 Core part, 25 Ligand part, 31, 41, 61 Substrate, 32, 42, 62 First electrode 33, 44, 63, 100, 504 Compound semiconductor layer, 36, 45, 66 Second electrode.
Claims (13)
隣り合う前記結晶粒の間に充填されている、有機高分子材料からなる有機高分子部分とから構成され、
厚さが１μｍ以上５μｍ以下である、化合物半導体層。 A compound semiconductor portion comprising a plurality of crystal grains, comprising a compound semiconductor material;
An organic polymer portion made of an organic polymer material filled between the adjacent crystal grains ,
A compound semiconductor layer having a thickness of 1 μm or more and 5 μm or less.
前記化合物半導体層は、請求項１〜４のいずれかに記載の化合物半導体層である化合物薄膜太陽電池。 A compound thin film solar cell comprising a substrate and a first electrode, a compound semiconductor layer, and a second electrode provided on the substrate,
The said compound semiconductor layer is a compound thin film solar cell which is a compound semiconductor layer in any one of Claims 1-4 .
化合物半導体材料からなる核部分と前記核部分の周囲を取り囲むｎ−オクタンセレナールからなる配位子部分とを含むナノ粒子と、有機高分子材料とが分散された溶液を調製する工程と、
前記溶液を基板上に塗布してから焼成する工程とを備えた、
厚さが１μｍ以上５μｍ以下である、化合物半導体層の製造方法。 It is a manufacturing method of the compound semiconductor layer in any one of Claims 1-4 , Comprising:
A step of preparing a solution in which nanoparticles including a core portion made of a compound semiconductor material and a ligand portion made of n-octaneselenal surrounding the core portion and an organic polymer material are dispersed;
And a step of applying the solution onto a substrate and then baking.
The manufacturing method of a compound semiconductor layer whose thickness is 1 micrometer or more and 5 micrometers or less.
前記化合物半導体層は、請求項６〜１２のいずれかに記載の化合物半導体層の製造方法によって形成される化合物薄膜太陽電池の製造方法。 A method of manufacturing a compound thin film solar cell by forming a first electrode, a compound semiconductor layer, and a second electrode on a substrate,
The compound semiconductor layer, the manufacturing method of the compound thin film solar cell which is formed by the manufacturing method of a compound semiconductor layer according to any one of claims 6-12.
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