JP6002508B2 - Nitride semiconductor wafer - Google Patents
Nitride semiconductor wafer Download PDFInfo
- Publication number
- JP6002508B2 JP6002508B2 JP2012193047A JP2012193047A JP6002508B2 JP 6002508 B2 JP6002508 B2 JP 6002508B2 JP 2012193047 A JP2012193047 A JP 2012193047A JP 2012193047 A JP2012193047 A JP 2012193047A JP 6002508 B2 JP6002508 B2 JP 6002508B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- acceptor
- buffer
- semiconductor wafer
- nitride semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 28
- 150000004767 nitrides Chemical class 0.000 title claims description 25
- 239000000203 mixture Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 18
- 229910052799 carbon Inorganic materials 0.000 claims description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 7
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 7
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 claims description 3
- 239000000370 acceptor Substances 0.000 description 57
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 29
- 229910002601 GaN Inorganic materials 0.000 description 26
- 230000010287 polarization Effects 0.000 description 26
- 239000003574 free electron Substances 0.000 description 12
- 239000013078 crystal Substances 0.000 description 11
- 238000005259 measurement Methods 0.000 description 10
- 238000011156 evaluation Methods 0.000 description 9
- 238000009413 insulation Methods 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000002994 raw material Substances 0.000 description 5
- 239000011701 zinc Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052742 iron Inorganic materials 0.000 description 3
- 230000002269 spontaneous effect Effects 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 239000011575 calcium Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 239000011572 manganese Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- 229910052784 alkaline earth metal Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 125000000118 dimethyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 238000010893 electron trap Methods 0.000 description 1
- 238000000921 elemental analysis Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
- H01L21/02507—Alternating layers, e.g. superlattice
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02579—P-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02581—Transition metal or rare earth elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Materials Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Description
本発明は、窒化物半導体ウェハに関する。 The present invention relates to a nitride semiconductor wafer.
Si、SiC、GaN等からなる導電性あるいは半絶縁性の半導体基板の(111)面上、あるいはC面〔(0001)面〕上に、高電子移動度トランジスタ(HEMT)などのヘテロ接合を有するデバイス構造を形成する場合、バッファ層に高い絶縁特性が求められる。しかし、単層のバッファ層を用いた場合は、バッファ層内にエネルギー障壁が無く、バッファ層に注入された自由電子が動きやすいため、必ずしも十分な絶縁特性が得られない。 A heterojunction such as a high electron mobility transistor (HEMT) is formed on the (111) plane or the C plane ((0001) plane) of a conductive or semi-insulating semiconductor substrate made of Si, SiC, GaN or the like. When forming a device structure, high insulation characteristics are required for the buffer layer. However, when a single buffer layer is used, there is no energy barrier in the buffer layer, and free electrons injected into the buffer layer easily move, so that sufficient insulation characteristics cannot always be obtained.
絶縁特性を向上させるためには、例えば、窒化アルミニウムガリウム(AlGaN)層と窒化ガリウム(GaN)層とのヘテロ接合を含むバッファ層を用いることが有効であるが、窒化物半導体特有の分極効果のために生じる誘起電荷が、絶縁特性向上の障害となる。c軸方向に積層したAlGaN/GaNへテロ接合構造は、窒化物系半導体結晶に固有の自発分極及びピエゾ分極によって、界面に反対符号の自由キャリアが誘起されやすい。 In order to improve the insulation characteristics, for example, it is effective to use a buffer layer including a heterojunction of an aluminum gallium nitride (AlGaN) layer and a gallium nitride (GaN) layer. The induced charge generated for this is an obstacle to the improvement of the insulation characteristics. In the AlGaN / GaN heterojunction structure laminated in the c-axis direction, free carriers with opposite signs are likely to be induced at the interface due to the spontaneous polarization and piezoelectric polarization inherent in the nitride-based semiconductor crystal.
上記のようなヘテロ接合を含むバッファ層においては、分極モーメントがAlxGa1−xN層のAl組成xに依存するため、分極電荷密度はAl組成xに依存する(例えば、非特許文献1参照)。非特許文献1によれば、AlGaN層中に固有に存在する自発分極とGaN層の中に固有に存在する自発分極との差分に相当する電荷σPsp/eがAlGaN層とGaN層の界面に誘起される。さらに、外力に応じて発生するAlGaN層中の弾性応力によるAlGaN層中のピエゾ分極と外力に応じて発生するGaN層中の弾性応力によるGaN層中のピエゾ分極との差分に相当する電荷σPpe/eがAlGaN層とGaN層の界面に誘起される。このため、上記のσPsp/eとσPpe/eとの合計σ/e(Psp+Ppe)がAlGaN層とGaN層の界面に誘起される全分極電荷に相当する。
In the buffer layer including the heterojunction as described above, since the polarization moment depends on the Al composition x of the Al x Ga 1-x N layer, the polarization charge density depends on the Al composition x (for example, Non-Patent Document 1). reference). According to
そして、AlGaN層の組成式AlxGa1−xNのAl組成xとσ/e(Psp+Ppe)との関係を実験により求めると、この関係を表す曲線は、関係式σ/e(Psp+Ppe)=5×1013・x(x≦0.6)、σ/e(Psp+Ppe)=1×1014・x−3×1013(x>0.6)で表される。 Then, when the relationship between the Al composition x of the AlGaN layer Al x Ga 1-x N and σ / e (P sp + P pe ) is obtained by experiments, the curve representing this relationship is expressed by the relationship σ / e ( P sp + P pe ) = 5 × 10 13 · x (x ≦ 0.6), σ / e (P sp + P pe ) = 1 × 10 14 · x−3 × 10 13 (x> 0.6) Is done.
すなわち、非特許文献1によれば、AlGaN/GaNへテロ接合構造を有するバッファ層において、AlGaN層の組成式をAlxGa1−xN、バッファ層中の各々のAlGaN層とGaN層の界面の分極電荷密度をNpとすると、x≦0.6のときは、概ねNp=5×1013・x(cm−2)で表され、x>0.6のときは、概ねNp=1×1014・x−3×1013(cm−2)で表される。例えば、Al組成xが0.1である場合は、分極電荷密度Npは概ね5x1012(cm−2)である。
That is, according to Non-Patent
分極電荷は層の両端に反対符号の電荷を誘起するが、AlGaN/GaNへテロ接合構造が独立系である場合は、電気的には中性であって問題はない。しかし、その上層にHEMT構造などのアクティブ層が形成されると、それによってバンドダイアグラムが変化して、部分的に中性条件から外れる。自由電子をキャリアとするモノポーラデバイスであるHEMTエピ構造では、バッファ層のAlGaN/GaN界面にも電子が優勢的に誘起されやすくなる。これを抑えるためには、バッファ層へのアクセプタの導入が有効であると考えられる。 Polarization charges induce charges of opposite signs at both ends of the layer, but when the AlGaN / GaN heterojunction structure is an independent system, it is electrically neutral and causes no problem. However, when an active layer such as a HEMT structure is formed on the upper layer, the band diagram is changed thereby, and partially deviates from the neutral condition. In the HEMT epi structure, which is a monopolar device using free electrons as carriers, electrons tend to be predominantly induced at the AlGaN / GaN interface of the buffer layer. In order to suppress this, it is considered effective to introduce an acceptor into the buffer layer.
従来、組成の異なる2種の窒化アルミニウムガリウム層の交互層からなる多層バッファ層に、炭素を含有させた化合物半導体基板が知られている(例えば、特許文献1参照)。特許文献1によれば、多層バッファ層が炭素を含有することにより、デバイスの耐電圧性能が向上する。
2. Description of the Related Art Conventionally, a compound semiconductor substrate in which carbon is contained in a multilayer buffer layer composed of alternating layers of two types of aluminum gallium nitride layers having different compositions is known (for example, see Patent Document 1). According to
しかし、特許文献1に記載された化合物半導体基板のように、多層バッファ層全体に炭素をドーピングすると、アクセプタとして機能する炭素がチャネル層の自由電子も捕獲してしまうおそれが高く、デバイスのオン抵抗が上昇し、デバイス特性が悪化してしまうという問題がある。
However, when carbon is doped in the entire multilayer buffer layer as in the compound semiconductor substrate described in
したがって、本発明の目的の一つは、オン抵抗特性及びバッファリーク特性に優れるデバイスの製造に用いることができる、ヘテロ接合を含むバッファ層を有する窒化物半導体ウェハを提供することにある。 Accordingly, one object of the present invention is to provide a nitride semiconductor wafer having a buffer layer including a heterojunction, which can be used for manufacturing a device having excellent on-resistance characteristics and buffer leakage characteristics.
(1)また、本発明の他の態様によれば、上記目的を達成するため、基板と、AlxGa1−xN層(0≦x≦0.05)と、AlyGa1−yN層(0<y≦1、かつx<y)との交互層を含む、前記基板上のバッファ層と、を有し、前記交互層において、前記AlyGa1−yN層のみがアクセプタを含み、前記交互層の前記AlyGa1−yN層のうちの最上層のAlyGa1−yN層のAl組成yは、0<y≦0.4であり、前記最上層のAlyGa1−yN層の前記アクセプタのシート濃度Nsは、5×1013・y<Ns≦2×1013(cm−2)である、窒化物半導体ウェハが提供される。 (1) According to another aspect of the present invention, for achieving the above object, a substrate, Al x Ga 1-x N layer (0 ≦ x ≦ 0.05), Al y Ga 1-y A buffer layer on the substrate including alternating layers with N layers (0 <y ≦ 1 and x <y), wherein only the Al y Ga 1-y N layer is an acceptor. wherein the said Al y Ga 1-y N Al composition y of the uppermost Al y Ga 1-y N layer of layers of the alternating layer is 0 <y ≦ 0.4, the uppermost A nitride semiconductor wafer in which the acceptor sheet concentration Ns of the Al y Ga 1-y N layer is 5 × 10 13 · y <Ns ≦ 2 × 10 13 (cm −2 ) is provided.
(2)上記窒化物半導体ウェハにおいて、前記アクセプタは、鉄(Fe)、炭素(C)、亜鉛(Zn)のうちの少なくとも1種類からなることが好ましい。 ( 2 ) In the nitride semiconductor wafer, the acceptor is preferably made of at least one of iron (Fe), carbon (C), and zinc (Zn).
(3)上記窒化物半導体ウェハにおいて、前記AlxGa1−xN層のAl組成xは、x=0であることが好ましい。 ( 3 ) In the nitride semiconductor wafer, the Al composition x of the Al x Ga 1-x N layer is preferably x = 0.
(4)上記窒化物半導体ウェハにおいて、前記交互層のすべての前記AlyGa1−yN層のAl組成y及び一層あたりの前記アクセプタのシート濃度Nsが等しいことが好ましい。 ( 4 ) In the nitride semiconductor wafer, it is preferable that the Al composition y of all the Al y Ga 1-y N layers of the alternating layers and the sheet concentration Ns of the acceptor per layer are equal.
本発明の一態様によれば、オン抵抗特性及びバッファリーク特性に優れるデバイスの製造に用いることができる、ヘテロ接合を含むバッファ層を有する窒化物半導体ウェハを提供することができる。 According to one embodiment of the present invention, a nitride semiconductor wafer having a buffer layer including a heterojunction, which can be used for manufacturing a device having excellent on-resistance characteristics and buffer leak characteristics can be provided.
(実施の形態の要点)
本発明の一実施の形態は、基板と、AlxGa1−xN層(0≦x≦0.05)と、AlyGa1−yN層(0<y≦1、かつx<y)との交互層を含む、基板上のバッファ層と、を有し、交互層において、AlyGa1−yN層のみがアクセプタを含む、窒化物半導体ウェハを提供する。
(Main points of the embodiment)
An embodiment of the present invention includes a substrate, an Al x Ga 1-x N layer (0 ≦ x ≦ 0.05), an Al y Ga 1-y N layer (0 <y ≦ 1, and x <y And a buffer layer on the substrate, wherein only the Al y Ga 1-y N layer includes an acceptor.
窒化物半導体ウェハを用いてHEMT等のデバイスを製造した場合、交互層において、AlxGa1−xN層がアクセプタを含まず、AlyGa1−yN層のみがアクセプタを含むことにより、AlxGa1−xN層とAlyGa1−yN層とのヘテロ界面に生じる分極電荷に起因する誘起電荷を効果的に抑制することができる。さらに、AlyGa1−yN層のアクセプタ濃度を適切な値に設定することにより、アクセプタによるチャネル層の自由電子の捕獲を最小限に抑えてキャリア伝導の低減を抑えつつ、バッファ層における自由キャリア発生を抑制して高い絶縁特性を確保することができる。 When a device such as HEMT is manufactured using a nitride semiconductor wafer, in the alternating layers, the Al x Ga 1-x N layer does not include an acceptor, and only the Al y Ga 1-y N layer includes an acceptor, It is possible to effectively suppress the induced charge caused by the polarization charge generated at the hetero interface between the Al x Ga 1-x N layer and the Al y Ga 1-y N layer. Furthermore, by setting the acceptor concentration of the Al y Ga 1-y N layer to an appropriate value, the free electron trapping in the channel layer by the acceptor is minimized, the reduction in carrier conduction is suppressed, and the freedom in the buffer layer is reduced. Carrier generation can be suppressed and high insulation characteristics can be ensured.
〔実施の形態〕
(窒化物半導体ウェハの構造)
図1(a)は、実施の形態に係る窒化物半導体ウェハの垂直断面図である。図1(b)は、窒化物半導体ウェハを用いて形成されたHEMT(高電子移動度トランジスタ)の垂直断面図である。
Embodiment
(Nitride semiconductor wafer structure)
FIG. 1A is a vertical sectional view of a nitride semiconductor wafer according to an embodiment. FIG. 1B is a vertical sectional view of a HEMT (High Electron Mobility Transistor) formed using a nitride semiconductor wafer.
窒化物半導体ウェハ1は、基板11、基板11上のGaNバッファ層12、GaNバッファ層12上のバッファ層13を有する。HEMT2は、窒化物半導体ウェハ1と、窒化物半導体ウェハ1のバッファ層13上のチャネル層21と、チャネル層21上の障壁層22と、障壁層22上のソース電極23、ドレイン電極24、及びゲート電極25を有する。
The
基板11は、例えば、ノンドープのGaN基板、又はFeドープGaN基板である。また、基板11とGaNバッファ層12との間に核発生層と呼ばれるAlN又はAlGaNからなる層を挿入することにより、半絶縁性SiC基板やSi基板等を基板11として使用することができる。
The
GaNバッファ層12は、例えば、GaN結晶からなる。チャネル層21は、例えば、GaN結晶又はInGaN結晶からなり、20nmの厚さを有する。障壁層22は、例えば、AlGaN結晶又はInAlN結晶からなり、25nmの厚さを有する。ソース電極23及びドレイン電極24は、例えば、TiとAlの積層体からなる。ゲート電極25は、例えば、PdとAuの積層体からなる。
The GaN
バッファ層13は、AlxGa1−xN層(0≦x≦0.05)13aと、AlyGa1−yN層(0<y≦1、かつx<y)13bとの交互層、すなわちAlxGa1−xN層13aとAlyGa1−yN層13bとを交互に積層して形成される層からなる。AlxGa1−xN層13a及びAlyGa1−yN層13bの各々の厚さは、例えば、50nmである。
The
AlxGa1−xN層13aは、AlxGa1−xN結晶(0≦x≦0.05)からなり、アクセプタを実質的に含まない。AlyGa1−yN層13bは、AlyGa1−yN結晶(0<y≦1、かつx<y)を母結晶とし、アクセプタを含む。 The Al x Ga 1-x N layer 13a is made of an Al x Ga 1-x N crystal (0 ≦ x ≦ 0.05) and does not substantially include an acceptor. The Al y Ga 1-y N layer 13b uses an Al y Ga 1-y N crystal (0 <y ≦ 1 and x <y) as a mother crystal and includes an acceptor.
すなわち、このAlxGa1−xN層13aとAlyGa1−yN層13bの交互層において、AlyGa1−yN層13bのみが実質的にアクセプタを含む。AlxGa1−xN層13aには意図的にアクセプタがドーピングされないため、AlyGa1−yN層13bから拡散移動したようなアクセプタがAlxGa1−xN層13a中に存在したとしても、その濃度は極めて低く、電気的測定の検出下限以下(例えば、8×1016(cm−3)以下)である。
That is, in the alternating layers of the Al x Ga 1-x N layer 13a and the Al y Ga 1-y N layer 13b, only the Al y Ga 1-y N layer 13b substantially includes an acceptor. Since Al x Ga intentionally acceptor in 1-x
仮に、AlxGa1−xN層13aとAlyGa1−yN層13bの両方がアクセプタを含むとすると、AlxGa1−xN層13a中のアクセプタ準位がフェルミ準位をピン止めして、AlyGa1−yN層13bにアクセプタをドーピングする効果が弱まる。このため、分極電荷に起因する誘起電荷の補償が不十分となり、バッファ層13の絶縁特性が低減するおそれがある。また、逆に、バッファ層13の絶縁特性が確保されるような濃度でアクセプタをドーピングすると、チャネル層の自由電子も捕獲してしまい、デバイスのオン抵抗が上昇するおそれが高い。
If both the Al x Ga 1-x N layer 13a and the Al y Ga 1-y N layer 13b include an acceptor, the acceptor level in the Al x Ga 1-x N layer 13a pins the Fermi level. The effect of doping the acceptor into the Al y Ga 1-y N layer 13b is weakened. For this reason, compensation of the induced charge due to the polarization charge becomes insufficient, and there is a possibility that the insulating characteristics of the
なお、AlxGa1−xN層13aの分極電荷密度は小さい方が好ましいので、AlxGa1−xN層13aのAl組成xは、x=0であることが好ましい。 Since polarization density of the Al x Ga 1-x N layer 13a is preferably small, Al composition x of Al x Ga 1-x N layer 13a is preferably x = 0.
また、AlxGa1−xN層13aとAlyGa1−yN層13bの層数は、図1(a)、(b)に示されるものに限られない。また、バッファ層13において、AlxGa1−xN層13aとAlyGa1−yN層13bの層数は、同じであってもよいし、一方が他方より1つ多くてもよい。
Moreover, the number of layers of the Al x Ga 1-x N layer 13a and the Al y Ga 1-y N layer 13b is not limited to that shown in FIGS. Moreover, in the
AlyGa1−yN層13bに含まれるアクセプタとして、ベリリウム(Be)、マグネシウム(Mg)、カルシウム(Ca)、亜鉛(Zn)、又はカドミウム(Cd)等のII族金属、鉄(Fe)又はマンガン(Mn)等の遷移金属、炭素(C)等の両性不純物を用いることができる。中でも、本実施の形態においては、ドーピングの容易さの観点から、Fe、Zn、又はCがアクセプタとして好ましく、Cが特に好ましい。 As an acceptor included in the Al y Ga 1-y N layer 13b, a group II metal such as beryllium (Be), magnesium (Mg), calcium (Ca), zinc (Zn), or cadmium (Cd), iron (Fe) Alternatively, transition metals such as manganese (Mn) and amphoteric impurities such as carbon (C) can be used. Among these, in the present embodiment, Fe, Zn, or C is preferable as an acceptor from the viewpoint of easy doping, and C is particularly preferable.
バッファ層13におけるAlyGa1−yN層13bのうちの少なくとも最上層のAlyGa1−yN層13bのAl組成yは、0<y≦0.4であり、かつアクセプタのシート濃度Nsは、5×1013・y<Ns≦2×1013(cm−2)であることが好ましい。
Al composition y of at least the uppermost layer of Al y Ga 1-y N layer 13b of the Al y Ga 1-y N layer 13b in the
最上層のAlyGa1−yN層13bのアクセプタのシート濃度Nsが5×1013・y以下の場合、AlxGa1−xN層13aとAlyGa1−yN層13bとのヘテロ界面に生じる分極電荷に起因する誘起電荷を十分に補償することができず、バッファリーク電流を十分に抑えることができないおそれがある。一方、アクセプタのシート濃度Nsが2×1013(cm−2)より高い場合、アクセプタがチャネル層21の自由電子を捕獲し、HEMT2のオン抵抗が上昇するおそれがある。
When the sheet concentration Ns of the acceptor of the uppermost Al y Ga 1-y N layer 13b is 5 × 10 13 · y or less, the Al x Ga 1-x N layer 13a and the Al y Ga 1-y N layer 13b There is a possibility that the induced charge caused by the polarization charge generated at the heterointerface cannot be sufficiently compensated and the buffer leakage current cannot be sufficiently suppressed. On the other hand, when the sheet concentration Ns of the acceptor is higher than 2 × 10 13 (cm −2 ), the acceptor may capture free electrons of the channel layer 21 and increase the on-resistance of the
また、最上層のAlyGa1−yN層13bのAl組成yが0.4よりも大きい場合、分極電荷に起因する誘起電荷の量が多くなりすぎ、これを補償するためにシート濃度Nsが2×1013(cm−2)より高いアクセプタが必要になるおそれがある。 Further, when the Al composition y of the uppermost Al y Ga 1-y N layer 13b is larger than 0.4, the amount of induced charges due to the polarization charge becomes too large, and the sheet concentration Ns is compensated for this. May require an acceptor higher than 2 × 10 13 (cm −2 ).
上から2層目以下のAlyGa1−yN層13bのAl組成y及び一層あたりのアクセプタのシート濃度Nsは、最上層のAlyGa1−yN層13bのものと異なっていてもよいが、チャネル層21の自由電子濃度への影響を極力抑えつつバッファリーク電流を極力抑えるために、最上層と同様の条件「Al組成yが0<y≦0.4であり、かつアクセプタのシート濃度Nsが5×1013・y<Ns≦2×1013(cm−2)」を満たすことが好ましい。また、製造が容易になるため、全てのAlyGa1−yN層13bのAl組成y及び一層あたりのアクセプタのシート濃度Nsが等しいことがより好ましい。 The Al composition y of the second and lower layers of the Al y Ga 1-y N layer 13b and the acceptor sheet concentration Ns per layer may be different from those of the uppermost layer of the Al y Ga 1-y N layer 13b. However, in order to suppress the buffer leakage current as much as possible while suppressing the influence on the free electron concentration of the channel layer 21 as much as possible, the condition “Al composition y is 0 <y ≦ 0.4 and the acceptor It is preferable that the sheet concentration Ns satisfies 5 × 10 13 · y <Ns ≦ 2 × 10 13 (cm −2 ) ”. Further, since the production is facilitated, and it is more preferable that all of Al y Ga 1-y N layer 13b of Al composition y and sheet density Ns of the acceptor per layer is equal.
(実施の形態の効果)
本実施の形態によれば、バッファ層13において、AlxGa1−xN層13aがアクセプタを含まず、AlyGa1−yN層13bのみがアクセプタを含むことにより、AlxGa1−xN層13aとAlyGa1−yN層13bとのヘテロ界面に生じる分極電荷に起因する誘起電荷を効果的に抑制することができる。さらに、AlyGa1−yN層13bのアクセプタ濃度を本実施の形態に係る適切な値に設定することにより、アクセプタによるチャネル層21の自由電子の捕獲を最小限に抑えてキャリア伝導の低減を抑えつつ、バッファ層13における自由キャリア発生を抑制して高い絶縁特性を確保することができる。
(Effect of embodiment)
According to the present embodiment, in the
したがって、本実施の形態の窒化物半導体ウェハ1を用いて、オン抵抗特性及びバッファリーク特性に優れるHEMT2等のデバイスを製造することができる。
Therefore, a device such as
〔他の実施の形態〕
以上、本発明の実施の形態を説明したが、本発明は、上記実施の形態に限定されず、発明の主旨を逸脱しない範囲内において種々変形実施が可能である。
[Other Embodiments]
Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention.
例えば、バッファ層13において、AlxGa1−xN層13a及びAlyGa1−yN層13bの代わりに、InAlN結晶からなる層を用いることも可能であるが、発生する分極電荷密度や、上記実施の形態と同様の効果を得るためのアクセプタ濃度はAlxGa1−xN層13a及びAlyGa1−yN層13bと異なる可能性がある。
For example, in the
上記実施の形態に係るHEMT2を製造し、各種評価を行った。以下に、評価の方法及び結果を述べる。
The
(バッファ層の製造)
本実施例において用いたバッファ層13の製造方法について述べる。
(Manufacture of buffer layer)
A method for manufacturing the
有機金属気相成膜法によりAlxGa1−xN層13aとAlyGa1−yN層13bを形成した。後述する各種の評価のために、AlyGa1−yN層13bのAl組成y及びアクセプタ濃度の異なる複数のHEMT2を形成した。なお、AlxGa1−xN層13aのAl組成xは0に固定した。
An Al x Ga 1-x N layer 13a and an Al y Ga 1-y N layer 13b were formed by a metal organic vapor deposition method. For various evaluations to be described later, a plurality of
Ga原料としてトリメチルガリウム又はトリエチルガリウムを用いた。Al原料としてトリメチルアルミニウムを用いた。窒素原料としてアンモニアを用い、一部、ヒドラジン系材料を用いた。また、アクセプタとしてのCの原料として、III族原料又はCBr4を用いた。アクセプタとしてのFeの原料としてFeCl3を用いた。アクセプタとしてのZnの原料としてジメチルZnを用いた。 Trimethyl gallium or triethyl gallium was used as a Ga raw material. Trimethylaluminum was used as the Al raw material. Ammonia was used as a nitrogen raw material, and a hydrazine-based material was partially used. Further, a group III material or CBr 4 was used as a material for C as an acceptor. FeCl 3 was used as a raw material for Fe as an acceptor. Dimethyl Zn was used as a raw material for Zn as an acceptor.
V/III比(V族原料の濃度とIII族原料の濃度の比)、成膜温度(サセプタ温度)、成長圧力を適宜変えてAlGaN結晶を成長させながら間欠的にCをドーピングし、AlxGa1−xN層13aとAlyGa1−yN層13bを形成した。そして、元素分析により所望のC濃度となったものを選別して後述する評価を行った。ここで、V/III比は概ね10〜100,000の範囲で調整した。成膜温度は概ね800〜1,250℃の範囲で調整した。成長圧力は概ね10k〜100kPaの範囲で調整した。キャリアガスとしては、水素、窒素、又はそれらの混合気体を用い、混合気体の混合割合は随時調整した。 Al x is doped intermittently while growing an AlGaN crystal by appropriately changing the V / III ratio (ratio of the concentration of the group V material to the concentration of the group III material), the film formation temperature (susceptor temperature), and the growth pressure. A Ga 1-x N layer 13a and an Al y Ga 1-y N layer 13b were formed. And the thing which became the desired C density | concentration by the elemental analysis was selected, and evaluation mentioned later was performed. Here, the V / III ratio was adjusted in the range of approximately 10 to 100,000. The film forming temperature was generally adjusted in the range of 800 to 1,250 ° C. The growth pressure was generally adjusted in the range of 10 to 100 kPa. As the carrier gas, hydrogen, nitrogen, or a mixed gas thereof was used, and the mixing ratio of the mixed gas was adjusted as needed.
なお、成膜条件を変えても、後述するHEMT2についての評価結果に変化はなかった。HEMT2の特性はAl組成やC等のアクセプタの濃度で一義的に決まっており、成膜条件にはあまり依存しないものと考えられる。 In addition, even if the film forming conditions were changed, there was no change in the evaluation results for HEMT2, which will be described later. The characteristics of HEMT2 are uniquely determined by the acceptor concentration such as the Al composition and C, and are considered to be less dependent on the film forming conditions.
また、基板11として、ノンドープのGaN基板とFeドープGaN基板を用いたが、いずれも評価結果に変化はなかった。また、チャネル層21と障壁層22に、GaN層とAlGaN層の組み合わせと、InGaN層とInAlN層の組み合わせを用いたが、いずれも評価結果に変化はなかった。
Moreover, although the non-doped GaN substrate and the Fe-doped GaN substrate were used as the
(バッファ層の絶縁特性の評価)
図2は、本実施の形態のHEMT2及び比較例のHEMTにおける、ゲート電圧とバッファリーク電流の関係を表すグラフである。図2の横軸はゲート電圧(V)を表し、縦軸はバッファリーク電流であるドレイン電流(A)を表す。線αは本実施の形態のHEMT2の測定結果を表し、線βは比較例のHEMTの測定結果を表す。
(Evaluation of insulation properties of buffer layer)
FIG. 2 is a graph showing the relationship between the gate voltage and the buffer leakage current in the
本測定に用いたHEMT2におけるバッファ層13は、厚さ50nmの2層のAlxGa1−xN層13aと、厚さ50nmの3層のAlyGa1−yN層13bから構成され、AlyGa1−yN層13bのAl組成yとアクセプタとしてのCのシート濃度Nsは、それぞれ0.15と、2×1013(cm−2)である。AlxGa1−xN層13aには、Cを意図的にドーピングしておらず、Cの濃度は電気的測定の検出下限以下(8×1016(cm−3)以下)であると推測される。
The
また、比較例のHEMTは、本測定に用いられるHEMT2のAlxGa1−xN層13aの代わりに厚さ50nmのアクセプタを含まないGaN層が形成され、AlyGa1−yN層13bの代わりに厚さ50nmのアクセプタとしてのCを含むGaN層が形成されたトランジスタである。このCを含むGaN層の1層あたりのCのシート濃度Nsは、2×1013(cm−2)である。
In addition, in the HEMT of the comparative example, a GaN layer not including an acceptor having a thickness of 50 nm is formed instead of the Al x Ga 1-x N layer 13a of the
また、本実施の形態のHEMT2及び比較例のHEMTのゲート長は2μmであり、ゲート幅は20μmである。測定は、ドレイン電圧を100Vとして行った。
The gate length of the
図2によれば、比較例のHEMTのピンチオフ時のバッファリーク電流がおよそ1×10−5(A)であるのに対して、実施の形態のHEMT2のピンチオフ時のバッファリーク電流は1×10−5(A)以下であり、比較例よりも2桁以上小さい。
According to FIG. 2, the buffer leakage current at the time of pinch-off of the HEMT of the comparative example is about 1 × 10 −5 (A), whereas the buffer leakage current at the time of pinch-off of the
2×1013(cm−2)という比較的低いシート濃度NsのCにより、リーク電流がこれほど抑えられる理由については物理的に明らかではないが、本実施の形態のバッファ層13においては、AlyGa1−yN層13bの一方の面において生じた分極電荷を、反対の面において生じた反対極性の分極電荷がある程度相殺するためであると考えられる。
Although the reason why the leakage current is suppressed so much by C having a relatively low sheet concentration Ns of 2 × 10 13 (cm −2 ) is not clear, in the
(絶縁特性のアクセプタ濃度依存性の評価)
図3は、HEMT2に−8Vのゲート電圧(Vg)を印加してピンチオフさせた状態における、AlyGa1−yN層13bのアクセプタとしてのCのシート濃度Nsとバッファリーク電流であるドレイン電流との関係を表すグラフである。図3の横軸はAlyGa1−yN層13bのCのシート濃度Ns(cm−2)を表し、縦軸はドレイン電流(A)を表す。図3は、AlyGa1−yN層13bのAl組成yがそれぞれ0.1、0.2、0.3である3種のHEMT2についての測定結果を示す。なお、AlyGa1−yN層13b以外の部材の構成はすべてのHEMT2において同じである。
(Evaluation of acceptor concentration dependence of insulation properties)
FIG. 3 shows the sheet concentration Ns of C as an acceptor of the Al y Ga 1-y N layer 13b and the drain current which is a buffer leak current in a state where the gate voltage (Vg) of −8V is applied to the
図3は、Cのシート濃度Nsがある境界値よりも高くなると、バッファリーク電流がさらに大きく低減し、1×10−9(A)程度になること示している。AlyGa1−yN層13bのAl組成yが大きいほど、この境界値は大きくなり、y=0.1、0.2、0.3のときの境界値は、それぞれおよそ5×1012(cm−2)、1×1013(cm−2)、1.5×1013(cm−2)である。 FIG. 3 shows that when the sheet density Ns of C becomes higher than a certain boundary value, the buffer leakage current is further greatly reduced to about 1 × 10 −9 (A). The larger the Al composition y of the Al y Ga 1-y N layer 13b, the larger this boundary value, and the boundary values when y = 0.1, 0.2, and 0.3 are about 5 × 10 12 respectively. (Cm −2 ), 1 × 10 13 (cm −2 ), and 1.5 × 10 13 (cm −2 ).
この境界値の値は、前述の“O. Ambacherら,Journal of Applied Physics,Vol.87,334頁,2000”に示される関係式「AlxGa1−xN層のAl組成xがx≦0.6のときは、AlGaN層とGaN層の界面の分極電荷密度NpはNp=5×1013・x(cm−2)、x>0.6のときは、Np=1×1014・x−3×1013(cm−2)」から算出されるAlyGa1−yN層13bとAlxGa1−xN層13a(xが0.05以下と小さいため、近似的にGaN層として扱うことができる)の界面の分極電荷密度Npにほぼ等しい。これは、分極電荷に起因する誘起電荷を補償するために、分極電荷密度Npと同等のシート濃度のアクセプタが必要になることによると考えられる。 The value of this boundary value is expressed by the relational expression “Al x Ga 1-x N layer x of the Al x Ga 1-x N layer x ≦ x ≦ O. Ambacher et al., Journal of Applied Physics, Vol. 87, page 334, 2000”. When 0.6, the polarization charge density Np at the interface between the AlGaN layer and the GaN layer is Np = 5 × 10 13 · x (cm −2 ), and when x> 0.6, Np = 1 × 10 14. The Al y Ga 1-y N layer 13b and the Al x Ga 1-x N layer 13a calculated from “x−3 × 10 13 (cm −2 )” (since x is as small as 0.05 or less, approximately The polarization charge density Np at the interface of the interface (which can be treated as a layer). This is considered to be because an acceptor having a sheet density equivalent to the polarization charge density Np is required to compensate for the induced charge caused by the polarization charge.
したがって、AlyGa1−yN層13bのアクセプタのシート濃度NsがAlyGa1−yN層13bの分極電荷密度Npよりも高いとき、すなわちAl組成yがy≦0.6のときは5×1013・y(cm−2)よりも高く、y>0.6のときは1×1014・y−3×1013(cm−2)よりも高いときに、高いバッファリーク電流の抑制効果が得られるといえる。 Therefore, when the Al y Ga 1-y N layer 13b sheet concentration Ns of acceptors is higher than the polarization density Np of Al y Ga 1-y N layer 13b, that is, when the Al composition y is y ≦ 0.6 is High buffer leakage current when higher than 5 × 10 13 · y (cm −2 ), and higher than 1 × 10 14 · y−3 × 10 13 (cm −2 ) when y> 0.6 It can be said that a suppression effect is obtained.
アクセプタのシート濃度Nsが高いほどバッファリーク電流が小さくなるのは、アクセプタのシート濃度Nsが高い方がバッファ層13のフェルミ準位の位置が安定するためと考えられる。これはまた、導入したアクセプタが、単にバッファ層13中の分極電荷による誘起電荷を補償するだけでなく、AlxGa1−xN層13a中、あるいはAlyGa1−yN層13b中に含まれる残留ドナー型不純物も補償しているためと思われる。一般に、バッファ層の残留ドナー型不純物のシート濃度は、チャネル層の自由電子のシート濃度(およそ1〜2×1013(cm−2))に影響を及ぼさない程度に制御され、それはチャネル層のシート濃度の悪くても半分以下、つまりおよそ1×1013(cm−2)以下である。
The reason why the buffer leak current decreases as the acceptor sheet concentration Ns increases is that the higher the acceptor sheet concentration Ns, the more stable the Fermi level position of the
(キャリア伝導特性のアクセプタ濃度依存性の評価)
図4は、本実施の形態のHEMT2における、アクセプタとしてのCのシート濃度Nsと飽和ドレイン電流との関係を表すグラフである。図4の横軸はAlyGa1−yN層13bに含まれる1層あたりのCのシート濃度Ns(cm−2)を表し、縦軸は飽和ドレイン電流(A/mm)を表す。図4は、AlyGa1−yN層13bのAl組成yがそれぞれ0.1、0.2、0.3である3種のHEMT2についての測定結果を示す。なお、AlyGa1−yN層13b以外の部材の構成はすべてのHEMT2において同じである。
(Evaluation of acceptor concentration dependence of carrier conduction characteristics)
FIG. 4 is a graph showing the relationship between the sheet concentration Ns of C as an acceptor and the saturation drain current in the
図4は、アクセプタであるCのシート濃度Nsが2×1013(cm−2)を超えると、飽和ドレイン電流が急激に低下することを示している。これは、チャネル層21の自由電子のシート濃度に対するAlyGa1−yN層13bのアクセプタのシート濃度Nsが高過ぎるため、チャネル層の自由電子がアクセプタに捕獲され、急激にフェルミ準位の位置がシフトすることによると考えられる。このため、AlyGa1−yN層13bの一層あたりのアクセプタのシート濃度Nsは、2×1013(cm−2)以下であることが好ましい。 FIG. 4 shows that when the sheet concentration Ns of the acceptor C exceeds 2 × 10 13 (cm −2 ), the saturation drain current rapidly decreases. This is because the acceptor sheet concentration Ns of the Al y Ga 1-y N layer 13b with respect to the free electron sheet concentration of the channel layer 21 is too high, so that the free electrons of the channel layer are trapped by the acceptor, and the Fermi level rapidly increases. This is thought to be due to the shift in position. Therefore, the sheet concentration Ns of the acceptor per layer of Al y Ga 1-y N layer 13b is preferably at 2 × 10 13 (cm -2) or less.
なお、HEMTを含む電界効果トランジスタ(FET)系デバイスでは、多くの場合、チャネル層の自由電子のシート濃度はいずれも1×1013〜2×1013(cm−2)程度と近い値であるから、窒化物半導体ウェハ1を用いてHEMT2以外のFET系デバイスを形成する場合においても、AlyGa1−yN層13bの一層あたりのアクセプタのシート濃度Nsは、2×1013(cm−2)以下であることが好ましいといえる。
In many cases, in the field effect transistor (FET) -based device including HEMT, the free electron sheet concentration of the channel layer is close to about 1 × 10 13 to 2 × 10 13 (cm −2 ). from, in the case of forming a FET-based devices other than HEMT2 using
ここで、上述の高いバッファリーク電流の抑制効果を得るための条件「y≦0.6のときはNs>5×1013・y(cm−2)、y>0.6のときはNs>1×1014・y−3×1013(cm−2)」に、チャネル層21のキャリア伝導を妨げないための条件「Ns≦2×1013(cm−2)」を加えると、前の条件においてy>0.4ではNs>2×1013(cm−2)となってしまうため、「0<y≦0.4、かつ5×1013・y<Ns≦2×1013(cm−2)」となる。 Here, the condition for obtaining the above-described effect of suppressing the high buffer leakage current is “Ns> 5 × 10 13 · y (cm −2 ) when y ≦ 0.6, and Ns> when y> 0.6. When the condition “Ns ≦ 2 × 10 13 (cm −2 )” for preventing the carrier conduction of the channel layer 21 is added to “1 × 10 14 · y−3 × 10 13 (cm −2 )”, Under the condition, if y> 0.4, Ns> 2 × 10 13 (cm −2 ), so “0 <y ≦ 0.4 and 5 × 10 13 · y <Ns ≦ 2 × 10 13 (cm -2 ) ".
したがって、チャネル層21のキャリア伝導を妨げず、かつバッファリーク電流を効果的に抑えるためには、AlyGa1−yN層13bが「0<y≦0.4、かつ5×1013・y<Ns≦2×1013(cm−2)」の条件を満たすことが好ましいといえる。 Therefore, in order not to hinder the carrier conduction of the channel layer 21 and to suppress the buffer leakage current effectively, the Al y Ga 1-y N layer 13b has a relationship of “0 <y ≦ 0.4 and 5 × 10 13. It can be said that it is preferable to satisfy the condition of “y <Ns ≦ 2 × 10 13 (cm −2 )”.
なお、Cの代わりにFe、ZnをAlyGa1−yN層13bにドーピングして同様の実験を行ったところ、同様の測定結果が得られ、同様の条件によりチャネル層21のキャリア伝導を妨げず、かつバッファリーク電流を効果的に抑えることができることがわかった。さらに、C、Fe、Znのうちの2種類又は3種類を組み合わせてAlyGa1−yN層13bにドーピングした場合も同様であった。 In addition, when the same experiment was conducted by doping Fe and Zn into the Al y Ga 1-y N layer 13b instead of C, the same measurement result was obtained, and the carrier conduction of the channel layer 21 was performed under the same conditions. It was found that the buffer leakage current can be effectively suppressed without hindering. Further, the same was true when the Al y Ga 1-y N layer 13b was doped by combining two or three of C, Fe, and Zn.
なお、本実施例においては、バッファ層13中のすべてのAlyGa1−yN層13bのAl組成y及びCのシート濃度Nsを等しくしたが、少なくともチャネル層21に最も近い最上層のAlyGa1−yN層13bが上記の条件「0<y≦0.4、かつ5×1013・y<Ns≦2×1013(cm−2)」を満たせば、同様の効果が得られる。
In this embodiment, the Al composition y of all the Al y Ga 1-y N layers 13 b and the sheet concentration Ns of C in the
上記に記載した実施の形態及び実施例は特許請求の範囲に係る発明を限定するものではない。また、実施の形態及び実施例の中で説明した特徴の組合せの全てが発明の課題を解決するための手段に必須であるとは限らない点に留意すべきである。 The embodiments and examples described above do not limit the invention according to the claims. It should be noted that not all combinations of features described in the embodiments and examples are necessarily essential to the means for solving the problems of the invention.
1 窒化物半導体ウェハ
11 基板
12 GaNバッファ層
13 バッファ層
13a AlxGa1−xN層
13b AlyGa1−yN層
First
Claims (4)
AlxGa1−xN層(0≦x≦0.05)と、AlyGa1−yN層(0<y≦1、かつx<y)との交互層を含む、前記基板上のバッファ層と、
を有し、
前記交互層において、前記AlyGa1−yN層のみがアクセプタを含み、
前記交互層の前記AlyGa1−yN層のうちの最上層のAlyGa1−yN層のAl組成yは、0<y≦0.4であり、
前記最上層のAlyGa1−yN層の前記アクセプタのシート濃度Nsは、5×1013・y<Ns≦2×1013(cm−2)である、
窒化物半導体ウェハ。 A substrate,
On the substrate, including alternating layers of Al x Ga 1-x N layers (0 ≦ x ≦ 0.05) and Al y Ga 1-y N layers (0 <y ≦ 1 and x <y) A buffer layer,
Have
In the alternating layers, only the Al y Ga 1-y N layer includes an acceptor,
It said Al y Ga 1-y N Al composition y of the uppermost Al y Ga 1-y N layer of layers of the alternating layer is 0 <y ≦ 0.4,
The acceptor sheet concentration Ns of the uppermost Al y Ga 1-y N layer is 5 × 10 13 · y <Ns ≦ 2 × 10 13 (cm −2 ).
Nitride semiconductor wafer.
請求項1に記載の窒化物半導体ウェハ。 The acceptor is composed of at least one of iron (Fe), carbon (C), and zinc (Zn).
The nitride semiconductor wafer according to claim 1 .
請求項1又は2に記載の窒化物半導体ウェハ。 The Al composition x of the Al x Ga 1-x N layer is x = 0.
The nitride semiconductor wafer according to claim 1 or 2 .
請求項1〜3のいずれかに記載の窒化物半導体ウェハ。 The Al composition y of all the Al y Ga 1-y N layers of the alternating layers and the sheet concentration Ns of the acceptor per layer are equal,
The nitride semiconductor wafer according to any one of claims 1-3.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012193047A JP6002508B2 (en) | 2012-09-03 | 2012-09-03 | Nitride semiconductor wafer |
US13/962,812 US9070619B2 (en) | 2012-09-03 | 2013-08-08 | Nitride semiconductor wafer for a high-electron-mobility transistor and its use |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012193047A JP6002508B2 (en) | 2012-09-03 | 2012-09-03 | Nitride semiconductor wafer |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014049674A JP2014049674A (en) | 2014-03-17 |
JP6002508B2 true JP6002508B2 (en) | 2016-10-05 |
Family
ID=50186204
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012193047A Expired - Fee Related JP6002508B2 (en) | 2012-09-03 | 2012-09-03 | Nitride semiconductor wafer |
Country Status (2)
Country | Link |
---|---|
US (1) | US9070619B2 (en) |
JP (1) | JP6002508B2 (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014196466A1 (en) * | 2013-06-06 | 2014-12-11 | 日本碍子株式会社 | Group 13 nitride composite substrate, semiconductor element, and production method for group 13 nitride composite substrate |
US20150137179A1 (en) * | 2013-11-19 | 2015-05-21 | Huga Optotech Inc. | Power device |
US9159788B2 (en) * | 2013-12-31 | 2015-10-13 | Industrial Technology Research Institute | Nitride semiconductor structure |
JP6249868B2 (en) * | 2014-04-18 | 2017-12-20 | サンケン電気株式会社 | Semiconductor substrate and semiconductor element |
CN104332498B (en) * | 2014-09-01 | 2018-01-05 | 苏州捷芯威半导体有限公司 | A kind of tiltedly preparation method of field plate power device and oblique field plate power device |
JP6473017B2 (en) | 2015-03-09 | 2019-02-20 | エア・ウォーター株式会社 | Compound semiconductor substrate |
TW201637078A (en) * | 2015-04-01 | 2016-10-16 | 環球晶圓股份有限公司 | Semiconductor device |
TWI566430B (en) * | 2015-05-06 | 2017-01-11 | 嘉晶電子股份有限公司 | Nitride semiconductor structure |
CN105206664B (en) * | 2015-10-29 | 2019-05-07 | 杭州士兰微电子股份有限公司 | HEMT device and its manufacturing method based on silicon substrate |
US10290730B1 (en) | 2018-04-12 | 2019-05-14 | Epistar Corporation | Semiconductor power device |
US20220328674A1 (en) * | 2021-04-12 | 2022-10-13 | Innoscience (Suzhou) Technology Co., Ltd. | Semiconductor device and method for manufacturing the same |
JPWO2022254596A1 (en) * | 2021-06-02 | 2022-12-08 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3994623B2 (en) * | 2000-04-21 | 2007-10-24 | 豊田合成株式会社 | Method for producing group III nitride compound semiconductor device |
IL161420A0 (en) * | 2001-10-26 | 2004-09-27 | Ammono Sp Zoo | Substrate for epitaxy |
US7919791B2 (en) * | 2002-03-25 | 2011-04-05 | Cree, Inc. | Doped group III-V nitride materials, and microelectronic devices and device precursor structures comprising same |
US7112830B2 (en) * | 2002-11-25 | 2006-09-26 | Apa Enterprises, Inc. | Super lattice modification of overlying transistor |
US20050006639A1 (en) * | 2003-05-23 | 2005-01-13 | Dupuis Russell D. | Semiconductor electronic devices and methods |
JP4509031B2 (en) * | 2003-09-05 | 2010-07-21 | サンケン電気株式会社 | Nitride semiconductor device |
JP4449467B2 (en) * | 2004-01-28 | 2010-04-14 | サンケン電気株式会社 | Semiconductor device |
JP5028640B2 (en) * | 2004-03-26 | 2012-09-19 | 日亜化学工業株式会社 | Nitride semiconductor laser device |
JP2009076694A (en) * | 2007-09-20 | 2009-04-09 | Panasonic Corp | Nitride semiconductor device and method for manufacturing the same |
JP5477685B2 (en) * | 2009-03-19 | 2014-04-23 | サンケン電気株式会社 | Semiconductor wafer, semiconductor element and manufacturing method thereof |
JP5634681B2 (en) * | 2009-03-26 | 2014-12-03 | 住友電工デバイス・イノベーション株式会社 | Semiconductor element |
JP2010251414A (en) * | 2009-04-13 | 2010-11-04 | Oki Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
US8742459B2 (en) * | 2009-05-14 | 2014-06-03 | Transphorm Inc. | High voltage III-nitride semiconductor devices |
JP4681684B1 (en) * | 2009-08-24 | 2011-05-11 | Dowaエレクトロニクス株式会社 | Nitride semiconductor device and manufacturing method thereof |
JP5188545B2 (en) | 2009-09-14 | 2013-04-24 | コバレントマテリアル株式会社 | Compound semiconductor substrate |
US20120326209A1 (en) * | 2010-03-01 | 2012-12-27 | Dowa Electronics Materials Co., Ltd. | Semiconductor device and method of producing the same |
JP2012009630A (en) * | 2010-06-24 | 2012-01-12 | Panasonic Corp | Nitride semiconductor device and method of manufacturing nitride semiconductor device |
US9691855B2 (en) * | 2012-02-17 | 2017-06-27 | Epistar Corporation | Method of growing a high quality III-V compound layer on a silicon substrate |
-
2012
- 2012-09-03 JP JP2012193047A patent/JP6002508B2/en not_active Expired - Fee Related
-
2013
- 2013-08-08 US US13/962,812 patent/US9070619B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2014049674A (en) | 2014-03-17 |
US9070619B2 (en) | 2015-06-30 |
US20140061665A1 (en) | 2014-03-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6002508B2 (en) | Nitride semiconductor wafer | |
US8344422B2 (en) | Semiconductor device | |
JP6473017B2 (en) | Compound semiconductor substrate | |
WO2012066701A1 (en) | Nitride semiconductor device | |
JP6330148B2 (en) | Semiconductor device | |
JP2017073506A (en) | Nitride semiconductor device and method for manufacturing the same | |
JP2009231508A (en) | Semiconductor device | |
JP5919703B2 (en) | Semiconductor device | |
WO2011024754A1 (en) | Group iii nitride laminated semiconductor wafer and group iii nitride semiconductor device | |
US20130256681A1 (en) | Group iii nitride-based high electron mobility transistor | |
JP2007250991A (en) | Semiconductor structure comprising superlattice structure, and semiconductor device equipped therewith | |
JPWO2010064706A1 (en) | Semiconductor device | |
JP2008277655A (en) | Semiconductor epitaxial wafer, and field-effect transistor | |
JP2010258313A (en) | Field-effect transistor and manufacturing method thereof | |
JP2010206125A (en) | Gallium nitride-based high electron mobility transistor | |
JP2007080855A (en) | Field effect transistor | |
JP2012169470A (en) | Semiconductor device and manufacturing method of the same | |
US20130043492A1 (en) | Nitride semiconductor transistor | |
JP2011171440A (en) | Group iii nitride-based hetero field-effect transistor | |
JP6001345B2 (en) | Semiconductor substrate for transistor, transistor, and method for manufacturing semiconductor substrate for transistor | |
JP5721782B2 (en) | Semiconductor device | |
JP2011171422A (en) | Field-effect transistor | |
JP6084254B2 (en) | Compound semiconductor substrate | |
JP2014067807A (en) | Nitride-based compound semiconductor element and manufacturing method of the same | |
JP2013038157A (en) | Compound semiconductor substrate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20141024 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20150515 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150917 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20151006 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20151127 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20151204 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20160419 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160630 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20160708 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160809 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160905 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6002508 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |