JP5974454B2 - Electronic components - Google Patents

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JP5974454B2
JP5974454B2 JP2011248550A JP2011248550A JP5974454B2 JP 5974454 B2 JP5974454 B2 JP 5974454B2 JP 2011248550 A JP2011248550 A JP 2011248550A JP 2011248550 A JP2011248550 A JP 2011248550A JP 5974454 B2 JP5974454 B2 JP 5974454B2
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substrate
semiconductor element
sealing material
electronic component
conductor
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JP2013105878A (en
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苅谷　隆
隆 苅谷
利益 陳
利益 陳
吉川　和弘
吉川　　和弘
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Ibiden Co Ltd
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Ibiden Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Description

本発明は、絶縁層と導体パターンとを積層してなる第１基板と、第１基板上に実装されて絶縁層と導体パターンとを積層してなるコアレスの第２基板と、第２基板上に実装される半導体素子とを有する電子部品に関するものである。 The present invention includes a first substrate formed by stacking an insulating layer and a conductor pattern, a coreless second substrate mounted on the first substrate and formed by stacking an insulating layer and a conductor pattern, and a second substrate. an electronic unit product having a semiconductor element mounted on.

半導体素子を実装する基板として、高集積化のためコア基板に層間樹脂絶縁層と導体パターンとを交互に積層して成るビルドアップ多層配線板が用いられている。ここで、更に、集積率を高め、配線距離を短くするため、厚みのあるコア基板を除いたコアレスのビルドアップ多層配線板が提案されている。特許文献１には、複数のチップ（半導体チップ、電子チップ）を１つのパッケージ内に収めたマルチチップパッケージが開示されている。複数のチップのうち任意のチップから発生した熱を他のチップに伝え難くするため、各チップが個別に封止されている。そして、任意のチップを封止する封止材の上にはヒートシンクが設けられている。 As a substrate for mounting a semiconductor element, a build-up multilayer wiring board in which an interlayer resin insulating layer and a conductor pattern are alternately stacked on a core substrate is used for high integration. Here, in order to further increase the integration rate and shorten the wiring distance, a coreless build-up multilayer wiring board excluding a thick core substrate has been proposed. Patent Document 1 discloses a multichip package in which a plurality of chips (semiconductor chips, electronic chips) are housed in one package. In order to make it difficult to transfer heat generated from an arbitrary chip among the plurality of chips to other chips, each chip is individually sealed. A heat sink is provided on a sealing material that seals an arbitrary chip.

特開２００８‐２８８２５０JP2008-288250A

近年、半導体素子（特にロジックチップ）は、プロセッサコア領域が小さくなる傾向にある。それに伴い、半導体素子に供給される電流の密度が高くなることから、半導体素子は発熱しやすくなる。
このため、マルチチップパッケージにおいては、ロジックチップで発生した熱を他のチップに伝え難くする構造への要求が高まっており、その点で依然として改善の余地があると考えられる。 In recent years, a semiconductor element (particularly a logic chip) tends to have a smaller processor core area. As a result, the density of the current supplied to the semiconductor element increases, and the semiconductor element easily generates heat.
For this reason, in the multi-chip package, there is an increasing demand for a structure that makes it difficult to transfer heat generated in the logic chip to other chips, and there is still room for improvement in that respect.

本発明は、上述した課題を解決するためになされたものであり、その目的とするところは、複数の半導体素子を有する場合でも、第１半導体素子（ロジックチップ）から発生した熱を第２半導体素子に伝達させにくくする電子部品を提供することにある。 The present invention has been made to solve the above-described problems, and an object of the present invention is to generate heat generated from the first semiconductor element (logic chip) even when the semiconductor device has a plurality of semiconductor elements. An object of the present invention is to provide an electronic component that is difficult to be transmitted to an element.

本願発明の電子部品では、第１貫通孔を有するコア基板と、該コア基板の両面に形成されている第１導体回路と、該第１貫通孔に形成され該コア基板の両面の第１導体回路を接続するスルーホール導体と、前記コア基板及び前記第１導体回路上に形成されて第１樹脂絶縁層と第２導体回路とが交互に積層されてなるビルドアップ層と、を備える第１基板と、
第２貫通孔を備える複数の第２樹脂絶縁層と、該第２樹脂絶縁層上に形成されている第３導体回路と、該第２貫通孔内に設けられ該第２樹脂絶縁層の両面の第３導体回路を接続するビア導体と、を有する第２基板と、
端子の設けられた下面と、該下面との反対側の上面とを備え、前記第２基板上に該下面側が実装されるロジックチップ及びメモリチップと、
前記ロジックチップ及びメモリチップ上に取り付けられる放熱部材であって、前記ロジックチップの前記上面に当接されると共に、前記メモリチップの前記上面との当接部位に開口の設けられた放熱部材と、を備え、前記放熱部材は、前記第２半導体素子の直上に開口を有し、前記第１半導体素子はロジックチップであり、前記第２半導体素子はメモリチップであり、前記第１封止材と前記第２封止材とは分離している。 In the electronic component of the present invention, the core substrate having the first through hole, the first conductor circuit formed on both surfaces of the core substrate, and the first conductor formed on the first through hole on both surfaces of the core substrate. A through-hole conductor for connecting a circuit; and a build-up layer formed on the core substrate and the first conductor circuit, wherein a first resin insulating layer and a second conductor circuit are alternately stacked. A substrate,
A plurality of second resin insulation layers having a second through hole, a third conductor circuit formed on the second resin insulation layer, and both surfaces of the second resin insulation layer provided in the second through hole A second conductor having a via conductor connecting the third conductor circuit;
A logic chip and a memory chip each including a lower surface provided with a terminal and an upper surface opposite to the lower surface, the lower surface being mounted on the second substrate;
A heat dissipating member attached on the logic chip and the memory chip, the heat dissipating member being in contact with the upper surface of the logic chip and provided with an opening at a contact portion with the upper surface of the memory chip; The heat dissipation member has an opening directly above the second semiconductor element, the first semiconductor element is a logic chip, the second semiconductor element is a memory chip, and the first sealing material It is separated from the second sealing material.

本願発明では、第２半導体素子の直上に開口を有する放熱部材を採用する。このため、第１半導体素子（ロジックチップ）から発生した熱が第２半導体素子（メモリチップ）へ伝わり難くなるため、第１半導体素子からの熱的影響でメモリチップが誤動作し難くなると考えられる。 In the present invention, a heat dissipating member having an opening immediately above the second semiconductor element is employed. For this reason, the heat generated from the first semiconductor element (logic chip) is not easily transmitted to the second semiconductor element (memory chip), so that it is considered that the memory chip is less likely to malfunction due to the thermal influence from the first semiconductor element.

本発明の第１実施形態に係る第２基板の製造工程図である。It is a manufacturing process figure of the 2nd substrate concerning a 1st embodiment of the present invention. 第１実施形態に係る第２基板の製造工程図である。It is a manufacturing process figure of the 2nd substrate concerning a 1st embodiment. 第１実施形態に係る第２基板の製造工程図である。It is a manufacturing process figure of the 2nd substrate concerning a 1st embodiment. 第１実施形態に係る第２基板の製造工程図である。It is a manufacturing process figure of the 2nd substrate concerning a 1st embodiment. 第１実施形態に係る第２基板の製造工程図である。It is a manufacturing process figure of the 2nd substrate concerning a 1st embodiment. 第１実施形態に係る第２基板の断面図である。It is sectional drawing of the 2nd board | substrate which concerns on 1st Embodiment. 第１実施形態に係る第２基板の平面図である。It is a top view of the 2nd substrate concerning a 1st embodiment. 第１実施形態に係る第１基板の断面図である。It is sectional drawing of the 1st board | substrate which concerns on 1st Embodiment. 第１実施形態に係る第１基板に第２基板が実装された状態を示す断面図である。It is sectional drawing which shows the state by which the 2nd board | substrate was mounted in the 1st board | substrate which concerns on 1st Embodiment. 第１実施形態に係る電子部品の断面図である。It is sectional drawing of the electronic component which concerns on 1st Embodiment. 第１実施形態に係る放熱部材の平面図である。It is a top view of the heat radiating member concerning a 1st embodiment. 第２実施形態に係る第２基板の製造工程図である。It is a manufacturing process figure of the 2nd substrate concerning a 2nd embodiment. 第２実施形態に係る第２基板の断面図である。It is sectional drawing of the 2nd board | substrate which concerns on 2nd Embodiment. 第２実施形態に係る第２基板の平面図である。It is a top view of the 2nd substrate concerning a 2nd embodiment.

[第１実施形態]
図１０は、第１実施形態の電子部品１０の断面図である。
電子部品１０は、コア基板２３０を備える第１基板２００と、コア基板を備えない第２基板２０と、第２基板２０上に実装された第１半導体素子（ロジックチップ９０Ａ）及び第２半導体素子（メモリチップ９０Ｂ）とを有している。ロジックチップ９０Ａは第１封止材９６Ａにより封止されており、メモリチップ９０Ｂは第２封止材９６Ｂにより封止されている。
第２基板２０上には、ロジックチップ９０Ａ及びメモリチップ９０Ｂを覆う放熱部材３００が設けられている。さらに、放熱部材３００上には、ヒートシンク３２０が設けられている。 [First embodiment]
FIG. 10 is a cross-sectional view of the electronic component 10 of the first embodiment.
The electronic component 10 includes a first substrate 200 including the core substrate 230, a second substrate 20 not including the core substrate, a first semiconductor element (logic chip 90A) and a second semiconductor element mounted on the second substrate 20. (Memory chip 90B). The logic chip 90A is sealed with a first sealing material 96A, and the memory chip 90B is sealed with a second sealing material 96B.
On the second substrate 20, a heat dissipation member 300 is provided to cover the logic chip 90A and the memory chip 90B. Further, a heat sink 320 is provided on the heat dissipation member 300.

第１基板２００は、コア基板２３０と、コア基板２３０の両面に設けられているビルドアップ層２１０とを有している。図８に第１基板の断面が示される。コア基板２３０の内部には、表裏の導体パターンを電気的に接続するスルーホール導体２３６が設けられている。コア基板の両面に積層された第１絶縁層（層間樹脂絶縁層）２５０を貫通する貫通孔２３３が設けられ、該貫通孔２３３内にスルーホール導体２３６が形成されている。スルーホール導体の端部にはスルーホールランド２３７が形成されている。スルーホール導体２３６によりコア基板両面の第１導体パターン２３４が接続されている。第１絶縁層２５０上には、第１ビア導体２６６及び第１導体パターン２６８を備える第１絶縁層（層間樹脂絶縁層）２６０と、第１ビア導体２７６及び第１導体パターン２７８を備える第１絶縁層（層間樹脂絶縁層）２７０とから成るビルドアップ層２１０が形成されている。第１絶縁層２７０上には、開口２８１を備えるソルダーレジスト層２８０が形成され、上面側の開口２８１には第２基板２０を実装するためのパッド２７８Ｐが設けられ、下面側の開口２８１には、図示しない外部基板接続用のパッド２７９Ｐが設けられている。 The first substrate 200 includes a core substrate 230 and buildup layers 210 provided on both surfaces of the core substrate 230. FIG. 8 shows a cross section of the first substrate. A through-hole conductor 236 that electrically connects the front and back conductor patterns is provided inside the core substrate 230. A through hole 233 that penetrates the first insulating layer (interlayer resin insulating layer) 250 laminated on both surfaces of the core substrate is provided, and a through hole conductor 236 is formed in the through hole 233. A through-hole land 237 is formed at the end of the through-hole conductor. First conductor patterns 234 on both surfaces of the core substrate are connected by through-hole conductors 236. On the first insulating layer 250, a first insulating layer (interlayer resin insulating layer) 260 including a first via conductor 266 and a first conductor pattern 268, and a first via conductor 276 and a first conductor pattern 278 are provided. A build-up layer 210 composed of an insulating layer (interlayer resin insulating layer) 270 is formed. A solder resist layer 280 having an opening 281 is formed on the first insulating layer 270, a pad 278 </ b> P for mounting the second substrate 20 is provided in the opening 281 on the upper surface side, and an opening 281 on the lower surface side is provided. A pad 279P for connecting an external substrate (not shown) is provided.

第２基板２０の断面が図６に示される。
第２基板２０は、第１面Ｆとその第１面とは反対側の第２面Ｓとを有する第２絶縁層５０と、第２絶縁層５０の第１面Ｆ上に形成されている第２導体パターン５８と、第２絶縁層５０の第１面上及び第２導体パターン５８上に形成されている第２絶縁層１５０と、第２絶縁層１５０上に形成されている第２導体パターン１５８とを有している。
そして、第２絶縁層１５０の内部には貫通孔１５１が設けられていて、この貫通孔１５１の内部には、第２導体パターン５８と第２導体パターン１５８とを接続する第２ビア導体１６０が設けられている。 A cross section of the second substrate 20 is shown in FIG.
The second substrate 20 is formed on a second insulating layer 50 having a first surface F and a second surface S opposite to the first surface, and the first surface F of the second insulating layer 50. The second conductor pattern 58, the second insulating layer 150 formed on the first surface of the second insulating layer 50 and the second conductor pattern 58, and the second conductor formed on the second insulating layer 150 Pattern 158.
A through hole 151 is provided in the second insulating layer 150, and a second via conductor 160 that connects the second conductor pattern 58 and the second conductor pattern 158 is provided in the through hole 151. Is provided.

第２絶縁層５０は、熱硬化性樹脂、感光性樹脂、熱硬化性樹脂の一部に感光性基が付与された樹脂、熱可塑性樹脂、又は、これらの樹脂を含む樹脂複合体等からなる層である。
第２絶縁層５０の内部には貫通孔５１が設けられている。貫通孔５１の内部には、めっきからなる第２ビア導体６０が形成されている。第２ビア導体６０の先端部には、半田バンプ７７が配置される。 The second insulating layer 50 is made of a thermosetting resin, a photosensitive resin, a resin in which a photosensitive group is added to a part of the thermosetting resin, a thermoplastic resin, or a resin composite containing these resins. Is a layer.
A through hole 51 is provided in the second insulating layer 50. A second via conductor 60 made of plating is formed inside the through hole 51. A solder bump 77 is disposed at the tip of the second via conductor 60.

第２絶縁層１５０上にはソルダーレジスト層７０が設けられている。ソルダーレジスト層７０には、第２導体パターン１５８の少なくとも一部を露出する開口７１が設けられている。この開口７１の内部には半田バンプ７６が設けられている。そして、これら半田バンプ７６を介して第２基板２０上にロジックチップ９０Ａ、メモリチップ９０Ｂが実装されている。なお、ロジックチップ９０Ａを実装するバンプ７６のピッチは９０μｍ以下である。 A solder resist layer 70 is provided on the second insulating layer 150. The solder resist layer 70 is provided with an opening 71 that exposes at least a part of the second conductor pattern 158. Solder bumps 76 are provided inside the openings 71. Then, the logic chip 90A and the memory chip 90B are mounted on the second substrate 20 via the solder bumps 76. The pitch of the bumps 76 on which the logic chip 90A is mounted is 90 μm or less.

ロジックチップ９０Ａの側面は第１封止材９６Ａで封止されている。この第１封止材９６Ａの表面とロジックチップ９０Ａの表面とは同一平面上に位置する。すなわち、ロジックチップ９０Ａの上面は第１封止材９６Ａから露出されている。メモリチップ９０Ｂの側面は第２封止材９６Ｂで封止され、メモリチップ９０Ｂの上面は第２封止材９６Ｂから露出されている。図７は、該第２基板２０の平面図である。第２基板の第１封止材９６Ａと第２封止材９６Ｂとの間には溝９６Ｃが設けられている。すなわち、第１封止材９６Ａと第２封止材９６Ｂとは分離している The side surface of the logic chip 90A is sealed with a first sealing material 96A. The surface of the first sealing material 96A and the surface of the logic chip 90A are located on the same plane. That is, the upper surface of the logic chip 90A is exposed from the first sealing material 96A. The side surface of the memory chip 90B is sealed with the second sealing material 96B, and the upper surface of the memory chip 90B is exposed from the second sealing material 96B. FIG. 7 is a plan view of the second substrate 20. A groove 96C is provided between the first sealing material 96A and the second sealing material 96B of the second substrate. That is, the first sealing material 96A and the second sealing material 96B are separated.

図１０に示すように第１基板３００上には、ロジックチップ９０Ａ及びメモリチップ９０Ｂを覆うように放熱部材３００が取り付けられている。放熱部材３００を形成する材料としては、例えばアルミニウムや銅等が挙げられる。放熱部材３００は、凹状のキャビティ部３０４と、キャビティ部３０４の周囲に設けられた平板部状のフランジ部３０２とから成り、キャビティ部３０４には平板部３０６が設けられている。キャビティ部３０４内に、ロジックチップ９０Ａとメモリチップ９０Ｂとが収容されている。そして、該放熱部材３００は、フランジ部３０２を介して第１基板２００に固定されている。 As shown in FIG. 10, the heat dissipation member 300 is attached on the first substrate 300 so as to cover the logic chip 90 </ b> A and the memory chip 90 </ b> B. Examples of the material for forming the heat dissipation member 300 include aluminum and copper. The heat dissipation member 300 includes a concave cavity portion 304 and a flat plate-like flange portion 302 provided around the cavity portion 304, and the flat plate portion 306 is provided in the cavity portion 304. In the cavity 304, the logic chip 90A and the memory chip 90B are accommodated. The heat radiating member 300 is fixed to the first substrate 200 via the flange portion 302.

図１１に、放熱部材３００が取り付けられた状態の第２基板の平面図が示される。
放熱部材３００の平板部３０６はメモリチップ９０Ｂ上に開口３０８を備え、放熱部材３００とメモリチップ９０Ｂとが直接接しないようにされている。図１０に示すように平板部３０６は、ロジックチップ９０Ａの上面、第１封止材９６Ａの上面、第２封止材９６Ｂの周縁側の上面と接している。放熱部材３００の平板部上には、放熱フィン３２２を備えるヒートシンク３２０が設けられている。 FIG. 11 shows a plan view of the second substrate with the heat dissipation member 300 attached thereto.
The flat plate portion 306 of the heat dissipating member 300 has an opening 308 on the memory chip 90B so that the heat dissipating member 300 and the memory chip 90B are not in direct contact with each other. As shown in FIG. 10, the flat plate portion 306 is in contact with the upper surface of the logic chip 90A, the upper surface of the first sealing material 96A, and the upper surface of the second sealing material 96B. On the flat plate portion of the heat radiating member 300, a heat sink 320 including heat radiating fins 322 is provided.

第１実施形態の電子部品では、ロジックチップ９０Ａ及びメモリチップ９０Ｂ上に放熱部材３００が取り付けられる。この放熱部材３００には、メモリチップ９０Ｂの上面との当接部位に開口３０８が設けられている。このため、ロジックチップ９０Ａからの熱が放熱部材３００を介してメモリチップ９０Ｂへ伝わり難くなるため、該ロジックチップからの熱的影響でメモリチップが誤動作し難くなる。 In the electronic component of the first embodiment, the heat dissipation member 300 is attached on the logic chip 90A and the memory chip 90B. The heat radiating member 300 is provided with an opening 308 at a contact portion with the upper surface of the memory chip 90B. This makes it difficult for heat from the logic chip 90A to be transferred to the memory chip 90B via the heat dissipation member 300, and thus the memory chip is less likely to malfunction due to thermal influence from the logic chip.

第１実施形態の電子部品では、ロジックチップ９０Ａを封止する第１封止材９６Ａと、メモリチップ９０Ｂを封止する第２封止材９６Ｂとの間に溝９６Ｃが設けられている。このため、ロジックチップ９０Ａからの熱が封止材を介してメモリチップ９０Ｂへ伝わり難くなるため、該ロジックチップからの熱的影響でメモリチップが誤動作し難くなる。 In the electronic component of the first embodiment, a groove 96C is provided between the first sealing material 96A that seals the logic chip 90A and the second sealing material 96B that seals the memory chip 90B. This makes it difficult for heat from the logic chip 90A to be transferred to the memory chip 90B through the sealing material, and thus the memory chip is less likely to malfunction due to the thermal influence from the logic chip.

第１実施形態の電子部品では、メモリチップ９０Ｂの周囲の第２封止材９６Ｂは、放熱部材３００と当接している。このため、第２封止材９６Ｂが放熱部材３００で押さえられることになり、第２封止材９６Ｂの剥離を防止することができる。 In the electronic component of the first embodiment, the second sealing material 96B around the memory chip 90B is in contact with the heat dissipation member 300. For this reason, the 2nd sealing material 96B will be hold | suppressed with the thermal radiation member 300, and peeling of the 2nd sealing material 96B can be prevented.

第１実施形態の電子部品では、放熱部材３００上にヒートシンク３２０が取り付けられているので、ロジックチップ９０Ａからの熱を効率的に逃がすことができる。 In the electronic component of the first embodiment, since the heat sink 320 is attached on the heat dissipation member 300, the heat from the logic chip 90A can be efficiently released.

第１実施形態の電子部品では、放熱部材３００は、凹状のキャビティ部３０４と該キャビティ部３０４の周縁のフランジ部３０２とを備え、キャビティ部３０４に、第２基板２０を、該第２基板に接触することなく収容するので、コアレスで強度的に弱い第２基板に熱的ストレスを与え難い。そして、コア基板を備え強度的に強い第１基板２００にフランジ部３０２を介して放熱部材３００が固定されているので、信頼性を高めることができる。 In the electronic component of the first embodiment, the heat dissipation member 300 includes a concave cavity portion 304 and a flange portion 302 at the periphery of the cavity portion 304, and the second substrate 20 is attached to the cavity portion 304 and the second substrate. Since it accommodates without contacting, it is hard to give a thermal stress to the coreless and weak second substrate. And since the heat radiating member 300 is being fixed to the 1st board | substrate 200 which is provided with a core board | substrate and is strong through the flange part 302, reliability can be improved.

第１実施形態の電子部品では、第１封止材９６Ａの表面とロジックチップ９０Ａの表面とは同一平面上に位置する。このため、電子部品全体の厚みを低減できる。さらに、ロジックチップ９０Ａで発生した熱を放熱部材３００に伝えやすい。また、ロジックチップ９０Ａの表面は放熱部材３００に接している。このため、ロジックチップ９０Ａで発生した熱を放熱部材３００に伝えやすい。 In the electronic component of the first embodiment, the surface of the first sealing material 96A and the surface of the logic chip 90A are located on the same plane. For this reason, the thickness of the whole electronic component can be reduced. Furthermore, the heat generated in the logic chip 90A can be easily transferred to the heat dissipation member 300. Further, the surface of the logic chip 90 </ b> A is in contact with the heat dissipation member 300. For this reason, the heat generated in the logic chip 90 </ b> A can be easily transmitted to the heat dissipation member 300.

第１実施形態の電子部品では、第１封止材９６Ａと第２封止材９６Ｂとは分離している。このため、ロジックチップ９０Ａで発生した熱をメモリチップ９０Ｂに伝え難い。また、放熱部材３００の開口３０８の径はメモリチップ９０Ｂの幅よりも大きい。すなわち、放熱部材３００とメモリチップ９０Ｂとが直接接することが避けられる。このため、ロジックチップ９０Ａで発生した熱をメモリチップ９０Ｂに伝え難い。更に、開口３０８によりメモリチップ９０Ｂの表面全体が露出される。このため、ロジックチップ９０Ａで発生した熱をメモリチップ９０Ｂに伝え難い。 In the electronic component of the first embodiment, the first sealing material 96A and the second sealing material 96B are separated. For this reason, it is difficult to transfer the heat generated in the logic chip 90A to the memory chip 90B. Further, the diameter of the opening 308 of the heat dissipation member 300 is larger than the width of the memory chip 90B. That is, direct contact between the heat dissipation member 300 and the memory chip 90B can be avoided. For this reason, it is difficult to transfer the heat generated in the logic chip 90A to the memory chip 90B. Further, the entire surface of the memory chip 90B is exposed through the opening 308. For this reason, it is difficult to transfer the heat generated in the logic chip 90A to the memory chip 90B.

[第２基板の製造方法]
第２基板の製造方法について、図１〜図７を参照して説明される。
（１）まず、厚さ約１．１mmのガラス板３０が用意される（図１（Ａ））。
ガラス板は、実装するシリコン製ＩＣチップとの熱膨張係数差が小さくなるように、ＣＴＥが約３．３（ｐｐｍ）以下で、且つ、後述する剥離工程において使用する３０８ｎｍのレーザ光に対して透過率が９割以上であることが望ましい。 [Method for manufacturing second substrate]
A method for manufacturing the second substrate will be described with reference to FIGS.
(1) First, a glass plate 30 having a thickness of about 1.1 mm is prepared (FIG. 1A).
The glass plate has a CTE of about 3.3 (ppm) or less so that the difference in coefficient of thermal expansion from the mounted silicon IC chip is small. It is desirable that the transmittance is 90% or more.

（２）ガラス板３０の上に、主として熱可塑性ポリイミド樹脂からなる剥離層３２が設けられる（図１（Ｂ））。 (2) A release layer 32 mainly made of a thermoplastic polyimide resin is provided on the glass plate 30 (FIG. 1B).

（３）剥離層３２の上に導体パターン３４が形成される（図１（Ｃ））。 (3) A conductor pattern 34 is formed on the release layer 32 (FIG. 1C).

（４）剥離層３２の上に第２絶縁層５０が形成される（図１（Ｄ））。 (4) The second insulating layer 50 is formed on the release layer 32 (FIG. 1D).

（５）ＣＯ2ガスレーザにて、第２絶縁層５０を貫通し、剥離層３２に至る電極体用開口５１が設けられる（図１（Ｅ）参照）。 (5) An electrode body opening 51 that penetrates the second insulating layer 50 and reaches the release layer 32 is provided by a CO2 gas laser (see FIG. 1E).

（６）スパッタリングにより、第２絶縁層５０上にＴｉＮ、Ｔｉ及びＣｕからなる導体層５２が形成される（図２（Ａ））。 (6) A conductor layer 52 made of TiN, Ti, and Cu is formed on the second insulating layer 50 by sputtering (FIG. 2A).

（７）導体層５２上に、市販の感光性ドライフィルムが貼り付けられ、フォトマスクフィルムが載置され露光された後、炭酸ナトリウムで現像処理され、厚さ約１５μｍのめっきレジスト５４が設けられる（図２（Ｂ））。 (7) A commercially available photosensitive dry film is affixed on the conductor layer 52, and after the photomask film is placed and exposed, it is developed with sodium carbonate to provide a plating resist 54 having a thickness of about 15 μm. (FIG. 2 (B)).

（８）導体層５２を給電層として用い、電解めっきが施され電解めっき膜５６が形成される（図２（Ｃ））。 (8) Using the conductor layer 52 as a power feeding layer, electrolytic plating is performed to form an electrolytic plating film 56 (FIG. 2C).

（９）めっきレジスト５４が剥離除去される。そして、剥離しためっきレジスト下の導体層５２が除去され、導体層５２及び電解めっき膜５６からなる第２導体パターン５８及び第２ビア導体６０が形成される（図２（Ｄ））。 (9) The plating resist 54 is peeled and removed. Then, the conductor layer 52 under the peeled plating resist is removed, and the second conductor pattern 58 and the second via conductor 60 made of the conductor layer 52 and the electrolytic plating film 56 are formed (FIG. 2D).

（１０）上記（４）〜（１０）と同様にして、第２絶縁層５０及び第２導体パターン５８上に第２絶縁層１５０及び第２導体パターン１５８、第２ビア導体１６０が形成される（図３（Ａ）、図３（Ｂ）、図３（Ｃ））。 (10) The second insulating layer 150, the second conductor pattern 158, and the second via conductor 160 are formed on the second insulating layer 50 and the second conductor pattern 58 in the same manner as in the above (4) to (10). (FIG. 3 (A), FIG. 3 (B), FIG. 3 (C)).

（１１）第２絶縁層１５０上にソルダーレジスト層７０が形成される。その後、ソルダーレジスト層７０の内部に開口７１が設けられて、第２導体パターン１５８の一部が露出される（図３（Ｄ））。第２導体パターン１５８のうち、開口７１により露出された部位によりパッド１５８Ｐが構成される。 (11) A solder resist layer 70 is formed on the second insulating layer 150. Thereafter, an opening 71 is provided inside the solder resist layer 70, and a part of the second conductor pattern 158 is exposed (FIG. 3D). A pad 158 </ b> P is constituted by a portion of the second conductor pattern 158 exposed by the opening 71.

（１２）次に、パッド１５８Ｐ上にＮｉめっきが施された後、半田めっき（Ｓｎ−Ａｇ）が施され、パッド１５８Ｐに半田バンプ７６が形成されることで、中間体１００が製造される。（図３（Ｅ））。この中間体１００は、ガラス板３０と、ガラス板３０上に形成されている第２基板２０とから形成されている。 (12) Next, after Ni plating is performed on the pad 158P, solder plating (Sn-Ag) is performed, and the solder bump 76 is formed on the pad 158P, whereby the intermediate 100 is manufactured. (FIG. 3E). The intermediate body 100 is formed of a glass plate 30 and a second substrate 20 formed on the glass plate 30.

（１３）次いで、中間体１００上に半田バンプ７６を介してロジックチップ９０Ａ、メモリチップ９０Ｂが実装される（図４（Ａ））。このとき、ガラス板３０がＩＣチップ９０Ａ、９０Ｂと熱膨張率が近いので、第２基板２０に加わる応力が低減される。 (13) Next, the logic chip 90A and the memory chip 90B are mounted on the intermediate body 100 via the solder bumps 76 (FIG. 4A). At this time, since the glass plate 30 has a thermal expansion coefficient close to that of the IC chips 90A and 90B, the stress applied to the second substrate 20 is reduced.

（１４）第２基板２０とロジックチップ９０Ａ、メモリチップ９０Ｂとの間にアンダーフィル９４が充填される（図４（Ｂ））。 (14) An underfill 94 is filled between the second substrate 20, the logic chip 90A, and the memory chip 90B (FIG. 4B).

（１５）モールド型内で、ロジックチップ９０Ａ、メモリチップ９０Ｂが封止材９６で封止される（図４（Ｃ））。 (15) The logic chip 90A and the memory chip 90B are sealed with a sealing material 96 in the mold (FIG. 4C).

（１６）ダイシング又はレーザにより封止材に溝９６Ｃが設けられ、封止材が第１封止材９６Ａと第２封止材９６Ｂとに分断される（図４（Ｄ））。 (16) A groove 96C is provided in the sealing material by dicing or laser, and the sealing material is divided into a first sealing material 96A and a second sealing material 96B (FIG. 4D).

（１７）第１封止材９６Ａ、第２封止材９６Ｂが研磨され、ロジックチップ９０Ａ、メモリチップ９０Ｂの上面が露出される（図５（Ａ））。これにより、ロジックチップ９０Ａに放熱部材３００を直接取り付けることが可能になる。さらに、電子部品全体の高さも抑制される。 (17) The first sealing material 96A and the second sealing material 96B are polished, and the upper surfaces of the logic chip 90A and the memory chip 90B are exposed (FIG. 5A). As a result, the heat dissipation member 300 can be directly attached to the logic chip 90A. Furthermore, the height of the entire electronic component is also suppressed.

（１８）次いで、３０８ｎｍのレーザ光がガラス板３０を透過させて剥離層３２に照射され、剥離層３２が軟化される。そして、第２基板２０に対してガラス板３０がスライドされ、ガラス板３０が剥離される（図５（Ｂ））。 (18) Next, a laser beam of 308 nm is transmitted through the glass plate 30 to irradiate the release layer 32, and the release layer 32 is softened. And the glass plate 30 is slid with respect to the 2nd board | substrate 20, and the glass plate 30 peels (FIG.5 (B)).

（１９）アッシングにより剥離層３２が除去され、第２絶縁層５０及び第２ビア導体６０が露出される（図５（Ｃ））。 (19) The peeling layer 32 is removed by ashing, and the second insulating layer 50 and the second via conductor 60 are exposed (FIG. 5C).

（２０）そして、第２ビア導体６０のパッド３４上に半田バンプ７７が形成され、第２基板２０が完成される（図５（Ｄ））。 (20) Then, solder bumps 77 are formed on the pads 34 of the second via conductor 60, and the second substrate 20 is completed (FIG. 5D).

（２１）第２基板２０は、図８を参照して上述した第１基板２００上に、半田バンプ７７を介して実装される。そして、第１基板２００と第２基板２０との間には、アンダーフィル９８が充填される（図９）。 (21) The second substrate 20 is mounted via the solder bumps 77 on the first substrate 200 described above with reference to FIG. An underfill 98 is filled between the first substrate 200 and the second substrate 20 (FIG. 9).

該第１基板２００上に、ヒートシンク３２０の固定された放熱部材３００が取り付けられ、その放熱部材３００とロジックチップ９０Ａの上面とが接触する（図１０）。 The heat radiating member 300 to which the heat sink 320 is fixed is attached on the first substrate 200, and the heat radiating member 300 and the upper surface of the logic chip 90A are in contact with each other (FIG. 10).

[第２実施形態]
図１３は、第２実施形態の第２基板２０の断面図であり、図１４は第２基板の平面図であり、図１４中のＸ−Ｘ断面が図１３に対応する。
図６を参照して上述した第１実施形態では、ロジックチップ９０Ａを封止する第１封止材９６Ａと、メモリチップ９０Ｂを封止する第２封止材９６Ｂとが分離されていた。これに対して、第２実施形態では、ロジックチップ９０Ａとメモリチップ９０Ｂとが一体の封止材９６に封止され、ロジックチップ９０Ａとメモリチップ９０Ｂとの周囲を封止材９６の環状部９６Ｄが囲み、封止材９６の中央部に溝９６Ｅが設けられる。 [Second Embodiment]
13 is a cross-sectional view of the second substrate 20 of the second embodiment, FIG. 14 is a plan view of the second substrate, and the XX cross-section in FIG. 14 corresponds to FIG.
In the first embodiment described above with reference to FIG. 6, the first sealing material 96A for sealing the logic chip 90A and the second sealing material 96B for sealing the memory chip 90B are separated. On the other hand, in the second embodiment, the logic chip 90A and the memory chip 90B are sealed with an integral sealing material 96, and the periphery of the logic chip 90A and the memory chip 90B is surrounded by the annular portion 96D of the sealing material 96. And a groove 96 </ b> E is provided in the central portion of the sealing material 96.

第２実施形態の電子部品の製造方法を図１２を参照し説明される。
図１〜図４（Ｂ）を参照して上述した第１実施形態と同様に、第２基板が製造され、ロジックチップ９０Ａとメモリチップ９０Ｂとが実装される（図１２（Ａ））。そして、溝９６Ｅを設ける部位を備えるモールド型内で、ロジックチップ９０Ａとメモリチップ９０Ｂとが封止材９６により封止される（図１２（Ｂ））。 The manufacturing method of the electronic component of 2nd Embodiment is demonstrated with reference to FIG.
Similar to the first embodiment described above with reference to FIGS. 1 to 4B, the second substrate is manufactured, and the logic chip 90A and the memory chip 90B are mounted (FIG. 12A). Then, the logic chip 90A and the memory chip 90B are sealed with a sealing material 96 in a mold having a portion where the groove 96E is provided (FIG. 12B).

第２実施形態の電子部品では、封止材９６は、ロジックチップ９０Ａ及びメモリチップ９０Ｂの側面を環状に保持する環状部９６Ｅを備え、該環状部の中央に溝９６Ｅが設けられている。このため、ロジックチップ及びメモリチップを封止して接続信頼性を高めながら、溝９６Ｅによりロジックチップからの熱が封止材９６を介してメモリチップへ伝わり難くすることができる。 In the electronic component of the second embodiment, the sealing material 96 includes an annular portion 96E that annularly holds the side surfaces of the logic chip 90A and the memory chip 90B, and a groove 96E is provided at the center of the annular portion. For this reason, it is possible to make it difficult for heat from the logic chip to be transmitted to the memory chip through the sealing material 96 by the groove 96E while sealing the logic chip and the memory chip to improve connection reliability.

１０ 電子部品
２０ 第２基板
５０ 第２絶縁層
５８ 第２導体パターン
６０ 第２ビア導体
９０Ａ ロジックチップ
９０Ｂ メモリチップ
９６ 封止材
９６Ａ 第１封止材
９６Ｂ 第２封止材
１５０ 第２絶縁層
１６０ ビア導体
１５８ 第２導体パターン
２００ 第２基板
３００ 放熱部材
３０８ 開口 10 electronic component 20 second substrate 50 second insulating layer 58 second conductor pattern 60 second via conductor 90A logic chip 90B memory chip 96 sealing material 96A first sealing material 96B second sealing material 150 second insulating layer 160 Via conductor 158 Second conductor pattern 200 Second substrate 300 Heat radiation member 308 Opening

Claims (8)

複数の第１絶縁層と該第１絶縁層上の第１導体パターンと上下の第１導体パターン同士を電気的に接続する第１ビア導体とを有する第１基板と、
該第１基板上に実装され、複数の第２絶縁層と該第２絶縁層上の第２導体パターンと上下の第２導体パターン同士を電気的に接続する第２ビア導体とを有する第２基板と、
該第２基板上に実装される第１半導体素子及び第２半導体素子と、
前記第１半導体素子を封止する第１封止材と、
前記第２半導体素子を封止する第２封止材と、
前記第１半導体素子及び前記第２半導体素子を覆うように前記第１基板上に設けられる放熱部材と、
を備える電子部品であって、
前記放熱部材は、前記第２半導体素子の直上に開口を有し、
前記第１半導体素子はロジックチップであり、前記第２半導体素子はメモリチップであり、
前記第１封止材と前記第２封止材とは分離している。 A first substrate having a plurality of first insulating layers, a first conductor pattern on the first insulating layer, and a first via conductor that electrically connects the upper and lower first conductor patterns;
A second mounted on the first substrate and having a plurality of second insulating layers, a second conductor pattern on the second insulating layer, and a second via conductor that electrically connects the upper and lower second conductor patterns. A substrate,
A first semiconductor element and a second semiconductor element mounted on the second substrate;
A first sealing material for sealing the first semiconductor element;
A second sealing material for sealing the second semiconductor element;
A heat dissipation member provided on the first substrate so as to cover the first semiconductor element and the second semiconductor element;
An electronic component comprising:
The heat radiating member may have a opening immediately above the second semiconductor element,
The first semiconductor element is a logic chip, and the second semiconductor element is a memory chip;
The first sealing material and the second sealing material are separated. 請求項１の電子部品であって：
前記第１封止材の表面と前記第１半導体素子の表面とは同一平面上に位置する。 The electronic component of claim 1 , wherein:
The surface of the first sealing material and the surface of the first semiconductor element are located on the same plane. 請求項１の電子部品であって：
前記第１半導体素子の表面は前記放熱部材に接している。 The electronic component of claim 1 , wherein:
The surface of the first semiconductor element is in contact with the heat dissipation member. 請求項１の電子部品であって：
前記開口の径は、前記第２半導体素子の幅よりも大きい。 The electronic component of claim 1 , wherein:
The diameter of the opening is larger than the width of the second semiconductor element. 請求項１の電子部品であって：
前記開口により、前記第２半導体素子の表面全体が露出される。 The electronic component of claim 1 , wherein:
Through the opening, the entire surface of the second semiconductor element is exposed. 請求項１の電子部品であって：
前記放熱部材上にヒートシンクが取り付けられている。 The electronic component of claim 1, wherein:
A heat sink is attached on the heat radiating member. 請求項１の電子部品であって：
前記第２基板は、前記第１半導体素子を実装するバンプを有しており、該バンプのピッチは９０μｍ以下である。 The electronic component of claim 1 , wherein:
The second substrate has bumps for mounting the first semiconductor element, and the pitch of the bumps is 90 μm or less. 請求項１の電子部品であって：
前記放熱部材は、前記第１半導体素子及び前記第２半導体素子を収容するキャビティ部と、前記第１基板に当接し得るフランジ部とを備えている。 The electronic component of claim 1, wherein:
The heat dissipating member includes a cavity portion that houses the first semiconductor element and the second semiconductor element, and a flange portion that can come into contact with the first substrate.
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