JP5965658B2 - 半導体膜の作製方法 - Google Patents
半導体膜の作製方法 Download PDFInfo
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- JP5965658B2 JP5965658B2 JP2012025693A JP2012025693A JP5965658B2 JP 5965658 B2 JP5965658 B2 JP 5965658B2 JP 2012025693 A JP2012025693 A JP 2012025693A JP 2012025693 A JP2012025693 A JP 2012025693A JP 5965658 B2 JP5965658 B2 JP 5965658B2
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- semiconductor film
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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Description
本実施の形態では、本発明の一態様である微結晶半導体膜の作製方法について説明する。具体的には、本実施の形態に示す微結晶半導体膜の作製方法において、反応室内に上部電極及び下部電極を備えたプラズマCVD装置を用いて、基板端部には微結晶半導体膜が形成されないように、該基板端部より内側の領域に微結晶半導体膜を形成する。
ここで、上記微結晶半導体膜の形成を可能とするプラズマCVD装置について図1乃至図3を用いて説明する。なお、本発明の一態様のプラズマCVD装置は平行平板電極を用いた容量結合型高周波プラズマCVD装置として説明する。
次に、上記プラズマCVD装置を用いて微結晶半導体膜を形成する方法について説明する。
本実施の形態は、本発明の一態様である微結晶半導体膜の作製方法において、実施の形態1で説明した方法とは異なる方法について説明する。
本実施の形態は、本発明の一態様である微結晶半導体膜の作製方法において、実施の形態1及び実施の形態2で説明した方法とは異なる方法について説明する。
本実施の形態は、実施の形態1乃至実施の形態3で説明した微結晶半導体膜の作製方法を用いた薄膜トランジスタの作製方法について説明する。
本実施の形態では、実施の形態4と比較して、さらに、オフ電流の低減が可能な薄膜トランジスタの作製方法について、図6、図8及び図10を用いて説明する。
本実施の形態では、本発明の一態様である半導体装置に形成される薄膜トランジスタの作製方法について、図6、図8、及び図11を参照して説明する。図11に示す工程は、図8(B)に示す工程に対応する。
実施の形態4乃至実施の形態6で示した方法で作製した薄膜トランジスタは、表示機能を有する半導体装置(表示装置ともいう)の画素部さらには駆動回路に用いることできる。また、薄膜トランジスタを用いた駆動回路の一部又は全体を、画素部と同じ基板上に一体形成し、システムオンパネルを形成することができる。
実施の形態7で説明した表示装置は、さまざまな電子機器に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビ、又はテレビジョン受信機ともいう)などが挙げられる。さらには、実施の形態7で説明した表示装置は、屋内でのデジタルサイネージ(Digital Signage:電子看板)、PID(Public Information Display)、電車などの乗り物の車内広告、等に適用することができる。特に、実施の形態7で説明した表示装置は、実施の形態4乃至実施の形態6に示した薄膜トランジスタを用いており、該薄膜トランジスタは、オフ電流が低く、且つオン電流及び電界効果移動度が高いことから、精細な画像又は映像を表示することができ、さらに表示装置の消費電力を低減させることができることため、該表示装置を、画像又は映像を長時間表示させる上記電子機器に適用することは有用である。そこで、本発明の一態様である表示装置を用いた電子機器の一例を、図12に示す。
51 実線
53 実線
55 実線
57 実線
101 ロードロック室
102 共通室
103 反応室
107 搬送機構
111 ゲートバルブ
112 ゲートバルブ
201 上部電極
202 下部電極
204 高周波電源
205 サセプター
208 ガス供給手段
209 排気手段
214 基板加熱ヒータ
215 ヒータコントローラ
216 絶縁材
240 基板
400 第1の上部電極
401 第2の上部電極
402 高周波電源
601 基板
603 ゲート電極
605 ゲート絶縁膜
607 種結晶
609 微結晶半導体膜
611 半導体膜
611a 微結晶半導体領域
611b 非晶質半導体領域
611c 半導体混相粒
613 不純物半導体膜
615 レジストマスク
615a レジストマスク
617 半導体積層体
617a 微結晶半導体領域
617b 非晶質半導体領域
621 不純物半導体膜
623 プラズマ
625 絶縁領域
627 導電膜
629a 配線
629b 配線
631a 一対の不純物半導体膜
631b 一対の不純物半導体膜
633 半導体積層体
633a 微結晶半導体領域
633b 一対の非晶質半導体領域
637 絶縁膜
639 バックゲート電極
643 半導体積層体
643a 微結晶半導体領域
643b 非晶質半導体領域
1000 テレビジョン装置
1001 筐体
1002 表示部
1004 筐体
1003 スピーカ
1005 操作キー
1006 接続端子
1007 センサ
1010 リモコン操作機
1011 表示部
1009 操作キー
2000 デジタルサイネージ
2002 筐体
2004 筐体
2006 表示部
2008 スピーカ
2010 スピーカ
Claims (4)
- 反応室を有するプラズマCVD装置を用いた半導体膜の作製方法であって、
前記反応室の第1の電極及び第2の電極の間に基板を配置し、
前記第1の電極に高周波電力を供給し前記反応室内にプラズマを発生させることによって、前記基板の端部よりも内側の領域上に半導体膜を形成し、
前記基板の端部上のプラズマ密度は、前記基板の端部よりも内側の領域上のプラズマ密度よりも高く、
前記基板の端部上の水素ラジカルの量は、前記基板の端部よりも内側の領域上よりも多いことを特徴とする半導体膜の作製方法。 - 請求項1において、
前記反応室に供給する水素の流量は一定であり、
前記反応室に供給する堆積性気体の流量を増減させることを特徴とする半導体膜の作製方法。 - 請求項1において
前記反応室に供給する堆積性気体の流量に対する水素の流量は、50倍以上2000倍以下であり、
前記反応室内の圧力は、5000Pa以上50000Pa以下であり、
前記第1の電極に供給する前記高周波電力は100W以上1300W以下であることを特徴とする半導体膜の作製方法。 - 反応室を有するプラズマCVD装置を用いた半導体膜の作製方法であって、
前記反応室の第1の電極及び第2の電極の間に基板を配置し、
前記第1の電極に高周波電力を供給することにより前記反応室内にプラズマを発生させることによって、前記基板上に半導体膜を形成し、
前記半導体膜に水素プラズマ処理を行うことによって、前記基板の端部上の前記半導体膜を選択的に除去し、
前記水素プラズマ処理において、前記基板の端部上のプラズマ密度は、前記基板の端部よりも内側の領域上のプラズマ密度よりも高く、
前記水素プラズマ処理において、前記基板の端部上の水素ラジカルの量は、前記基板の端部よりも内側の領域上よりも多いことを特徴とする半導体膜の作製方法。
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US20130188324A1 (en) * | 2010-09-29 | 2013-07-25 | Posco | Method for Manufacturing a Flexible Electronic Device Using a Roll-Shaped Motherboard, Flexible Electronic Device, and Flexible Substrate |
US9939728B2 (en) | 2011-09-12 | 2018-04-10 | Mapper Lithography Ip B.V. | Vacuum chamber with a thick aluminum base plate |
JP5401583B2 (ja) * | 2012-06-11 | 2014-01-29 | 日東電工株式会社 | 有機elデバイスの製造方法、および、有機elデバイス |
JP6754763B2 (ja) * | 2015-07-03 | 2020-09-16 | 株式会社半導体エネルギー研究所 | 液晶表示装置 |
CN106125372B (zh) * | 2016-09-20 | 2019-06-21 | 深圳市华星光电技术有限公司 | 一种基板加电探针组件 |
JP6760833B2 (ja) * | 2016-12-20 | 2020-09-23 | 株式会社Kokusai Electric | 半導体装置の製造方法、基板処理装置、およびプログラム |
JP7180984B2 (ja) * | 2018-03-01 | 2022-11-30 | 株式会社ニューフレアテクノロジー | 気相成長方法 |
CN110527986A (zh) * | 2019-10-18 | 2019-12-03 | 南京华伯新材料有限公司 | 一种pecvd薄膜沉积腔室及pecvd工艺 |
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