JP5933968B2 - Nandメモリ用デコーダ - Google Patents
Nandメモリ用デコーダ Download PDFInfo
- Publication number
- JP5933968B2 JP5933968B2 JP2011279867A JP2011279867A JP5933968B2 JP 5933968 B2 JP5933968 B2 JP 5933968B2 JP 2011279867 A JP2011279867 A JP 2011279867A JP 2011279867 A JP2011279867 A JP 2011279867A JP 5933968 B2 JP5933968 B2 JP 5933968B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- high voltage
- level shifter
- decoder
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000000295 complement effect Effects 0.000 description 8
- 101000739577 Homo sapiens Selenocysteine-specific elongation factor Proteins 0.000 description 7
- 102100037498 Selenocysteine-specific elongation factor Human genes 0.000 description 7
- 238000012790 confirmation Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 101100256578 Homo sapiens SELENOH gene Proteins 0.000 description 1
- 102100023840 Selenoprotein H Human genes 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000009414 blockwork Methods 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0028—Word-line or row circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
- H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
Description
M4はオフで、VoutはVhvに依存しない。VinがVddに近づくと、M2はオンになり、ノードVswの電圧を上昇させる。トランジスタM1はVswの電圧上昇に、VswがVDD−(M1のVth)に等しくなるまで貢献する。この時、M1はダイオード接続となり、この回路のインバータとして示された低電圧部分を隔離する。ノードVsbとノードVswの間の正帰還(M2とM3を介する)により電圧Vswは値Vhvに達する。
SSL 列選択線
GSL グランド選択線
GWL[31:0] グローバルワード線
GSSL グローバル列選択線
GGSL グローバルグランド選択線
Claims (4)
- デコーダ信号を受信し、第1電圧範囲のレベルシフター電圧出力を供給する出力を有するレベルシフターと、
該レベルシフターの該出力に結合され、該第1電圧範囲より広い第2電圧範囲のプルアップ回路電圧出力をメモリアレイのストリングに接続されたトランジスタに供給する出力を有するプルアップ回路と
を備え、
前記レベルシフターは負レベルシフターであり、
該レベルシフターの前記第1電圧範囲は該レベルシフターに結合された負第1バイアス電圧と正第2バイアス電圧とにより設定され、
前記第2電圧範囲は前記プルアップ回路に結合された正第3バイアス電圧と該負第1バイアス電圧とにより設定され、
消去時、非選択動作中に、前記プルアップ回路電圧出力は前記負第1バイアス電圧に等しい電圧である集積回路高電圧スイッチ装置。 - 消去時、選択動作中に、前記プルアップ回路電圧出力は前記正第3バイアス電圧に等しい電圧である請求項1に記載の装置。
- 前記レベルシフター電圧出力の前記第1電圧範囲は、デコーダからの前記デコーダ信号にない大きさの負電圧を含み、該デコーダ信号より広い請求項1に記載の装置。
- 前記プルアップ回路電圧出力の前記第2電圧範囲は、デコーダからの前記デコーダ信号にない大きさの負電圧と該デコーダ信号にない大きさの正電圧とを含み、該デコーダ信号より広い請求項1に記載の装置。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201061427040P | 2010-12-23 | 2010-12-23 | |
US61/427,040 | 2010-12-23 | ||
US13/185,887 US8638618B2 (en) | 2010-12-23 | 2011-07-19 | Decoder for NAND memory |
US13/185,887 | 2011-07-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012133876A JP2012133876A (ja) | 2012-07-12 |
JP5933968B2 true JP5933968B2 (ja) | 2016-06-15 |
Family
ID=46316605
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011279867A Active JP5933968B2 (ja) | 2010-12-23 | 2011-12-21 | Nandメモリ用デコーダ |
Country Status (5)
Country | Link |
---|---|
US (1) | US8638618B2 (ja) |
JP (1) | JP5933968B2 (ja) |
KR (2) | KR20120093052A (ja) |
CN (1) | CN102543185B (ja) |
TW (1) | TWI497503B (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8395434B1 (en) * | 2011-10-05 | 2013-03-12 | Sandisk Technologies Inc. | Level shifter with negative voltage capability |
KR102072767B1 (ko) | 2013-11-21 | 2020-02-03 | 삼성전자주식회사 | 고전압 스위치 및 그것을 포함하는 불휘발성 메모리 장치 |
US9379705B2 (en) | 2014-02-21 | 2016-06-28 | Samsung Electronics Co., Ltd. | Integrated circuit and semiconductor device including the same |
US9589642B2 (en) * | 2014-08-07 | 2017-03-07 | Macronix International Co., Ltd. | Level shifter and decoder for memory |
CN104681088B (zh) * | 2015-02-28 | 2018-02-09 | 上海华虹宏力半导体制造有限公司 | 一种行地址译码电路 |
US9997208B1 (en) * | 2017-03-29 | 2018-06-12 | Qualcomm Incorporated | High-speed level shifter |
KR102467312B1 (ko) * | 2018-10-15 | 2022-11-14 | 삼성전자주식회사 | 고전압 스위치 회로 및 이를 포함하는 비휘발성 메모리 장치 |
US11626864B1 (en) | 2021-12-08 | 2023-04-11 | Macronix International Co., Ltd. | Level shift circuit |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH103794A (ja) * | 1996-06-12 | 1998-01-06 | Hitachi Ltd | 不揮発性記憶装置および駆動方法 |
US6002290A (en) * | 1997-12-23 | 1999-12-14 | Sarnoff Corporation | Crisscross voltage level shifter |
JP3694422B2 (ja) * | 1999-06-21 | 2005-09-14 | シャープ株式会社 | ロウデコーダ回路 |
JP3863330B2 (ja) * | 1999-09-28 | 2006-12-27 | 株式会社東芝 | 不揮発性半導体メモリ |
TWI222647B (en) * | 2003-07-17 | 2004-10-21 | Amic Technology Corp | Flash memory capable of utilizing one driving voltage output circuit to drive a plurality of word line drivers |
KR100476725B1 (ko) * | 2003-08-01 | 2005-03-16 | 삼성전자주식회사 | 바닥 레벨의 저전압원 감지 기능을 가지는 레벨 쉬프터 및레벨 쉬프팅 방법 |
JP2005268621A (ja) * | 2004-03-19 | 2005-09-29 | Toshiba Corp | 半導体集積回路装置 |
JPWO2006025099A1 (ja) * | 2004-08-31 | 2008-05-08 | スパンション エルエルシー | 不揮発性記憶装置、およびその制御方法 |
JP2006252624A (ja) * | 2005-03-09 | 2006-09-21 | Toshiba Corp | 半導体記憶装置 |
JP2007080373A (ja) * | 2005-09-14 | 2007-03-29 | Renesas Technology Corp | 不揮発性メモリ |
KR100725993B1 (ko) * | 2005-12-28 | 2007-06-08 | 삼성전자주식회사 | 누설 전류를 방지하는 로우 디코더 회로 및 이를 구비하는반도체 메모리 장치 |
US7551492B2 (en) | 2006-03-29 | 2009-06-23 | Mosaid Technologies, Inc. | Non-volatile semiconductor memory with page erase |
CN100552823C (zh) * | 2006-08-16 | 2009-10-21 | 上海华虹Nec电子有限公司 | 用于低压eeprom的字线电压切换电路 |
US7593259B2 (en) | 2006-09-13 | 2009-09-22 | Mosaid Technologies Incorporated | Flash multi-level threshold distribution scheme |
JP2008084471A (ja) * | 2006-09-28 | 2008-04-10 | Toshiba Corp | 半導体記憶装置 |
US20080117691A1 (en) * | 2006-11-17 | 2008-05-22 | Sharp Kabushiki Kaisha | Erasing circuit of nonvolatile semiconductor memory device |
KR101330710B1 (ko) * | 2007-11-01 | 2013-11-19 | 삼성전자주식회사 | 플래시 메모리 장치 |
US8295087B2 (en) | 2008-06-16 | 2012-10-23 | Aplus Flash Technology, Inc. | Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS |
JP5169773B2 (ja) * | 2008-11-27 | 2013-03-27 | 富士通セミコンダクター株式会社 | 半導体メモリ、半導体メモリの動作方法およびシステム |
JP4750906B2 (ja) * | 2009-04-30 | 2011-08-17 | Powerchip株式会社 | Nandフラッシュメモリデバイスのプログラミング方法 |
KR101596826B1 (ko) * | 2009-10-26 | 2016-02-23 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그것의 바이어스 전압 인가 방법 |
-
2011
- 2011-07-19 US US13/185,887 patent/US8638618B2/en active Active
- 2011-08-19 KR KR1020110082760A patent/KR20120093052A/ko active Application Filing
- 2011-08-19 TW TW100129807A patent/TWI497503B/zh active
- 2011-08-31 CN CN201110254319.3A patent/CN102543185B/zh active Active
- 2011-12-21 JP JP2011279867A patent/JP5933968B2/ja active Active
-
2018
- 2018-12-13 KR KR1020180160649A patent/KR20180134829A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
TW201227743A (en) | 2012-07-01 |
KR20180134829A (ko) | 2018-12-19 |
KR20120093052A (ko) | 2012-08-22 |
US20120163087A1 (en) | 2012-06-28 |
JP2012133876A (ja) | 2012-07-12 |
TWI497503B (zh) | 2015-08-21 |
CN102543185B (zh) | 2016-05-11 |
CN102543185A (zh) | 2012-07-04 |
US8638618B2 (en) | 2014-01-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5933968B2 (ja) | Nandメモリ用デコーダ | |
US7193897B2 (en) | NAND flash memory device capable of changing a block size | |
KR100705221B1 (ko) | 플래쉬 메모리 소자 및 이를 이용한 플래쉬 메모리 셀의소거 방법 | |
US8976600B2 (en) | Word line driver circuit for selecting and deselecting word lines | |
KR101931408B1 (ko) | 레벨 시프트 회로, 반도체 장치 | |
KR100338772B1 (ko) | 바이어스 라인이 분리된 비휘발성 메모리 장치의 워드라인 드라이버 및 워드 라인 드라이빙 방법 | |
US6477091B2 (en) | Method, apparatus, and system to enhance negative voltage switching | |
US9219482B2 (en) | High voltage switch circuit and nonvolatile memory including the same | |
JP2007305283A (ja) | 消去動作時にメモリセルブロックのサイズを選択的に変更する機能を有するフラッシュメモリ装置及びその消去方法 | |
US9129685B2 (en) | Word-line driver for memory | |
KR100519793B1 (ko) | 플래쉬 메모리 장치 및 이 장치의 프로그램 방법 | |
US6044020A (en) | Nonvolatile semiconductor memory device with a row decoder circuit | |
KR100725993B1 (ko) | 누설 전류를 방지하는 로우 디코더 회로 및 이를 구비하는반도체 메모리 장치 | |
US9293181B2 (en) | Block selection circuit and semiconductor device having the same | |
EP2728582B1 (en) | Control gate word line driver circuit for multigate memory | |
US20200402578A1 (en) | Flash memory and method for operating the same | |
JP2011175708A (ja) | 半導体記憶装置のデコーダ回路 | |
KR100784108B1 (ko) | 데이터 입력 에러를 감소시키는 기능을 가지는 플래시메모리 소자 및 그 데이터 입력 동작 방법 | |
KR100250752B1 (ko) | 플래쉬 메모리에서의 디코더회로 | |
US20110069571A1 (en) | Word Line Decoder Circuit Apparatus and Method | |
TWI482431B (zh) | 準位轉換電路 | |
KR102328355B1 (ko) | 반도체 기억장치 및 프리차지 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140630 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150126 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150224 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20150522 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150624 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20151117 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160316 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20160324 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160426 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160506 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5933968 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |