JP5897337B2 - 抵抗性メモリ装置、そのレイアウト構造及びセンシング回路 - Google Patents
抵抗性メモリ装置、そのレイアウト構造及びセンシング回路 Download PDFInfo
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- JP5897337B2 JP5897337B2 JP2012006839A JP2012006839A JP5897337B2 JP 5897337 B2 JP5897337 B2 JP 5897337B2 JP 2012006839 A JP2012006839 A JP 2012006839A JP 2012006839 A JP2012006839 A JP 2012006839A JP 5897337 B2 JP5897337 B2 JP 5897337B2
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- 230000015654 memory Effects 0.000 claims description 108
- 230000004044 response Effects 0.000 claims description 15
- 238000010586 diagram Methods 0.000 description 11
- 230000007423 decrease Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 101150002757 RSL1 gene Proteins 0.000 description 1
- 102000000582 Retinoblastoma-Like Protein p107 Human genes 0.000 description 1
- 108010002342 Retinoblastoma-Like Protein p107 Proteins 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- QYYXITIZXRMPSZ-UHFFFAOYSA-N n'-tert-butyl-n'-(3,5-dimethylbenzoyl)-2-ethyl-3-methoxybenzohydrazide Chemical compound CCC1=C(OC)C=CC=C1C(=O)NN(C(C)(C)C)C(=O)C1=CC(C)=CC(C)=C1 QYYXITIZXRMPSZ-UHFFFAOYSA-N 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0026—Bit-line or column circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/82—Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Description
310 第1メモリ領域
320 第2メモリ領域
330 ローアドレスデコーダー部
340 コラムアドレスデコーダー
350 ビットラインドライバー/シンカー
40 センシング回路
410 第1シンク部
420 第2シンク部
430 感知部
440 比較部
Claims (3)
- メインメモリセルアレイ及び複数のレファレンスワードラインに接続されるように形成されるレファレンスセルアレイを含む複数のメモリ領域と、隣接するメモリ領域の間に共有されるビットラインドライバー/シンカーとを具備する抵抗性メモリ装置のためのセンシング回路であって、
リードイネーブル信号に応答して、選択されたメモリ領域と前記ビットラインドライバー/シンカーを共有する隣接メモリ領域のレファレンスセルに接続されたソースラインを接地端子へ連結する第1シンク部と、
リードイネーブル信号に応答して選択されたメモリ領域のメインメモリセルに接続されたソースラインを接地端子へ連結する第2シンク部と、
前記隣接メモリ領域のレファレンスセルに連結されたビットライン及び前記選択されたメモリ領域のメインメモリセルに連結されたビットラインに接続されて、前記選択されたメモリ領域のメインメモリセルのデータをセンシングして予備出力端子へ出力する感知部と、
基準電圧と前記予備出力端子の電圧とを比較してリードデータを出力する比較部とを具備する抵抗性メモリ装置のためのセンシング回路。 - 前記感知部が、
前記隣接メモリ領域のレファレンスセルに連結されたビットライン及び前記選択されたメモリ領域のメインメモリセルに連結されたビットラインへ電流を供給するローディング部と、
前記リードイネーブル信号に応答して前記ローディング部の出力電流を前記選択された
メモリ領域のビットライン及び前記隣接メモリ領域のビットラインへ提供するスイッチング部とを具備することを特徴とする、請求項1に記載の抵抗性メモリ装置のためのセンシング回路。 - 前記ローディング部が、
電源電圧端子及び前記隣接メモリ領域のビットラインの間に接続され、第2選択信号によって駆動されて前記隣接メモリ領域のビットラインに流出される電流を供給する第1電流生成部と、
電源電圧端子及び前記選択されたメモリ領域のビットラインの間に接続され、第1選択信号によって駆動されて前記選択されたメモリ領域のビットラインに流出された電流を供給する第2電流生成部と、
前記リードイネーブル信号によって駆動されて前記第1電流生成部と前記第2電流生成部との間に接続されるスイッチング部と、
前記第1電流生成部の出力電圧または前記第2電流生成部の出力電圧を前記予備出力端子へ提供する出力部とを具備することを特徴とする、請求項2に記載の抵抗性メモリ装置のためのセンシング回路。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2011-0104512 | 2011-10-13 | ||
KR1020110104512A KR101298190B1 (ko) | 2011-10-13 | 2011-10-13 | 저항성 메모리 장치, 그 레이아웃 구조 및 센싱 회로 |
Publications (2)
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JP2013089279A JP2013089279A (ja) | 2013-05-13 |
JP5897337B2 true JP5897337B2 (ja) | 2016-03-30 |
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JP2012006839A Active JP5897337B2 (ja) | 2011-10-13 | 2012-01-17 | 抵抗性メモリ装置、そのレイアウト構造及びセンシング回路 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8811059B2 (ja) |
JP (1) | JP5897337B2 (ja) |
KR (1) | KR101298190B1 (ja) |
CN (1) | CN103050148B (ja) |
TW (1) | TWI582771B (ja) |
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US20150071020A1 (en) * | 2013-09-06 | 2015-03-12 | Sony Corporation | Memory device comprising tiles with shared read and write circuits |
KR102116879B1 (ko) * | 2014-05-19 | 2020-06-01 | 에스케이하이닉스 주식회사 | 전자 장치 |
CN104051009B (zh) * | 2014-06-20 | 2017-02-15 | 中国科学院微电子研究所 | 一种电阻转变随机存储器rram的选通电路及选通方法 |
US9275714B1 (en) * | 2014-09-26 | 2016-03-01 | Qualcomm Incorporated | Read operation of MRAM using a dummy word line |
US9318190B1 (en) * | 2014-09-30 | 2016-04-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device |
CN105741874B (zh) * | 2014-12-08 | 2019-10-25 | 中芯国际集成电路制造(上海)有限公司 | 用于快闪存储器的双位线读出电路和读出方法 |
US9299430B1 (en) * | 2015-01-22 | 2016-03-29 | Nantero Inc. | Methods for reading and programming 1-R resistive change element arrays |
US9496036B1 (en) * | 2015-11-30 | 2016-11-15 | Winbond Electronics Corp. | Writing method for resistive memory cell and resistive memory |
US9679643B1 (en) | 2016-03-09 | 2017-06-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Resistive memory device having a trimmable resistance of at least on of a driver and a sinker is trimmed based on a row location |
KR102643710B1 (ko) * | 2016-09-20 | 2024-03-06 | 에스케이하이닉스 주식회사 | 저항 변화 메모리 장치 |
US10290327B2 (en) * | 2017-10-13 | 2019-05-14 | Nantero, Inc. | Devices and methods for accessing resistive change elements in resistive change element arrays |
KR102445560B1 (ko) * | 2018-03-09 | 2022-09-22 | 에스케이하이닉스 주식회사 | 저항성 메모리 장치 및 그의 동작 방법 |
TWI708253B (zh) * | 2018-11-16 | 2020-10-21 | 力旺電子股份有限公司 | 非揮發性記憶體良率提升的設計暨測試方法 |
CN111223508B (zh) * | 2018-11-27 | 2021-11-16 | 华邦电子股份有限公司 | 存储器存储装置及其电阻式存储器元件成型方法 |
CN111724847A (zh) * | 2020-06-03 | 2020-09-29 | 厦门半导体工业技术研发有限公司 | 一种半导体集成电路器件及其使用方法 |
US11508436B2 (en) * | 2020-09-29 | 2022-11-22 | Sharp Semiconductor Innovation Corporation | Memory device |
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KR100300549B1 (ko) | 1999-06-16 | 2001-11-01 | 김영환 | 비휘발성 메모리 센싱장치 및 방법 |
JP2002100181A (ja) * | 2000-09-27 | 2002-04-05 | Nec Corp | 磁気ランダムアクセスメモリ |
KR100418521B1 (ko) * | 2001-06-11 | 2004-02-11 | 삼성전자주식회사 | 계층적 섹터구조를 갖는 불휘발성 반도체 메모리 장치 |
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2011
- 2011-10-13 KR KR1020110104512A patent/KR101298190B1/ko active IP Right Grant
- 2011-12-28 US US13/339,159 patent/US8811059B2/en active Active
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2012
- 2012-01-17 JP JP2012006839A patent/JP5897337B2/ja active Active
- 2012-01-20 TW TW101102470A patent/TWI582771B/zh active
- 2012-03-09 CN CN201210061018.3A patent/CN103050148B/zh active Active
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Publication number | Publication date |
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US20130094277A1 (en) | 2013-04-18 |
CN103050148B (zh) | 2017-06-09 |
TWI582771B (zh) | 2017-05-11 |
CN103050148A (zh) | 2013-04-17 |
KR20130039872A (ko) | 2013-04-23 |
TW201316338A (zh) | 2013-04-16 |
JP2013089279A (ja) | 2013-05-13 |
KR101298190B1 (ko) | 2013-08-20 |
US8811059B2 (en) | 2014-08-19 |
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