JP5895374B2 - Electronic components - Google Patents

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JP5895374B2
JP5895374B2 JP2011140550A JP2011140550A JP5895374B2 JP 5895374 B2 JP5895374 B2 JP 5895374B2 JP 2011140550 A JP2011140550 A JP 2011140550A JP 2011140550 A JP2011140550 A JP 2011140550A JP 5895374 B2 JP5895374 B2 JP 5895374B2
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acoustic wave
electrode
electrodes
rectangular electrode
surface acoustic
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JP2013009158A (en
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一郎 松田
一郎 松田
渡辺　寛樹
寛樹 渡辺
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Description

本発明は、電子部品に関し、特に、実装基板の裏面上に裏面電極を有する電子部品に関する。   The present invention relates to an electronic component, and more particularly to an electronic component having a back electrode on the back surface of a mounting substrate.

近年、携帯電話のＲＦ段に弾性表面波装置が用いられるようになっている。例えば特許文献１には、弾性表面波素子を実装基板の上面（実装面）にフリップチップ実装してなる弾性表面波装置が記載されている。実装基板の下面（裏面）には、弾性表面波装置の外部端子である複数の裏面電極と、裏面電極の周囲と覆うソルダーレジストとが形成されている。   In recent years, surface acoustic wave devices have been used in the RF stage of mobile phones. For example, Patent Document 1 describes a surface acoustic wave device in which a surface acoustic wave element is flip-chip mounted on an upper surface (mounting surface) of a mounting substrate. A plurality of back surface electrodes, which are external terminals of the surface acoustic wave device, and a solder resist that covers and surrounds the back surface electrodes are formed on the bottom surface (back surface) of the mounting substrate.

特開平１１−２６６２３号公報JP 11-26623 A

しかしながら、同じ弾性表面波素子を使用する弾性表面波装置であっても、携帯電話のセットメーカや携帯電話のモデルによって要求される裏面電極の配置は異なる場合があり、裏面電極の配置が異なる実装基板を複数用意する必要があった。   However, even in a surface acoustic wave device that uses the same surface acoustic wave element, the required arrangement of the back electrode may differ depending on the mobile phone set manufacturer or the model of the mobile phone, and the arrangement of the back electrode is different. It was necessary to prepare a plurality of substrates.

本発明は、上記のような問題に鑑みてなされたものであり、本発明の目的は、異なる裏面電極の配置の要求に適用可能である実装基板を備える電子部品を提供することにある。   The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an electronic component including a mounting substrate that can be applied to the requirements for disposition of different backside electrodes.

本発明に係る電子部品は、１つの局面では、実装面と裏面とを有する基板と、基板の実装面に搭載される電気素子と、基板の裏面上に形成され、電気素子と電気的に接続される複数の裏面電極と、複数の裏面電極を覆うように基板の裏面上に形成された被膜とを備えた電子部品であって、複数の裏面電極の少なくとも１つは、一方の矩形状の電極部の面積が他方の矩形状の電極部の面積よりも小さく、一方の矩形状の電極部の一角のみが他方の矩形状の電極部と重なり、全体として１つの矩形状とならないように互いに一部を共有して構成され、被膜は、２つまたは３つの矩形状の電極部の少なくとも１つにおいて２つまたは３つの矩形状の電極部のいずれか１つの全体を露出させるように窓開けされている。 In one aspect, an electronic component according to the present invention is formed on a substrate having a mounting surface and a back surface, an electric element mounted on the mounting surface of the substrate, and a back surface of the substrate, and is electrically connected to the electric element. An electronic component comprising a plurality of back electrodes and a coating formed on the back surface of the substrate so as to cover the plurality of back electrodes, wherein at least one of the plurality of back electrodes is one rectangular shape The area of the electrode part is smaller than the area of the other rectangular electrode part, and only one corner of one rectangular electrode part overlaps with the other rectangular electrode part so that they do not form one rectangular shape as a whole. The coating is configured to share a part, and the window is opened so that at least one of the two or three rectangular electrode portions exposes any one of the two or three rectangular electrode portions. Has been.

本発明に係る電子部品は、他の局面では、実装面と裏面とを有する基板と、基板の実装面に搭載される電気素子と、基板の裏面上に形成され、電気素子と電気的に接続される複数の裏面電極と、複数の裏面電極を覆うように基板の裏面上に形成された被膜とを備えた電子部品であって、複数の裏面電極の少なくとも１つは、一方の矩形状の電極部の面積が他方の矩形状の電極部の面積よりも小さく、一方の矩形状の電極部の一角が他方の矩形状の電極部と重なり、全体として１つの矩形状とならないように互いに一部を共有して構成され、被膜は、２つまたは３つの矩形状の電極部の少なくとも１つにおいて２つまたは３つの矩形状の電極部のいずれか１つのみの全体を露出させるように窓開けされている。
１つの実施態様では、上記電子部品は、弾性表面波装置である。 In another aspect, the electronic component according to the present invention is formed on a substrate having a mounting surface and a back surface, an electric element mounted on the mounting surface of the substrate, and an electrically connected to the electric element. An electronic component comprising a plurality of back electrodes and a coating formed on the back surface of the substrate so as to cover the plurality of back electrodes, wherein at least one of the plurality of back electrodes is one rectangular shape The area of the electrode portion is smaller than the area of the other rectangular electrode portion, and one corner of one rectangular electrode portion overlaps with the other rectangular electrode portion so that they do not form one rectangular shape as a whole. The window is configured to expose only one of the two or three rectangular electrode portions in at least one of the two or three rectangular electrode portions. Opened.
In one embodiment, the electronic component is a surface acoustic wave device.

本発明によれば、実装基板の共用が可能となり、その結果、電子部品のコストの増大を抑制することができる。   According to the present invention, the mounting substrate can be shared, and as a result, an increase in the cost of the electronic component can be suppressed.

本発明の実施の形態１〜３に係る電子部品としての弾性表面波デュプレクサの回路構成を模式的に示す図である。It is a figure which shows typically the circuit structure of the surface acoustic wave duplexer as an electronic component which concerns on Embodiment 1-3 of this invention. 図１に示す弾性表面波デュプレクサの模式的断面図である。It is typical sectional drawing of the surface acoustic wave duplexer shown in FIG. 本発明の実施の形態１に係る弾性表面波デュプレクサ（電子部品）における裏面電極を示す図である。It is a figure which shows the back surface electrode in the surface acoustic wave duplexer (electronic component) which concerns on Embodiment 1 of this invention. 図３に示す裏面電極上にレジストパターンを形成した状態を示す図（その１）である。FIG. 4 is a diagram (No. 1) illustrating a state in which a resist pattern is formed on the back electrode illustrated in FIG. 3. 図３に示す裏面電極上にレジストパターンを形成した状態を示す図（その２）である。FIG. 4 is a diagram (No. 2) illustrating a state in which a resist pattern is formed on the back electrode illustrated in FIG. 3. 図３に示す裏面電極の変形例を示す図である。It is a figure which shows the modification of the back surface electrode shown in FIG. 本発明の実施の形態２に係る弾性表面波フィルタ（電子部品）における裏面電極を示す図である。It is a figure which shows the back surface electrode in the surface acoustic wave filter (electronic component) which concerns on Embodiment 2 of this invention. 図７に示す裏面電極上にレジストパターンを形成した状態を示す図（その１）である。FIG. 8 is a diagram (No. 1) illustrating a state in which a resist pattern is formed on the back electrode illustrated in FIG. 7. 図７に示す裏面電極上にレジストパターンを形成した状態を示す図（その２）である。FIG. 8 is a diagram (No. 2) illustrating a state in which a resist pattern is formed on the back electrode illustrated in FIG. 7. 本発明の実施の形態３に係るデュアル弾性表面波フィルタ（電子部品）における裏面電極を示す図である。It is a figure which shows the back surface electrode in the dual surface acoustic wave filter (electronic component) which concerns on Embodiment 3 of this invention. 図１０に示す裏面電極上にレジストパターンを形成した状態を示す図（その１）である。FIG. 11 is a diagram (No. 1) illustrating a state in which a resist pattern is formed on the back electrode illustrated in FIG. 10. 図１０に示す裏面電極上にレジストパターンを形成した状態を示す図（その２）である。FIG. 11 is a diagram (No. 2) illustrating a state in which a resist pattern is formed on the back electrode illustrated in FIG. 10. 図１０に示す裏面電極上にレジストパターンを形成した状態を示す図（その３）である。FIG. 11 is a diagram (No. 3) illustrating a state in which a resist pattern is formed on the back electrode illustrated in FIG. 10.

以下に、本発明の実施の形態について説明する。なお、同一または相当する部分に同一の参照符号を付し、その説明を繰返さない場合がある。   Embodiments of the present invention will be described below. Note that the same or corresponding portions are denoted by the same reference numerals, and the description thereof may not be repeated.

なお、以下に説明する実施の形態において、個数、量などに言及する場合、特に記載がある場合を除き、本発明の範囲は必ずしもその個数、量などに限定されない。また、以下の実施の形態において、各々の構成要素は、特に記載がある場合を除き、本発明にとって必ずしも必須のものではない。   Note that in the embodiments described below, when referring to the number, amount, and the like, the scope of the present invention is not necessarily limited to the number, amount, and the like unless otherwise specified. In the following embodiments, each component is not necessarily essential for the present invention unless otherwise specified.

図１は、後述する実施の形態１〜３に係る電子部品としてのデュプレクサ１０の回路構成を模式的に示す図である。   FIG. 1 is a diagram schematically showing a circuit configuration of a duplexer 10 as an electronic component according to Embodiments 1 to 3 described later.

図１に示すデュプレクサ１０は、たとえば、携帯電話機などのＲＦ回路に搭載されるものである。デュプレクサ１０は、ＵＭＴＳ−ＢＡＮＤ２に対応するデュプレクサである。ＵＭＴＳ−ＢＡＮＤ２の送信周波数帯は、１８５０〜１９１０ＭＨｚであり、受信周波数帯は、１９３０〜１９９０ＭＨｚである。   A duplexer 10 shown in FIG. 1 is mounted on an RF circuit such as a mobile phone, for example. The duplexer 10 is a duplexer corresponding to UMTS-BAND2. The transmission frequency band of UMTS-BAND2 is 1850 to 1910 MHz, and the reception frequency band is 1930 to 1990 MHz.

デュプレクサ１０は、送信フィルタ１１と、受信フィルタ１２と、送信端子１３と、第１の受信端子１４Ａと、第２の受信端子１４Ｂと、アンテナに接続されるアンテナ端子１５とを有する。アンテナ端子１５と送信端子１３との間に、送信フィルタ１１が接続されている。また、アンテナ端子１５と第１の受信端子１４Ａおよび第２の受信端子１４Ｂとの間に、受信フィルタ１２が接続されている。アンテナ端子１５と送信フィルタ１１および受信フィルタ１２との間の接続点と、グラウンドとの間には、整合回路を構成するインダクタＬ１が接続されている。   The duplexer 10 includes a transmission filter 11, a reception filter 12, a transmission terminal 13, a first reception terminal 14A, a second reception terminal 14B, and an antenna terminal 15 connected to the antenna. A transmission filter 11 is connected between the antenna terminal 15 and the transmission terminal 13. The reception filter 12 is connected between the antenna terminal 15 and the first reception terminal 14A and the second reception terminal 14B. An inductor L1 constituting a matching circuit is connected between a connection point between the antenna terminal 15 and the transmission filter 11 and the reception filter 12 and the ground.

送信フィルタ１１は、ラダー型弾性表面波フィルタである。送信フィルタ１１は、直列腕共振子Ｓ１，Ｓ２，Ｓ３と、並列腕共振子Ｐ１，Ｐ２，Ｐ３とを有する。直列腕共振子Ｓ１，Ｓ２，Ｓ３と、並列腕共振子Ｐ１，Ｐ２，Ｐ３とのそれぞれは、ひとつの共振子として機能する複数の１ポート型弾性表面波共振子により構成されている。１ポート型弾性表面波共振子のそれぞれは、１つのＩＤＴ電極と、ＩＤＴ電極の弾性表面波伝搬方向両側に配置された２つの反射器とを有する。並列腕共振子Ｐ１，Ｐ２とグラウンドとの間には、インダクタＬ２が接続されている。並列腕共振子Ｐ３とグラウンドとの間には、インダクタＬ３が接続されている。送信フィルタ１１は、キャパシタＣ１とインダクタＬ４とからなるＬＣ共振回路を有する。   The transmission filter 11 is a ladder type surface acoustic wave filter. The transmission filter 11 includes series arm resonators S1, S2, and S3 and parallel arm resonators P1, P2, and P3. Each of the series arm resonators S1, S2, and S3 and the parallel arm resonators P1, P2, and P3 includes a plurality of one-port surface acoustic wave resonators that function as one resonator. Each of the 1-port surface acoustic wave resonators has one IDT electrode and two reflectors disposed on both sides of the IDT electrode in the surface acoustic wave propagation direction. An inductor L2 is connected between the parallel arm resonators P1 and P2 and the ground. An inductor L3 is connected between the parallel arm resonator P3 and the ground. The transmission filter 11 has an LC resonance circuit composed of a capacitor C1 and an inductor L4.

受信フィルタ１２は、平衡−不平衡変換機能を有するバランス型の縦結合共振子型弾性表面波フィルタである。縦結合共振子型弾性表面波フィルタは、４つの３ＩＤＴ型の縦結合共振子型弾性表面波フィルタ部と、８つの１ポート型弾性波表面共振子とを有する。４つの３ＩＤＴ型の縦結合共振子型弾性表面波フィルタ部のそれぞれは、３つのＩＤＴ電極と、ＩＤＴ電極の弾性表面波伝搬方向両側に配置された２つの反射器とを有する。８つの１ポート型弾性表面波共振子のそれぞれは、１つのＩＤＴ電極と、ＩＤＴ電極の弾性表面波伝搬方向両側に配置された２つの反射器とを有する。   The reception filter 12 is a balanced longitudinally coupled resonator type surface acoustic wave filter having a balanced-unbalanced conversion function. The longitudinally coupled resonator type surface acoustic wave filter has four 3IDT type longitudinally coupled resonator type surface acoustic wave filter sections and eight 1-port type surface acoustic wave resonators. Each of the four 3IDT type longitudinally coupled resonator type surface acoustic wave filter sections has three IDT electrodes and two reflectors arranged on both sides of the surface acoustic wave propagation direction of the IDT electrodes. Each of the eight one-port surface acoustic wave resonators has one IDT electrode and two reflectors disposed on both sides of the IDT electrode in the surface acoustic wave propagation direction.

図２は、デュプレクサ１０の模式的断面図である。図２に示すように、デュプレクサ１０は、弾性表面波素子（電気素子）１００と、互いに対向する実装面と裏面とを有する実装基板（基板）２００と、実装基板２００に形成された電極層３００と、実装基板２００の裏面側に形成されたレジストパターン（被膜）４００とを有する。   FIG. 2 is a schematic cross-sectional view of the duplexer 10. As shown in FIG. 2, the duplexer 10 includes a surface acoustic wave element (electric element) 100, a mounting substrate (substrate) 200 having a mounting surface and a back surface facing each other, and an electrode layer 300 formed on the mounting substrate 200. And a resist pattern (film) 400 formed on the back surface side of the mounting substrate 200.

弾性表面波素子１００はタンタル酸リチウム、ニオブ酸リチウム、水晶などの圧電基板からなり、圧電基板の一方主面にはＩＤＴ、配線、パッド電極などの図示しない電極が形成されている。弾性表面波素子１００は、パッド電極上に設けられたバンプ５００により、実装基板２００の実装面にフリップチップ実装されている。そして、弾性表面波素子１００は、封止樹脂６００によって封止されている。すなわち、デュプレクサ１０は、ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）型の弾性表面波デュプレクサである。   The surface acoustic wave element 100 is made of a piezoelectric substrate such as lithium tantalate, lithium niobate, or quartz. An electrode (not shown) such as an IDT, wiring, or pad electrode is formed on one main surface of the piezoelectric substrate. The surface acoustic wave element 100 is flip-chip mounted on the mounting surface of the mounting substrate 200 by bumps 500 provided on the pad electrodes. The surface acoustic wave element 100 is sealed with a sealing resin 600. That is, the duplexer 10 is a CSP (Chip Size Package) type surface acoustic wave duplexer.

実装基板２００は、第１誘電体層２１０および第２誘電体層２２０とからなる。電極３００は、第１電極層３１０と、第２電極層３２０と、第３電極層３３０とからなる。第１電極層３１０は実装基板２００の裏面に形成されており、弾性表面波デュプレクサの外部端子である複数の裏面電極を含む。第２電極層３２０は実装基板２００の内部に形成されており、複数の内部配線を含む。第３電極層３３０は実装基板２００の実装面に形成されており、弾性表面波素子１００のパッド電極にバンプを介して電気的に接続されている複数のランド電極と、ランド電極に接続されている引き回し配線とを含む。誘電体層２１０，２２０と、電極層３１０，３２０，３３０とは、交互に積層されている。そして、第１電極層３１０、第２電極層３２０、および第３電極層３３０は、実装基板の内部で図示しないビアホールを介して電気的に接続されている。誘電体層２１０，２２０は、たとえば、樹脂や、アルミナなどのセラミックスなどにより構成することができる。   The mounting substrate 200 includes a first dielectric layer 210 and a second dielectric layer 220. The electrode 300 includes a first electrode layer 310, a second electrode layer 320, and a third electrode layer 330. The first electrode layer 310 is formed on the back surface of the mounting substrate 200 and includes a plurality of back surface electrodes that are external terminals of the surface acoustic wave duplexer. The second electrode layer 320 is formed inside the mounting substrate 200 and includes a plurality of internal wirings. The third electrode layer 330 is formed on the mounting surface of the mounting substrate 200, and is connected to the land electrodes and a plurality of land electrodes that are electrically connected to the pad electrodes of the surface acoustic wave element 100 via bumps. Including routing wiring. Dielectric layers 210, 220 and electrode layers 310, 320, 330 are alternately stacked. The first electrode layer 310, the second electrode layer 320, and the third electrode layer 330 are electrically connected to each other through a via hole (not shown) inside the mounting substrate. Dielectric layers 210 and 220 can be made of, for example, resin, ceramics such as alumina, or the like.

後述する実施の形態１〜３において、弾性表面波素子１００は、上記送信フィルタ１１のインダクタＬ２，Ｌ３，Ｌ４を除いた部分と、受信フィルタ１２とが一体に形成されたものである。ただし、本発明においては、送信フィルタ１１のインダクタＬ２，Ｌ３，Ｌ４を除いた部分が設けられた送信側弾性表面波素子と、受信フィルタ１２が設けられた受信側弾性表面波素子とが、それぞれ別体に設けられていてもよい。   In the first to third embodiments to be described later, the surface acoustic wave element 100 is formed by integrally forming the transmission filter 11 except for the inductors L2, L3, and L4 and the reception filter 12. However, in the present invention, the transmission-side surface acoustic wave element provided with a portion excluding the inductors L2, L3, and L4 of the transmission filter 11 and the reception-side surface acoustic wave element provided with the reception filter 12 are respectively provided. It may be provided separately.

実施の形態１〜３に係る電子部品は、第１電極層３１０とレジストパターン４００とにその特徴を有するものである。詳細については、後述する。   The electronic components according to the first to third embodiments have the characteristics in the first electrode layer 310 and the resist pattern 400. Details will be described later.

（実施の形態１）
次に、実施の形態１に係る電子部品について図３〜図６を用いて説明する。本実施の形態に係る電子部品は、弾性表面波素子をアルミナから成る実装基板にバンプによりフリップチップ実装した、ＣＳＰタイプの弾性表面波デュプレクサである。 (Embodiment 1)
Next, the electronic component according to the first embodiment will be described with reference to FIGS. The electronic component according to the present embodiment is a CSP type surface acoustic wave duplexer in which a surface acoustic wave element is flip-chip mounted on a mounting substrate made of alumina by a bump.

本実施の形態に係る弾性表面波デュプレクサは、外形寸法が２．５×２．０ｍｍである矩形状の実装基板２００を備え、図３に示すように、実装基板２００の裏面に形成されている第１電極層３１０は、複数の裏面電極３１０ａ〜３１０ｉを含んでいる。このうち、裏面の中央に位置する裏面電極３１０ｉを除く、裏面の周縁側に位置する裏面電極３１０ａ〜３１０ｈのそれぞれは、互いに一部を共有する２つの矩形状電極部から構成されている。すなわち、２つの矩形状電極部のうち、一方の矩形状電極部は他方の矩形状電極部より実装基板２００の裏面の中心側に位置しており、一方の矩形状電極部の一角が他方の矩形状電極部と重なるように配置されている。また、本実施の形態では、一方の矩形状電極部の面積は他方の矩形状電極部の面積よりも小さくなっている。   The surface acoustic wave duplexer according to the present embodiment includes a rectangular mounting board 200 having an outer dimension of 2.5 × 2.0 mm, and is formed on the back surface of the mounting board 200 as shown in FIG. The first electrode layer 310 includes a plurality of back surface electrodes 310a to 310i. Among these, each of back surface electrodes 310a-310h located in the peripheral side of a back surface except the back surface electrode 310i located in the center of a back surface is comprised from two rectangular electrode parts which share a part mutually. That is, of the two rectangular electrode portions, one rectangular electrode portion is located closer to the center side of the back surface of the mounting substrate 200 than the other rectangular electrode portion, and one corner of the one rectangular electrode portion is the other. It arrange | positions so that it may overlap with a rectangular-shaped electrode part. Moreover, in this Embodiment, the area of one rectangular electrode part is smaller than the area of the other rectangular electrode part.

さらに、本実施の形態に係る弾性表面波デュプレクサでは、実装基板２００の裏面を覆うように絶縁性のレジストパターン４００が形成されており、レジストパターン４００は裏面電極３１０ａ〜３１０ｉの一部が露出するように窓開けされている。そして、レジストパターン４００は、図４に示すように裏面電極３１０ａ〜３１０ｈの一方の矩形状電極部の全体が露出するように窓開けされている場合と、図５に示すように裏面電極３１０ａ〜３１０ｈの他方の矩形状電極部の全体が露出するように窓開けされている場合がある。より具体的には、レジストパターン４００はフォトリソグラフィ法を用いて窓開けされており、パターンが異なる２種類のフォトマスクを使い分けることにより、露出領域を異ならせている。ここでは、図４に示す露出領域の配置が２．０×１．６ｍｍの外形寸法である従来の弾性表面波デュプレクサの裏面電極の配置とほぼ一致しており、図５に示す露出領域の配置が２．５×２．０ｍｍの外形寸法である他の従来の弾性表面波デュプレクサの裏面電極の配置とほぼ一致している。   Furthermore, in the surface acoustic wave duplexer according to the present embodiment, the insulating resist pattern 400 is formed so as to cover the back surface of the mounting substrate 200, and the back surface electrodes 310a to 310i are partially exposed in the resist pattern 400. So that windows are opened. The resist pattern 400 has a window opened so that the entire one of the rectangular electrodes of the back electrodes 310a to 310h is exposed as shown in FIG. 4, and the back electrode 310a to 310a as shown in FIG. A window may be opened so that the entire other rectangular electrode portion of 310h is exposed. More specifically, the resist pattern 400 is opened using a photolithographic method, and the exposed regions are made different by using two types of photomasks having different patterns. Here, the arrangement of the exposed region shown in FIG. 4 is substantially the same as the arrangement of the back surface electrode of the conventional surface acoustic wave duplexer having an outer dimension of 2.0 × 1.6 mm, and the arrangement of the exposed region shown in FIG. Is substantially the same as the arrangement of the back electrode of another conventional surface acoustic wave duplexer having an outer dimension of 2.5 × 2.0 mm.

このように、本実施の形態に係る弾性表面波デュプレクサでは、レジストパターン４００の形状を上記のように使い分けることで、同じ実装基板を用いながら、２種類（２．５×２．０ｍｍおよび２．０×１．６ｍｍ）の裏面電極の配置に対応することが可能である。したがって、実装基板の共用が可能となるため、電子部品の製造コストの増大を抑制することができる。   As described above, in the surface acoustic wave duplexer according to the present embodiment, the shape of the resist pattern 400 is properly used as described above, so that two types (2.5 × 2.0 mm and 2.. 0 × 1.6 mm) can be accommodated. Therefore, since the mounting substrate can be shared, an increase in the manufacturing cost of the electronic component can be suppressed.

また、裏面電極３１０ａ〜３１０ｈの露出していない部分はレジストパターン４００で被覆されているので、弾性表面波デュプレクサを搭載する回路基板における意図しない部分との電気的接触を回避することができる。   In addition, since the unexposed portions of the back electrodes 310a to 310h are covered with the resist pattern 400, electrical contact with unintended portions on the circuit board on which the surface acoustic wave duplexer is mounted can be avoided.

さらに、本実施の形態に係る弾性表面波デュプレクサは、２．０×１．６ｍｍの外形寸法である従来の弾性表面波デュプレクサより実装基板が大きいため、実装基板における配線の設計自由度も高い。そのため、本実施の形態に係る弾性表面波デュプレクサは、従来の弾性表面波デュプレクサに比べて、良好なアイソレーション特性や減衰特性などを得ることが可能となる。   Furthermore, since the surface acoustic wave duplexer according to the present embodiment has a larger mounting substrate than the conventional surface acoustic wave duplexer having an outer dimension of 2.0 × 1.6 mm, the degree of freedom in designing the wiring on the mounting substrate is high. Therefore, the surface acoustic wave duplexer according to the present embodiment can obtain better isolation characteristics, attenuation characteristics, and the like than the conventional surface acoustic wave duplexer.

なお、本実施の形態では、裏面電極３１０ｄにおける一方の矩形状電極部の一角が切り欠かれているが、これは弾性表面波デュプレクサを実装する方向性を識別するためである。このように、裏面電極３１０ａ〜３１０ｈを構成する２つの電極部は必ずしも矩形状である必要はない。裏面電極３１０ａ〜３１０ｈを構成する２つの電極部の形状は、弾性表面波デュプレクサを搭載する回路基板側の電極形状や用途に応じて適宜変更可能である。   In the present embodiment, one corner of the rectangular electrode portion of the back electrode 310d is cut away in order to identify the direction in which the surface acoustic wave duplexer is mounted. Thus, the two electrode portions constituting the back electrodes 310a to 310h do not necessarily have to be rectangular. The shapes of the two electrode portions constituting the back electrodes 310a to 310h can be appropriately changed according to the electrode shape on the circuit board side on which the surface acoustic wave duplexer is mounted and the application.

また、図６に示すように、裏面電極３１０ａ〜３１０ｉの形状を変形してもよい。図６において、実線で示す部分が変形例の裏面電極３１０ａ〜３１０ｉである。点線で示す部分は、比較するために、図３の裏面電極３１０ａ〜３１０ｈを重ね合わせたものである。変形例の裏面電極３１０ａ〜３１０ｈは、図３の裏面電極３１０ａ〜３１０ｈの角部（凹んだ部分）を埋める電極が追加されている。このように、裏面電極３１０ａ〜３１０ｈを構成する２つの電極部は、明確に区分されていなくともよい。   Moreover, as shown in FIG. 6, you may deform | transform the shape of the back surface electrodes 310a-310i. In FIG. 6, the portions indicated by the solid lines are the back surface electrodes 310a to 310i of the modified examples. The portions indicated by dotted lines are obtained by superimposing the back surface electrodes 310a to 310h of FIG. 3 for comparison. The back surface electrodes 310a to 310h of the modification are added with electrodes that fill corners (recessed portions) of the back surface electrodes 310a to 310h in FIG. As described above, the two electrode portions constituting the back surface electrodes 310a to 310h may not be clearly divided.

（実施の形態２）
次に、実施の形態２に係る電子部品について図７〜図９を用いて説明する。本実施の形態に係る電子部品は、弾性表面波フィルタである。本発明において、「電子部品」は、上述した弾性表面波デュプレクサに限らず、任意の表面実装品（ＳＭＤ品）に適用可能である。また、上述した誘電体層２１０，２２０は、樹脂プリント基板であってもよい。また、レジストパターン４００に代えて、セラミックスのコーティング材を用いて「被膜」を形成してもよい。 (Embodiment 2)
Next, an electronic component according to the second embodiment will be described with reference to FIGS. The electronic component according to the present embodiment is a surface acoustic wave filter. In the present invention, the “electronic component” is not limited to the surface acoustic wave duplexer described above, but can be applied to any surface-mounted product (SMD product). Further, the dielectric layers 210 and 220 described above may be resin printed boards. In place of the resist pattern 400, a “film” may be formed using a ceramic coating material.

図７に示すように、本実施の形態に係る弾性表面波フィルタにおいても、実施の形態１と同様に、実装基板２００の裏面に形成されている第１電極層３１０が、複数の裏面電極を含んでいる。ここでは、裏面の周縁側に位置する５つの裏面電極のうち、３つの裏面電極が互いに一部を共有する２つの矩形状電極部から構成されている。このように、裏面の周縁側に位置する裏面電極のすべてが、２つの矩形状電極部から構成されていなくともよい。   As shown in FIG. 7, also in the surface acoustic wave filter according to the present embodiment, the first electrode layer 310 formed on the back surface of the mounting substrate 200 includes a plurality of back electrodes, as in the first embodiment. Contains. Here, among the five back electrodes located on the peripheral side of the back surface, the three back electrodes are composed of two rectangular electrode portions that share a part of each other. Thus, all of the back surface electrodes located on the peripheral side of the back surface may not be composed of two rectangular electrode portions.

また、本実施の形態においても、実装基板２００の裏面を覆うように絶縁性のレジストパターン４００が形成されており、レジストパターン４００は、図８に示すように、一方の矩形状電極部の全体を露出させるように窓開けする場合と、図９に示すように、他方の矩形状電極部の全体を露出させるように窓開けする場合がある。このように、レジストパターン４００の形状を使い分けることで、同じ実装基板を用いながら、２種類の裏面電極の配置に対応することが可能である。   Also in the present embodiment, an insulating resist pattern 400 is formed so as to cover the back surface of the mounting substrate 200, and the resist pattern 400 is formed as a whole of one rectangular electrode portion as shown in FIG. There are cases where the window is opened so as to expose the window, and as shown in FIG. 9, the window is opened so that the entire other rectangular electrode section is exposed. As described above, by properly using the shape of the resist pattern 400, it is possible to cope with the arrangement of two types of back surface electrodes while using the same mounting substrate.

（実施の形態３）
次に、実施の形態３に係る電子部品について図１０〜図１３を用いて説明する。本実施の形態に係る電子部品は、デュアル弾性表面波フィルタである。 (Embodiment 3)
Next, an electronic component according to Embodiment 3 will be described with reference to FIGS. The electronic component according to the present embodiment is a dual surface acoustic wave filter.

図１０に示すように、本実施の形態に係るデュアル弾性表面波フィルタにおいても、実施の形態１、２と同様に、実装基板２００の裏面に形成されている第１電極層３１０が、複数の裏面電極を含んでいる。ここでは、複数の裏面電極が３つの矩形状電極部から構成されており、隣り合う２つの矩形状電極部は互いに一部を共有している。したがって、実装基板２００の裏面を覆うレジストパターン４００は、図１１〜図１３に示すように、３つの矩形状電極部の全体がそれぞれ露出するように、窓開けする場合がある。このように、レジストパターン４００の形状を使い分けることで、同じ実装基板を用いながら、３種類の裏面電極の配置に対応することが可能である。   As shown in FIG. 10, also in the dual surface acoustic wave filter according to the present embodiment, the first electrode layer 310 formed on the back surface of the mounting substrate 200 includes a plurality of the same as in the first and second embodiments. A back electrode is included. Here, the plurality of back surface electrodes are composed of three rectangular electrode portions, and two adjacent rectangular electrode portions share a part of each other. Therefore, as shown in FIGS. 11 to 13, the resist pattern 400 covering the back surface of the mounting substrate 200 may be opened so that the entire three rectangular electrode portions are respectively exposed. As described above, by properly using the shape of the resist pattern 400, it is possible to cope with the arrangement of the three types of back surface electrodes while using the same mounting substrate.

なお、裏面電極を構成する電極を４つ以上にすることによっては、４種類以上の裏面電極の配置に対応することも、当然可能である。   Of course, it is possible to correspond to the arrangement of four or more types of back electrode by using four or more electrodes constituting the back electrode.

以上、本発明の実施の形態について説明したが、今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。   Although the embodiments of the present invention have been described above, the embodiments disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

１０ デュプレクサ、１００ 弾性表面波素子、２００ 実装基板、２１０ 第１誘電体層、２２０ 第２誘電体層、３００ 電極、３１０ 第１電極層、３１０ａ〜３１０ｉ 裏面電極、３２０ 第２電極層、３３０ 第３電極層、４００ レジストパターン、５００ バンプ、６００ 封止樹脂。   DESCRIPTION OF SYMBOLS 10 Duplexer, 100 Surface acoustic wave element, 200 Mounting substrate, 210 1st dielectric layer, 220 2nd dielectric layer, 300 electrode, 310 1st electrode layer, 310a-310i Back surface electrode, 320 2nd electrode layer, 330 1st 3 electrode layers, 400 resist pattern, 500 bumps, 600 sealing resin.

Claims (3)

実装面と裏面とを有する基板と、
前記基板の前記実装面に搭載される電気素子と、
前記基板の前記裏面上に形成され、前記電気素子と電気的に接続される複数の裏面電極と、
前記複数の裏面電極を覆うように前記基板の前記裏面上に形成された被膜とを備えた電子部品であって、
前記複数の裏面電極の少なくとも１つは、２つまたは３つの矩形状の電極部のうち隣り合う２つの電極部が、一方の矩形状の電極部の面積が他方の矩形状の電極部の面積よりも小さく、一方の矩形状の電極部の一角のみが他方の矩形状の電極部と重なり、全体として１つの矩形状とならないように互いに一部を共有して構成され、
前記被膜は、前記２つまたは３つの矩形状の電極部の少なくとも１つにおいて前記２つまたは３つの矩形状の電極部のいずれか１つの全体を露出させるように窓開けされている、電子部品。 A substrate having a mounting surface and a back surface;
An electrical element mounted on the mounting surface of the substrate;
A plurality of back electrodes formed on the back surface of the substrate and electrically connected to the electrical element;
An electronic component comprising a coating formed on the back surface of the substrate so as to cover the plurality of back electrodes,
At least one of the plurality of back-surface electrodes has two or three rectangular electrode portions adjacent to each other, and the area of one rectangular electrode portion is the area of the other rectangular electrode portion. Less than one, and only one corner of one rectangular electrode portion overlaps with the other rectangular electrode portion, and is configured to share a part of each other so as not to form one rectangular shape as a whole,
The coating has a window opened so that at least one of the two or three rectangular electrode portions exposes any one of the two or three rectangular electrode portions. . 実装面と裏面とを有する基板と、
前記基板の前記実装面に搭載される電気素子と、
前記基板の前記裏面上に形成され、前記電気素子と電気的に接続される複数の裏面電極と、
前記複数の裏面電極を覆うように前記基板の前記裏面上に形成された被膜とを備えた電子部品であって、
前記複数の裏面電極の少なくとも１つは、２つまたは３つの矩形状の電極部のうち隣り合う２つの電極部が、一方の矩形状の電極部の面積が他方の矩形状の電極部の面積よりも小さく、一方の矩形状の電極部の一角が他方の矩形状の電極部と重なり、全体として１つの矩形状とならないように互いに一部を共有して構成され、
前記被膜は、前記２つまたは３つの矩形状の電極部の少なくとも１つにおいて前記２つまたは３つの矩形状の電極部のいずれか１つのみの全体を露出させるように窓開けされている、電子部品。 A substrate having a mounting surface and a back surface;
An electrical element mounted on the mounting surface of the substrate;
A plurality of back electrodes formed on the back surface of the substrate and electrically connected to the electrical element;
An electronic component comprising a coating formed on the back surface of the substrate so as to cover the plurality of back electrodes,
At least one of the plurality of back-surface electrodes has two or three rectangular electrode portions adjacent to each other, and the area of one rectangular electrode portion is the area of the other rectangular electrode portion. Smaller than, one corner of one rectangular electrode portion overlaps with the other rectangular electrode portion, and is configured to share a part of each other so that it does not become one rectangular shape as a whole,
The coating is windowed so as to expose only one of the two or three rectangular electrode portions in at least one of the two or three rectangular electrode portions , electronic components. 前記電子部品は、弾性表面波装置である、請求項１または請求項２に記載の電子部品。   The electronic component according to claim 1, wherein the electronic component is a surface acoustic wave device.
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