JP5838040B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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JP5838040B2
JP5838040B2 JP2011104804A JP2011104804A JP5838040B2 JP 5838040 B2 JP5838040 B2 JP 5838040B2 JP 2011104804 A JP2011104804 A JP 2011104804A JP 2011104804 A JP2011104804 A JP 2011104804A JP 5838040 B2 JP5838040 B2 JP 5838040B2
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insulating film
semiconductor device
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JP2012238627A (en
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勝治 吉田
勝治 吉田
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Lapis Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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Description

本発明は、基板上に備えられた電極パッドとこれを覆う絶縁膜とを有する半導体装置の製造方法及び半導体装置に関する。   The present invention relates to a method of manufacturing a semiconductor device having an electrode pad provided on a substrate and an insulating film covering the electrode pad, and a semiconductor device.

一般に、ウェハレベルチップサイズパッケージ（ＷＬ−ＣＳＰ）構造の半導体装置は、回路素子及び電極パッドが備えられた半導体ウェハ上に絶縁膜を形成し、絶縁膜に開口を形成し、開口を介して電極パッドに電気的に接続される再配線パターンを形成し、再配線パターンを覆うモールド樹脂を形成し、モールド樹脂に開口を形成し、再配線層に電気的に接続される半田バンプ等の外部接続端子を形成することによって、製造される。また、ウェハプロセス後であって絶縁膜形成前に、電極パッドにプロ−ビング装置のプロービング針（プローブピン）を接触させ、半導体ウェハの各チップ（半導体装置）が良品か不良品かの検査が行われる。   In general, in a semiconductor device having a wafer level chip size package (WL-CSP) structure, an insulating film is formed on a semiconductor wafer provided with circuit elements and electrode pads, an opening is formed in the insulating film, and an electrode is formed through the opening. Form a rewiring pattern that is electrically connected to the pad, form a mold resin that covers the rewiring pattern, form an opening in the mold resin, and external connections such as solder bumps that are electrically connected to the rewiring layer It is manufactured by forming a terminal. In addition, after the wafer process and before the formation of the insulating film, the probing needle (probe pin) of the probing device is brought into contact with the electrode pad to inspect whether each chip (semiconductor device) of the semiconductor wafer is good or defective. Done.

しかし、プロービング針を接触させることによって電極パッドの一部が削られ、電極パッドの表面に突起した部分を含むプロービング痕が発生することがある。プロ−ビング痕の突起した部分は、電極パッドを覆うように形成された絶縁膜上に突き出ることがあり、その場合には、絶縁膜上に突き出た部分が再配線パターンを断線させるなどの問題があった。   However, when the probing needle is brought into contact with the electrode pad, a part of the electrode pad is scraped, and a probing mark including a protruding portion on the surface of the electrode pad may be generated. The protruding part of the probing mark may protrude on the insulating film formed so as to cover the electrode pad, and in this case, the protruding part on the insulating film breaks the rewiring pattern. was there.

従来、このようなプロ−ビング痕に起因する問題に対して、種々の提案がある。例えば、特許文献１は、電極パッドのプロ−ビング痕を厚い絶縁膜によって被覆する方法を提案している。また、特許文献２は、電極パッドのプロ−ビング痕を再配線パターンで覆うことによって、プロ−ビング痕の突起した部分が封止樹脂に接しないようにする方法を提案している。また、特許文献３は、電極パッドのプロ−ビング痕の庇の下に感光性樹脂を設けると共に、プロ−ビング痕の上に複数層の電極膜を設ける方法を提案している。さらに、特許文献４は、電極パッド上の異物を除去する方法を提案している。   Conventionally, various proposals have been made for problems caused by such probing marks. For example, Patent Document 1 proposes a method of covering a probing mark on an electrode pad with a thick insulating film. Further, Patent Document 2 proposes a method in which the protruding portion of the probing mark is not in contact with the sealing resin by covering the probing mark of the electrode pad with a rewiring pattern. Patent Document 3 proposes a method in which a photosensitive resin is provided under the probing marks of the electrode pad and a plurality of electrode films are provided on the probing marks. Further, Patent Document 4 proposes a method for removing foreign matter on the electrode pad.

特開２００８−２３５５３９号公報（例えば、段落００２３、図１）JP 2008-235539 A (for example, paragraph 0023, FIG. 1) 特開２０１０−５０２２４号公報（例えば、段落００２４、図２）Japanese Patent Laying-Open No. 2010-50224 (for example, paragraph 0024, FIG. 2) 特開２００９−４９２９７号公報（例えば、段落００３２、図１２）JP 2009-49297 A (for example, paragraph 0032, FIG. 12) 特開平４−３６７２９５号公報（例えば、段落００１１、図１）JP-A-4-367295 (for example, paragraph 0011, FIG. 1)

しかし、特許文献１に示される方法では、絶縁膜の厚膜化によって半導体ウェハに生じる応力が増大するため、半導体ウェハに反りやクラックが発生し易くなるという問題がある。   However, the method disclosed in Patent Document 1 has a problem in that warping and cracking are likely to occur in the semiconductor wafer because the stress generated in the semiconductor wafer is increased by increasing the thickness of the insulating film.

特許文献２に示される方法では、プロービング痕の位置が一定でないため、再配線パターンで確実に覆うことができないことがあり、また、再配線パターンの厚さが不足する場合には、プロ−ビング痕の突起した部分が再配線パターンを断線させることがあるという問題がある。   In the method disclosed in Patent Document 2, since the position of the probing mark is not constant, it may not be reliably covered with the rewiring pattern, and when the thickness of the rewiring pattern is insufficient, the probing is performed. There is a problem that the protruding portion of the trace may break the rewiring pattern.

特許文献３に示される方法では、感光性樹脂層の形成、複数の電極膜の形成など、製造工程が非常に複雑になり、また、起伏のあるプロ−ビング痕の上に電極材料からなるポストを形成するので、電極パッドとその上の電極材料との良好な接続性を得難いという問題がある。   In the method disclosed in Patent Document 3, the manufacturing process such as formation of a photosensitive resin layer and formation of a plurality of electrode films becomes very complicated, and a post made of an electrode material on an uneven probing mark. Therefore, there is a problem that it is difficult to obtain good connectivity between the electrode pad and the electrode material thereon.

特許文献４に示される方法では、基板及び電極パッドが露出した状態で電極パッド上の異物を研磨して除去するので、電極パッドや基板内の回路素子にダメージを与えやすいという問題がある。   In the method disclosed in Patent Document 4, foreign matter on the electrode pad is polished and removed in a state where the substrate and the electrode pad are exposed, so that there is a problem that the electrode pad and circuit elements in the substrate are easily damaged.

そこで、本発明は、上記従来技術の課題を解決するためになされたものであり、その目的は、電極パッドの表面の突出部に起因する不具合が発生し難い半導体装置の製造方法及び半導体装置を提供することにある。   Accordingly, the present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a method of manufacturing a semiconductor device and a semiconductor device that are less likely to cause problems due to protrusions on the surface of the electrode pad. It is to provide.

本発明に係る半導体装置の製造方法は、表面に突出部を有する電極パッドを備える基板上に、前記突出部の上部を露出させると共に前記突出部の下部を覆うように前記電極パッドを覆う第１の絶縁膜を形成する第１の絶縁膜形成工程と、前記第１の絶縁膜の表面から突起した前記突出部の前記上部を除去する除去処理工程と、前記除去処理工程後に、前記第１の絶縁膜上及び前記突出部の前記下部の頂部上に第２の絶縁膜を形成する第２の絶縁膜形成工程とを有することを特徴としている。 The method of manufacturing a semiconductor device according to the present invention, on a substrate having an electrode pad having protrusions on the surface, the covering the electrode pad so as to cover the lower portion of the protruding portion to expose the upper portion of the projecting portion a first insulating film forming step of forming a first insulating film, said first insulating said you remove the top of the protrusion removal processing step projecting from the surface of the film, after it said removing step, the first And a second insulating film forming step of forming a second insulating film on the first insulating film and on the top of the lower portion of the projecting portion .

本発明に係る半導体装置は、基板と、前記基板上に備えられ、表面に突出部を有する電極パッドと、前記基板上に、前記突出部の頂部を露出させると共に前記突出部の側面を被覆するように前記電極パッドの表面を被覆する第１の絶縁膜と、前記第１の絶縁膜と前記突出部の頂部とを被覆する第２の絶縁膜とを有することを特徴としている。 A semiconductor device according to the present invention includes a substrate, an electrode pad provided on the substrate and having a protrusion on the surface, and the top of the protrusion is exposed and covers the side surface of the protrusion on the substrate. It is characterized by having as a first insulating film covering the surface of the electrode pad, and a second insulating film covering a top portion of the front Symbol the protruding portion and the first insulating film.

本発明に係る半導体装置の製造方法及び半導体装置によれば、半導体装置の電極パッドの表面の突出部に起因する不具合が発生し難いので、不良品の発生率を低下させることができるという効果がある。   According to the method for manufacturing a semiconductor device and the semiconductor device according to the present invention, it is difficult for a defect due to the protruding portion on the surface of the electrode pad of the semiconductor device to occur. is there.

本発明の実施の形態に係る半導体装置の製造方法の第１工程を概略的に示す縦断面図である。It is a longitudinal section showing roughly the 1st process of the manufacturing method of the semiconductor device concerning an embodiment of the invention. 本発明の実施の形態に係る半導体装置の製造方法の第２工程を概略的に示す縦断面図である。It is a longitudinal cross-sectional view which shows schematically the 2nd process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法の第３工程を概略的に示す縦断面図である。It is a longitudinal cross-sectional view which shows schematically the 3rd process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法の第４工程を概略的に示す縦断面図である。It is a longitudinal cross-sectional view which shows schematically the 4th process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法の第５工程を概略的に示す縦断面図である。It is a longitudinal cross-sectional view which shows schematically the 5th process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法の第６工程を概略的に示す縦断面図である。It is a longitudinal cross-sectional view which shows schematically the 6th process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法の第７工程を概略的に示す縦断面図である。It is a longitudinal cross-sectional view which shows schematically the 7th process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 第１比較例の半導体装置の製造方法の一工程を概略的に示す縦断面図である。It is a longitudinal cross-sectional view which shows roughly 1 process of the manufacturing method of the semiconductor device of a 1st comparative example. 第２比較例の半導体装置の製造方法の一工程を概略的に示す縦断面図である。It is a longitudinal cross-sectional view which shows roughly 1 process of the manufacturing method of the semiconductor device of a 2nd comparative example. 第３比較例の半導体装置の製造方法の一工程を概略的に示す縦断面図である。It is a longitudinal section showing roughly one process of a manufacturing method of a semiconductor device of the 3rd comparative example.

図１乃至図７は、本発明の実施の形態に係る半導体装置の製造方法の第１工程から第７工程までを概略的に示す縦断面図である。なお、図１乃至図７には、半導体ウェハの一部の縦断面が示されている。   1 to 7 are longitudinal sectional views schematically showing from the first step to the seventh step of the semiconductor device manufacturing method according to the embodiment of the present invention. 1 to 7 show a longitudinal section of a part of the semiconductor wafer.

実施の形態に係る半導体装置の製造方法においては、図１に示されるように、先ず、基板の一例としての半導体ウェハ１上に電極パッド２とパッシベーション膜（ＰＶ膜）３とを形成する。半導体ウェハ１は、内部にトランジスタ、コンデンサ、抵抗素子などの回路素子及び配線を含む集積回路を有している。半導体ウェハ１としては、シリコンウェハ又はガリウムヒ素ウェハなどを用いることができる。電極パッド２は、半導体ウェハ１内の集積回路に電気的に接続されており、例えば、アルミニウム（Ａｌ）、銅（Ｃｕ）、Ａｌ−Ｓｉ系合金、Ａｌ−Ｓｉ−Ｃｕ系合金などから構成される。電極パッド２は、例えば、メッキ法や蒸着法により形成することができる。ＰＶ膜３は、例えば、シリコン窒化膜などであり、半導体ウェハ１に機械的損傷、化学的損傷、電気的損傷などを与え難くしている。ＰＶ膜３は、例えば、蒸着法により形成することができる。図１に示される第１工程においては、電極パッド２は、ＰＶ膜３の開口から、表面（上面）を露出させている。   In the method of manufacturing a semiconductor device according to the embodiment, as shown in FIG. 1, first, an electrode pad 2 and a passivation film (PV film) 3 are formed on a semiconductor wafer 1 as an example of a substrate. The semiconductor wafer 1 has an integrated circuit including circuit elements such as transistors, capacitors, and resistance elements, and wiring. As the semiconductor wafer 1, a silicon wafer or a gallium arsenide wafer can be used. The electrode pad 2 is electrically connected to an integrated circuit in the semiconductor wafer 1, and is made of, for example, aluminum (Al), copper (Cu), Al—Si alloy, Al—Si—Cu alloy, or the like. The The electrode pad 2 can be formed by, for example, a plating method or a vapor deposition method. The PV film 3 is, for example, a silicon nitride film, and makes it difficult to cause mechanical damage, chemical damage, electrical damage, or the like to the semiconductor wafer 1. The PV film 3 can be formed by, for example, a vapor deposition method. In the first step shown in FIG. 1, the electrode pad 2 exposes the surface (upper surface) from the opening of the PV film 3.

次に、図２に示されるように、検査装置としてのプロ−ビング装置のプロービング針（プローブピン）１０１を電極パッド２に接触させ、半導体ウェハ１内の集積回路が良品であるか不良品であるかのテスト（例えば、動作確認）を行い、その後、電極パッド２からプロービング針１０１を離す。この工程を、プロ−ビング工程又は検査工程と言う。プロ−ビング針１０１は、例えば、タングステン（Ｗ）から構成される。このときのプロ−ビング針１０１の接触により、プロ−ビング針１０１よりも柔らかい材料で形成されている電極パッド２の表面に、突出部を含むプロ−ビング痕（プローブ痕）２１が形成される。プロ−ビング痕２１の形状及び大きさは、色々あるが、例えば、図２に示されるように、突起した部分２２を有するプロ−ビング痕２１が形成されることがある。   Next, as shown in FIG. 2, a probing needle (probe pin) 101 of a probing apparatus as an inspection apparatus is brought into contact with the electrode pad 2 so that the integrated circuit in the semiconductor wafer 1 is a good product or a defective product. A certain test (for example, operation check) is performed, and then the probing needle 101 is released from the electrode pad 2. This process is called a probing process or an inspection process. The probing needle 101 is made of, for example, tungsten (W). By the contact of the probing needle 101 at this time, a probing mark (probe mark) 21 including a protruding portion is formed on the surface of the electrode pad 2 formed of a material softer than the probing needle 101. . There are various shapes and sizes of the probing mark 21. For example, as shown in FIG. 2, the probing mark 21 having the protruding portion 22 may be formed.

次に、図３に示されるように、プロービング痕２１が存在する電極パッド２を備える基板１上に、電極パッド２の少なくとも一部を覆う第１の絶縁膜４を形成する。図３においては、第１の絶縁膜４は、プロ−ビング痕２１の突起した部分２２以外の部分を覆っている。第１の絶縁膜４の材料としては、例えば、ポリイミドを用いることができる。また、第１の絶縁膜４の材料として、ポリベンゾオキサゾール（ＰＢＯ）などの他の絶縁材料を用いることもできる。第１の絶縁膜４の膜厚は、最終的な絶縁膜（ここでは、第１の絶縁膜４と第２の絶縁膜５の膜厚の合計）の、３分の１から２の膜厚分の１程度の厚さとし、通常は２〜２０［μｍ］であり、図３に示されるように、プロ−ビング痕２１の突起した部分２２が露出していてもよい。なお、第１の絶縁層４を、複数の積層する絶縁層から構成してもよい。   Next, as shown in FIG. 3, the first insulating film 4 covering at least a part of the electrode pad 2 is formed on the substrate 1 including the electrode pad 2 on which the probing mark 21 is present. In FIG. 3, the first insulating film 4 covers a portion other than the protruding portion 22 of the probing mark 21. As a material of the first insulating film 4, for example, polyimide can be used. Further, as the material of the first insulating film 4, other insulating materials such as polybenzoxazole (PBO) can be used. The thickness of the first insulating film 4 is one third to two of the final insulating film (here, the total thickness of the first insulating film 4 and the second insulating film 5). The thickness is about one-half, and is usually 2 to 20 [μm]. As shown in FIG. 3, the protruding portion 22 of the probing mark 21 may be exposed. Note that the first insulating layer 4 may be composed of a plurality of stacked insulating layers.

次に、図４に示されるように、プロービング痕２１の内の、第１の絶縁膜４よりも上に突き出た部分２２を除去することができる除去処理工程を行う。除去処理工程としては、突き出た部分２２をエッチングにより除去する工程、又は、研磨装置１０２によって突き出た部分２２を機械的に研磨して除去する工程を採用することができる。除去処理工程をエッチング処理によって行う場合には、第１の絶縁膜４に対するダメージが少ないという利点がある。また、除去処理工程を研磨処理によって行う場合には、第１の絶縁膜４に対するダメージが多くなるが、突き出た部分２２の除去を迅速に行うことができる。   Next, as shown in FIG. 4, a removal process step is performed that can remove the portion 22 of the probing mark 21 protruding above the first insulating film 4. As the removal processing step, a step of removing the protruding portion 22 by etching or a step of mechanically polishing and removing the protruding portion 22 by the polishing apparatus 102 can be employed. When the removal process step is performed by an etching process, there is an advantage that damage to the first insulating film 4 is small. Further, when the removal process step is performed by a polishing process, damage to the first insulating film 4 increases, but the protruding portion 22 can be quickly removed.

次に、図５に示されるように、第１の絶縁膜４と除去処理工程を受けた後の電極パッド２のプロービング痕２１の存在する部分の上面に、第２の絶縁膜５を形成する。第２の絶縁膜５の材料としては、例えば、ポリイミドなどを用いることができる。また、第２の絶縁膜５の材料として、ＰＢＯなどの他の絶縁材料を用いることもできる。第２の絶縁膜５は、第１の絶縁膜４と同じ材料で形成することができる。第１及び第２の絶縁膜３，４が熱硬化性樹脂である場合には、この段階でキュア炉にてキュア処理を行う。第１及び第２の絶縁膜３，４の設定膜厚は、キュア処理後の値になるように調整する。また、第２の絶縁層６の上に、１又は複数層の他の絶縁層を形成することもできる。   Next, as shown in FIG. 5, the second insulating film 5 is formed on the upper surface of the portion of the electrode pad 2 where the probing marks 21 are present after undergoing the first insulating film 4 and the removal treatment step. . As a material of the second insulating film 5, for example, polyimide can be used. Further, as the material of the second insulating film 5, other insulating materials such as PBO can be used. The second insulating film 5 can be formed of the same material as the first insulating film 4. When the first and second insulating films 3 and 4 are thermosetting resins, a curing process is performed in a curing furnace at this stage. The set film thickness of the first and second insulating films 3 and 4 is adjusted so as to have a value after the curing process. One or more other insulating layers may be formed on the second insulating layer 6.

次に、図６に示されるように、第２の絶縁膜形成工程の後に、第２の絶縁膜５及び第１の絶縁膜４を貫通し、電極パッド２の上面に達する開口５１を形成する。開口５１は、例えば、フォトリソグラフィ技術を用いて形成することができる。次に、開口５１を介して電極パッド２に電気的に接続する再配線層（再配線パターン）６を形成する。再配線層６は、例えば、Ｃｕ又はＣｕを主成分とする合金などから、例えば、メッキ法などにより構成することができる。なお、開口５１の形成を、図４に示される突き出た部分２３の除去処理工程の後に第１の絶縁膜４に第１の開口を設ける工程と、図５に示される第２の絶縁膜５の形成後に第２の絶縁膜５に第１の開口に繋がる第２の開口を形成する２工程とによって、行ってもよい。図６に示されるように、開口５１の形成を１工程で行う場合には、製造工程の数を減らすことができ、また、開口の形成を複数工程で行う場合に生じることがある、位置ズレの可能性が無くなるという利点がある。   Next, as shown in FIG. 6, after the second insulating film formation step, an opening 51 that penetrates the second insulating film 5 and the first insulating film 4 and reaches the upper surface of the electrode pad 2 is formed. . The opening 51 can be formed using, for example, a photolithography technique. Next, a rewiring layer (rewiring pattern) 6 that is electrically connected to the electrode pad 2 through the opening 51 is formed. The rewiring layer 6 can be made of, for example, Cu or an alloy containing Cu as a main component by, for example, a plating method. In addition, the formation of the opening 51 includes the step of providing the first opening in the first insulating film 4 after the removal processing step of the protruding portion 23 shown in FIG. 4, and the second insulating film 5 shown in FIG. This may be performed by two steps of forming a second opening connected to the first opening in the second insulating film 5 after the formation. As shown in FIG. 6, when the formation of the opening 51 is performed in one process, the number of manufacturing processes can be reduced, and the positional deviation that may occur when the formation of the opening is performed in a plurality of processes. There is an advantage that the possibility of.

次に、図７に示されるように、再配線層６を、一部（符号７１）を露出するように、覆う封止層としてのモールド樹脂層７を形成し、再配線層６に電気的に接続された柱状電極８と、この柱状電極８上に形成された外部接続電極としての半田ボール９とを形成する。   Next, as shown in FIG. 7, a mold resin layer 7 is formed as a sealing layer to cover the rewiring layer 6 so that a part (reference numeral 71) of the rewiring layer 6 is exposed. A columnar electrode 8 connected to the electrode and a solder ball 9 as an external connection electrode formed on the columnar electrode 8 are formed.

以上に説明した本実施の形態に係る半導体装置の製造方法及び半導体装置によれば、第１の絶縁膜４の形成後に、プロービング痕２１の突起した部分２２を除去するので、基板１内の集積回路（下地デバイス）にダメージを与えることなく、ＷＬ−ＣＳＰ加工を行うことができる。このため、本実施の形態に係る半導体装置の製造方法及び半導体装置によれば、電極パッド２のプロ−ビング痕２１に起因する不良品の発生率を低下させることができる。   According to the manufacturing method and semiconductor device of the semiconductor device according to the present embodiment described above, the protruding portion 22 of the probing mark 21 is removed after the first insulating film 4 is formed. WL-CSP processing can be performed without damaging the circuit (underlying device). For this reason, according to the semiconductor device manufacturing method and the semiconductor device according to the present embodiment, it is possible to reduce the incidence of defective products due to the probing marks 21 of the electrode pads 2.

また、本実施の形態に係る半導体装置の製造方法及び半導体装置によれば、絶縁膜を２層形成しており、第２の絶縁膜５上に突起した部分が無く、２層の絶縁膜４，５の同じ位置に重なってピンホールが発生する可能性は低いため、絶縁膜８，９の全体を貫通するピンホールの発生は極めて少ないという利点がある。   In addition, according to the method of manufacturing a semiconductor device and the semiconductor device according to the present embodiment, two layers of insulating films are formed, and there are no protruding portions on the second insulating film 5. , 5 is less likely to generate pinholes at the same position, and therefore, there is an advantage that the generation of pinholes penetrating the entire insulating films 8 and 9 is extremely small.

なお、上記説明では、突起した部分（突出部）２２がプロ−ビング痕である場合を説明したが、本発明は、突起した部分（突出部）２２がプロ−ビング以外の原因によって発生した場合にも適用可能である。   In the above description, the case where the protruding portion (projecting portion) 22 is a probing mark has been described. However, in the present invention, the protruding portion (projecting portion) 22 is caused by a cause other than probing. It is also applicable to.

図８は、第１比較例の半導体装置の製造方法の一工程を概略的に示す縦断面図である。図８において、図６（実施の形態）の半導体装置の構成と同一又は対応する部分には、同じ符号を付す。第１比較例は、プロービング痕２１の突起した部分の除去処理工程を行わないときに、再配線層２０６を断線させた状況を示している。既に説明したように、本実施の形態に係る半導体装置の製造方法及び半導体装置によれば、プロービング痕２１の第１の絶縁膜４よりも突き出た部分２２を除去しているので、図８のプロービング痕２１によって、再配線層６が断線することは無い。   FIG. 8 is a longitudinal sectional view schematically showing one step of the method for manufacturing the semiconductor device of the first comparative example. In FIG. 8, parts that are the same as or correspond to those in the configuration of the semiconductor device in FIG. The first comparative example shows a situation where the rewiring layer 206 is disconnected when the removal processing step of the protruding portion of the probing mark 21 is not performed. As already described, according to the method of manufacturing a semiconductor device and the semiconductor device according to the present embodiment, the portion 22 protruding from the first insulating film 4 of the probing mark 21 is removed. The rewiring layer 6 is not disconnected by the probing mark 21.

図９は、第２比較例の半導体装置の製造方法の一工程を概略的に示す縦断面図である。図９において、図６（実施の形態）の半導体装置の構成と同一又は対応する部分には、同じ符号を付す。第２比較例は、プロービング痕２１の突起した部分の全体を膜厚Ｂの厚い絶縁層３０４で覆い、その上に再配線層３０６を形成する場合を示している。しかし、この場合には、絶縁膜３０４の厚膜化によって基板１としての半導体ウェハに生じる応力が増大するため、半導体ウェハに反りやクラックが発生し易くなるという問題がある。本実施の形態に係る半導体装置の製造方法及び半導体装置によれば、プロービング痕２１の第１の絶縁膜４よりも突き出た部分２２を除去しているので、第１の絶縁膜４と第２の絶縁膜５との合計の厚さ（図７の膜厚Ａ）を薄くすることができるので、半導体ウェハに反りやクラックが発生し難い。   FIG. 9 is a longitudinal sectional view schematically showing one step of the method for manufacturing the semiconductor device of the second comparative example. 9, parts that are the same as or correspond to those in the semiconductor device in FIG. 6 (the embodiment) are denoted by the same reference numerals. The second comparative example shows a case where the entire protruding portion of the probing mark 21 is covered with a thick insulating layer 304 and a rewiring layer 306 is formed thereon. However, in this case, since the stress generated in the semiconductor wafer as the substrate 1 is increased by increasing the thickness of the insulating film 304, there is a problem that warpage and cracks are likely to occur in the semiconductor wafer. According to the method for manufacturing a semiconductor device and the semiconductor device according to the present embodiment, the portion 22 protruding from the first insulating film 4 of the probing mark 21 is removed, so the first insulating film 4 and the second insulating film 4 are removed. Since the total thickness with the insulating film 5 (film thickness A in FIG. 7) can be reduced, warpage and cracks are unlikely to occur in the semiconductor wafer.

図１０は、第３比較例の半導体装置の製造方法の一工程を概略的に示す縦断面図である。図１０において、図６（実施の形態）の半導体装置の構成と同一又は対応する部分には、同じ符号を付す。第３比較例は、電極パッド２のプロ−ビング痕２１の突起した部分を絶縁層４０４の開口４０５内に置き、突起した部分を再配線層４０６で覆うことによって、突起した部分が封止樹脂に接しないようにする方法を提案している。しかし、半導体ウェハ上に多数配置された電極パッド２の各プロービング痕の突起した部分の位置は一定でないため、これらを再配線パターンで確実に覆うことは、困難である。本実施の形態に係る半導体装置の製造方法及び半導体装置によれば、プロービング痕２１の第１の絶縁膜４よりも突き出た部分２２を除去しているので、プロ−ビング痕２１の突起した部分を絶縁層４０４の開口４０５内に置き、突起した部分を再配線層４０６で覆うという困難な処理工程を必要としていないので、製造プロセスが複雑にならない利点がある。   FIG. 10 is a longitudinal sectional view schematically showing one step of the method for manufacturing the semiconductor device of the third comparative example. 10, parts that are the same as or correspond to those in the semiconductor device in FIG. 6 (embodiment) are denoted by the same reference numerals. In the third comparative example, the protruding portion of the probing mark 21 of the electrode pad 2 is placed in the opening 405 of the insulating layer 404, and the protruding portion is covered with the rewiring layer 406. Proposes a way to avoid contact. However, since the positions of the protruding portions of the probing marks of the electrode pads 2 arranged in large numbers on the semiconductor wafer are not constant, it is difficult to reliably cover them with the rewiring pattern. According to the method of manufacturing a semiconductor device and the semiconductor device according to the present embodiment, since the portion 22 protruding from the first insulating film 4 of the probing mark 21 is removed, the protruding portion of the probing mark 21 is removed. This is advantageous in that the manufacturing process is not complicated because a difficult processing step is not required to place the protruding portion in the opening 405 of the insulating layer 404 and cover the protruding portion with the rewiring layer 406.

１ 半導体ウェハ、 ２ 電極パッド、 ３ パッシベーション膜（ＰＶ膜）、 ４ 第１の絶縁膜、 ５ 第２の絶縁膜、 ６ 再配線層（再配線パターン）、 ７ モールド樹脂（封止層）、 ８ 柱状電極、 ９ 半田ボール、 ２１ プロ−ビング痕（プローブ痕）、 ２２ 突起した部分、 ２３ 第１の絶縁膜よりも上に突き出た部分、 ７１ 開口、 １０１ プロービング針（プローブピン）。   DESCRIPTION OF SYMBOLS 1 Semiconductor wafer, 2 Electrode pad, 3 Passivation film (PV film), 4 1st insulating film, 5 2nd insulating film, 6 Rewiring layer (rewiring pattern), 7 Mold resin (sealing layer), 8 Columnar electrode, 9 solder ball, 21 probing mark (probe mark), 22 protruding part, 23 part protruding above the first insulating film, 71 opening, 101 probing needle (probe pin).

Claims (13)

表面に突出部を有する電極パッドを備える基板上に、前記突出部の上部を露出させると共に前記突出部の下部を覆うように前記電極パッドを覆う第１の絶縁膜を形成する第１の絶縁膜形成工程と、
前記第１の絶縁膜の表面から突起した前記突出部の前記上部を除去する除去処理工程と、
前記除去処理工程後に、前記第１の絶縁膜上及び前記突出部の前記下部の頂部上に第２の絶縁膜を形成する第２の絶縁膜形成工程と
を有することを特徴とする半導体装置の製造方法。 On a substrate having an electrode pad having protrusions on the surface, a first insulation forming a first insulating film covering the electrode pad so as to cover the lower portion of the protruding portion to expose the upper portion of the projecting portion A film forming step;
And removing process remove the upper portion of the protruding portion that protrudes from the surface of the first insulating film,
And a second insulating film forming step of forming a second insulating film on the first insulating film and on the top of the lower portion of the protruding portion after the removing process. Production method. 前記電極パッドの前記突出部は、プロービング痕であることを特徴とする請求項１に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the protruding portion of the electrode pad is a probing mark. 前記第１の絶縁膜形成工程前に、前記電極パッドにプロービング針を接触させ、その後、前記電極パッドから前記プロービング針を離す動作を含む検査工程をさらに有することを特徴とする請求項１又は２に記載の半導体装置の製造方法。   3. The method according to claim 1, further comprising an inspection step including an operation of bringing a probing needle into contact with the electrode pad before the first insulating film forming step and then separating the probing needle from the electrode pad. The manufacturing method of the semiconductor device as described in any one of. 前記除去処理工程は、前記突出部の前記上部をエッチングにより除去する工程を含む
ことを特徴とする請求項１から３までのいずれか１項に記載の半導体装置の製造方法。 Pre Symbol removing treatment step, a method of manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that it comprises a step of removing the upper portion of the protruding portion by etching. 前記除去処理工程は、前記突出部の前記上部を研磨により除去する工程を含む
ことを特徴とする請求項１から３までのいずれか１項に記載の半導体装置の製造方法。 Pre Symbol removing treatment step, a method of manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that it comprises a step of removing by polishing the upper portion of the protrusion. 前記第２の絶縁膜形成工程後に、前記第１の絶縁膜及び前記第２の絶縁膜を貫通し、前記電極パッドの一部を露出する開口部を形成する工程と、
前記開口部を介して前記電極パッドに電気的に接続する再配線層を形成する工程と
をさらに有することを特徴とする請求項１から５までのいずれか１項に記載の半導体装置の製造方法。 After the second insulating film formation step, said step of first insulating films and to penetrate the second insulating film to form an opening exposing a portion of the electrode pad,
The method of manufacturing a semiconductor device according to any one of claims 1 to 5, characterized by further comprising the step of forming the rewiring layer electrically connected to the electrode pad through the opening . 前記第１の絶縁膜形成工程と前記第２の絶縁膜形成工程との間において、前記第１の絶縁膜を貫通し、前記電極パッドの一部を露出する第１の開口部を形成する工程と、
前記第２の絶縁膜形成工程後に、前記第２の絶縁膜を貫通し、前記第１の開口部に繋がる第２の開口部を形成する工程と、
前記第２の開口部及び前記第１の開口部を介して前記電極パッドに電気的に接続する再配線層を形成する工程と
をさらに有することを特徴とする請求項１から５までのいずれか１項に記載の半導体装置の製造方法。 In between the first insulating film forming step and the second insulating film formation step, through said first insulating film, forming a first opening exposing a portion of the electrode pad When,
After the second insulating film formation step, a step of penetrating the second insulating film, forming a second opening leading to the first opening,
Either to claims 1 to 5 further comprising the step of forming the rewiring layer electrically connected to the electrode pad through the second opening and the first opening 2. A method for manufacturing a semiconductor device according to item 1. 前記再配線層を覆う封止層を形成する工程と、
前記再配線層に電気的に接続され、前記封止層上に備えられた電極部を形成する工程と
をさらに有することを特徴とする請求項６又は７に記載の半導体装置の製造方法。 Forming a sealing layer covering the rewiring layer;
The method of manufacturing a semiconductor device according to claim 6, further comprising: forming an electrode portion electrically connected to the redistribution layer and provided on the sealing layer. 基板と、
前記基板上に備えられ、表面に突出部を有する電極パッドと、
前記基板上に、前記突出部の頂部を露出させると共に前記突出部の側面を被覆するように前記電極パッドの表面を被覆する第１の絶縁膜と、
前記第１の絶縁膜と前記突出部の頂部とを被覆する第２の絶縁膜と
を有することを特徴とする半導体装置。 A substrate,
An electrode pad provided on the substrate and having a protrusion on the surface;
On the substrate, a first insulating film that covers a surface of the electrode pad so as to expose a top portion of the protrusion and to cover a side surface of the protrusion ,
Before Symbol wherein a and a second insulating film covering a top portion of the projecting portion and the first insulating film. 前記電極パッドの前記突出部は、プロービング痕であることを特徴とする請求項９に記載の半導体装置。   The semiconductor device according to claim 9, wherein the protruding portion of the electrode pad is a probing mark. 前記電極パッドの前記突出部は、前記第１の絶縁膜の表面より高い部分を持たない
ことを特徴とする請求項９又は１０に記載の半導体装置。 The projecting portion of the electrode pads, the semiconductor device according to claim 9 or 10, characterized in that no higher than said surface portion of the first insulating film. 前記第１の絶縁膜及び前記第２の絶縁膜を貫通し、前記電極パッドに達する開口部と、
前記開口部を介して前記電極パッドに電気的に接続する再配線層と
をさらに有することを特徴とする請求項９から１１までのいずれか１項に記載の半導体装置。 Through the first insulating film and said second insulating film, an opening reaching the electrode pad,
The semiconductor device according to any one of up to 11 from claim 9, further comprising a rewiring layer to be electrically connected to the electrode pad through the opening. 前記再配線層を覆う封止層と、
前記再配線層に電気的に接続され、前記封止層上に備えられた電極部と
をさらに有することを特徴とする請求項１２に記載の半導体装置。 A sealing layer covering the rewiring layer;
The semiconductor device according to claim 12 , further comprising: an electrode part electrically connected to the redistribution layer and provided on the sealing layer.
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