JP5827277B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- JP5827277B2 JP5827277B2 JP2013160954A JP2013160954A JP5827277B2 JP 5827277 B2 JP5827277 B2 JP 5827277B2 JP 2013160954 A JP2013160954 A JP 2013160954A JP 2013160954 A JP2013160954 A JP 2013160954A JP 5827277 B2 JP5827277 B2 JP 5827277B2
- Authority
- JP
- Japan
- Prior art keywords
- copper
- electrode
- grinding
- silicon
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 54
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000010949 copper Substances 0.000 claims description 111
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 104
- 229910052802 copper Inorganic materials 0.000 claims description 104
- 239000000758 substrate Substances 0.000 claims description 88
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 80
- 229910052710 silicon Inorganic materials 0.000 claims description 80
- 239000010703 silicon Substances 0.000 claims description 80
- 238000000227 grinding Methods 0.000 claims description 78
- 238000000034 method Methods 0.000 claims description 43
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 17
- 238000005498 polishing Methods 0.000 claims description 17
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 17
- 238000004140 cleaning Methods 0.000 claims description 14
- 229910052759 nickel Inorganic materials 0.000 claims description 14
- 238000007772 electroless plating Methods 0.000 claims description 13
- 239000000853 adhesive Substances 0.000 claims description 10
- 230000001070 adhesive effect Effects 0.000 claims description 10
- 239000000126 substance Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- 239000003513 alkali Substances 0.000 claims description 7
- 229910018594 Si-Cu Inorganic materials 0.000 claims description 6
- 229910008465 Si—Cu Inorganic materials 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 230000035515 penetration Effects 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005553 drilling Methods 0.000 claims description 4
- 238000005406 washing Methods 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 28
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 10
- 239000004020 conductor Substances 0.000 description 9
- 239000007788 liquid Substances 0.000 description 9
- 239000007864 aqueous solution Substances 0.000 description 7
- 238000011109 contamination Methods 0.000 description 7
- 238000007789 sealing Methods 0.000 description 7
- 239000006185 dispersion Substances 0.000 description 6
- 239000012530 fluid Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 239000000203 mixture Substances 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 239000012790 adhesive layer Substances 0.000 description 5
- 150000007514 bases Chemical class 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 235000011118 potassium hydroxide Nutrition 0.000 description 5
- HZAXFHJVJLSVMW-UHFFFAOYSA-N 2-Aminoethan-1-ol Chemical compound NCCO HZAXFHJVJLSVMW-UHFFFAOYSA-N 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 4
- 239000008119 colloidal silica Substances 0.000 description 4
- VDZOOKBUILJEDG-UHFFFAOYSA-M tetrabutylammonium hydroxide Chemical compound [OH-].CCCC[N+](CCCC)(CCCC)CCCC VDZOOKBUILJEDG-UHFFFAOYSA-M 0.000 description 4
- 238000002042 time-of-flight secondary ion mass spectrometry Methods 0.000 description 4
- 239000002699 waste material Substances 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- WMFOQBRAJBCJND-UHFFFAOYSA-M Lithium hydroxide Chemical compound [Li+].[OH-] WMFOQBRAJBCJND-UHFFFAOYSA-M 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000010432 diamond Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- NDKBVBUGCNGSJJ-UHFFFAOYSA-M benzyltrimethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)CC1=CC=CC=C1 NDKBVBUGCNGSJJ-UHFFFAOYSA-M 0.000 description 2
- 229910001431 copper ion Inorganic materials 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229940031098 ethanolamine Drugs 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229940073455 tetraethylammonium hydroxide Drugs 0.000 description 2
- LRGJRHZIDJQFCL-UHFFFAOYSA-M tetraethylazanium;hydroxide Chemical compound [OH-].CC[N+](CC)(CC)CC LRGJRHZIDJQFCL-UHFFFAOYSA-M 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- JWZZKOKVBUJMES-UHFFFAOYSA-N (+-)-Isoprenaline Chemical compound CC(C)NCC(O)C1=CC=C(O)C(O)=C1 JWZZKOKVBUJMES-UHFFFAOYSA-N 0.000 description 1
- VILCJCGEZXAXTO-UHFFFAOYSA-N 2,2,2-tetramine Chemical compound NCCNCCNCCN VILCJCGEZXAXTO-UHFFFAOYSA-N 0.000 description 1
- XHJGXOOOMKCJPP-UHFFFAOYSA-N 2-[tert-butyl(2-hydroxyethyl)amino]ethanol Chemical compound OCCN(C(C)(C)C)CCO XHJGXOOOMKCJPP-UHFFFAOYSA-N 0.000 description 1
- KIZQNNOULOCVDM-UHFFFAOYSA-M 2-hydroxyethyl(trimethyl)azanium;hydroxide Chemical compound [OH-].C[N+](C)(C)CCO KIZQNNOULOCVDM-UHFFFAOYSA-M 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910017758 Cu-Si Inorganic materials 0.000 description 1
- 229910017931 Cu—Si Inorganic materials 0.000 description 1
- RPNUMPOLZDHAAY-UHFFFAOYSA-N Diethylenetriamine Chemical compound NCCNCCN RPNUMPOLZDHAAY-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- GSEJCLTVZPLZKY-UHFFFAOYSA-N Triethanolamine Chemical compound OCCN(CCO)CCO GSEJCLTVZPLZKY-UHFFFAOYSA-N 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229960001231 choline Drugs 0.000 description 1
- OEYIOHPDSNJKLS-UHFFFAOYSA-N choline Chemical compound C[N+](C)(C)CCO OEYIOHPDSNJKLS-UHFFFAOYSA-N 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- ZBCBWPMODOFKDW-UHFFFAOYSA-N diethanolamine Chemical compound OCCNCCO ZBCBWPMODOFKDW-UHFFFAOYSA-N 0.000 description 1
- YPTUAQWMBNZZRN-UHFFFAOYSA-N dimethylaminoboron Chemical compound [B]N(C)C YPTUAQWMBNZZRN-UHFFFAOYSA-N 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000010985 leather Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- LGQLOGILCSXPEA-UHFFFAOYSA-L nickel sulfate Chemical compound [Ni+2].[O-]S([O-])(=O)=O LGQLOGILCSXPEA-UHFFFAOYSA-L 0.000 description 1
- 229910000363 nickel(II) sulfate Inorganic materials 0.000 description 1
- 238000000879 optical micrograph Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000001509 sodium citrate Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- VHLDQAOFSQCOFS-UHFFFAOYSA-M tetrakis(2-hydroxyethyl)azanium;hydroxide Chemical compound [OH-].OCC[N+](CCO)(CCO)CCO VHLDQAOFSQCOFS-UHFFFAOYSA-M 0.000 description 1
- QEMXHQIAXOOASZ-UHFFFAOYSA-N tetramethylammonium Chemical compound C[N+](C)(C)C QEMXHQIAXOOASZ-UHFFFAOYSA-N 0.000 description 1
- LPSKDVINWQNWFE-UHFFFAOYSA-M tetrapropylazanium;hydroxide Chemical compound [OH-].CCC[N+](CCC)(CCC)CCC LPSKDVINWQNWFE-UHFFFAOYSA-M 0.000 description 1
- 229960001124 trientine Drugs 0.000 description 1
- BJAARRARQJZURR-UHFFFAOYSA-N trimethylazanium;hydroxide Chemical compound O.CN(C)C BJAARRARQJZURR-UHFFFAOYSA-N 0.000 description 1
- IJGSGCGKAAXRSC-UHFFFAOYSA-M tris(2-hydroxyethyl)-methylazanium;hydroxide Chemical compound [OH-].OCC[N+](C)(CCO)CCO IJGSGCGKAAXRSC-UHFFFAOYSA-M 0.000 description 1
- HRXKRNGNAMMEHJ-UHFFFAOYSA-K trisodium citrate Chemical compound [Na+].[Na+].[Na+].[O-]C(=O)CC(O)(CC([O-])=O)C([O-])=O HRXKRNGNAMMEHJ-UHFFFAOYSA-K 0.000 description 1
- 229940038773 trisodium citrate Drugs 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000004065 wastewater treatment Methods 0.000 description 1
Description
本発明は、トランジスター、キャパシタ、メモリーカード、センサー、撮像素子、等として携帯電話、デジタルカメラ、ビデオカメラ、カーナビゲーション、パーソナルコンピュータ、ゲーム機、液晶テレビ、プリンター等に使用される半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device used in a mobile phone, digital camera, video camera, car navigation, personal computer, game machine, liquid crystal television, printer, etc. as a transistor, capacitor, memory card, sensor, imaging device, etc. About.
貫通電極を備える半導体装置の製造が実施されている。たとえば、特開２０１２−１２９２６０号公報（特許文献１）は、ダミー基板上に樹脂接着層を設け、この樹脂接着層上に少なくとも１つの電極パッドを有する複数の半導体素子と導電性を有する複数の導体柱を配置し、前記半導体素子と前記導体柱とが配置されている側の面に前記ダミー基板と前記半導体素子と前記導体柱とを覆うように封止して封止部を形成した後、前記導体柱の前記ダミー基板と反対側の端部が露出するまで、前記封止部の前記ダミー基板と反対側の面を研削および／または研磨加工し、次いで、前記半導体素子封止体から前記ダミー基板を剥離させて半導体素子封止体を製造する方法を開示する。また、厚さ方向に複数の貫通孔がエッチング法により形成されたシート材を用意し、各貫通孔に電極パッドおよび導体柱が対応するように、半導体素子封止体にシート材を貼り合わせるシート材貼り合わせ工程と、貫通孔に導電性を有する導体ポストを形成する導体ポスト（貫通電極）形成工程と、シート材の前記半導体素子封止体とは反対の面側に、導体ポストに電気的に接続する銅メッキ配線を形成する配線形成工程と、半導体素子封止体とは反対側の面に、配線の一部が露出するように、開口部を備える被覆部を形成する被覆部形成工程と、開口部で露出する前記銅メッキ配線に、バンプを電気的に接続するバンプ接続工程と、半導体素子毎に対応するように、半導体素子封止体を個片化することにより、複数の半導体パッケージを一括して得る個片化工程とを有する半導体パッケージの製造方法も提案する。 Manufacture of semiconductor devices provided with through electrodes has been carried out. For example, Japanese Patent Laid-Open No. 2012-129260 (Patent Document 1) provides a resin adhesive layer on a dummy substrate and a plurality of semiconductor elements having at least one electrode pad on the resin adhesive layer and a plurality of conductive elements. After disposing a conductor column and forming a sealing portion on the surface on which the semiconductor element and the conductor column are disposed so as to cover the dummy substrate, the semiconductor element, and the conductor column Then, grinding and / or polishing the surface of the sealing portion opposite to the dummy substrate until the end of the conductor column opposite to the dummy substrate is exposed, and then from the semiconductor element sealing body Disclosed is a method for manufacturing a semiconductor element encapsulant by peeling off the dummy substrate. Also, a sheet material in which a plurality of through holes are formed by an etching method in the thickness direction is prepared, and the sheet material is bonded to the semiconductor element sealing body so that the electrode pads and the conductor columns correspond to the respective through holes. The material post step, the conductor post (through electrode) forming step for forming a conductive post having conductivity in the through hole, and the surface of the sheet material opposite to the semiconductor element sealing body are electrically connected to the conductor post. Forming a copper-plated wiring to be connected to the cover, and forming a covering portion having an opening so that a part of the wiring is exposed on the surface opposite to the semiconductor element sealing body And a bump connection step for electrically connecting bumps to the copper-plated wiring exposed at the openings, and by separating the semiconductor element sealing body so as to correspond to each semiconductor element, a plurality of semiconductors One package Also we propose a method of manufacturing a semiconductor package having a obtained by singulation process.
また、特開２００５−１３６１８７号公報（特許文献２）は、半導体基板の一面に所定回路を複数整列配置形成し、回路に電気的に繋がる配線及び絶縁層を順次所定パターンに積層形成して多層配線部を形成し、多層配線部を形成する段階で半導体基板に表面が絶縁膜で覆われる充填電極を形成し、多層配線部の所定の配線上に銅メッキポスト電極を形成し、半導体基板の一面に第１の絶縁層を形成し、第１の絶縁層（ポリイミド、エポキシ樹脂等の絶縁樹脂層）の表面を所定厚さ除去してポスト電極を露出させ、半導体基板の他の一面を研削して充填電極を露出させて銅メッキ貫通電極を形成し、半導体基板の一面をエッチングして貫通電極を先端を突出させ、貫通電極の先端を露出させる状態で半導体基板の一面に第２の絶縁層を形成し、両電極に突起電極を形成し、半導体基板を分割して半導体装置を形成する。この方法で得た複数の半導体装置を突起電極で積層固定して積層型（３Ｄ）半導体装置を製造する方法を開示する。 Japanese Patent Laying-Open No. 2005-136187 (Patent Document 2) discloses a multilayer in which a plurality of predetermined circuits are arranged and arranged on one surface of a semiconductor substrate, and wirings and insulating layers electrically connected to the circuits are sequentially stacked in a predetermined pattern. In the step of forming the wiring part, the filling electrode whose surface is covered with an insulating film is formed on the semiconductor substrate at the stage of forming the multilayer wiring part, the copper plating post electrode is formed on the predetermined wiring of the multilayer wiring part, and the semiconductor substrate A first insulating layer is formed on one surface, the surface of the first insulating layer (insulating resin layer such as polyimide or epoxy resin) is removed to a predetermined thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground. Then, a copper-plated through electrode is formed by exposing the filling electrode, and etching is performed on one surface of the semiconductor substrate so that the tip of the through electrode protrudes, and the second insulation is formed on the one surface of the semiconductor substrate with the tip of the through electrode exposed. Forming a layer The protruding electrodes formed on both electrodes, to form a semiconductor device by dividing a semiconductor substrate. A method of manufacturing a stacked type (3D) semiconductor device by laminating and fixing a plurality of semiconductor devices obtained by this method with protruding electrodes is disclosed.
また、特開２０１１−１５１１３８号公報（特許文献３）は、半導体基板上に形成された絶縁膜層（シリコン酸化膜、シリコン窒化膜、ポリシリコン膜など）に、その表面が露出するように銅パッド電極を形成する工程と、前記銅パッド電極にタンタル系バリア層を介して接触させて前記絶縁膜層上に導電性の接着剤層を形成する工程と、前記絶縁膜層と前記パッド電極が形成された側の面である第１面に、前記接着剤層を介して導電性の支持板を接合する工程と、前記第１面とは反対側の第２面から前記半導体基板を研磨して所定の厚さに薄化する工程と、前記第２面側から前記薄化した半導体基板および前記絶縁膜層を順次選択的にエッチングし、前記パッド電極に達する開孔を形成する工程と、前記支持板および前記接着剤層を介して前記パッド電極に所定の電位を与え、前記半導体基板の前記第２面側の表面上、および前記開孔の側壁に絶縁膜を形成する工程と、メッキ法により
前記開孔内に導電性材料を成長させて埋め込むことによって、少なくとも前記開孔の上端から前記パッド電極に達する貫通電極を形成する工程を含む半導体装置の製造方法を提案する。
Japanese Patent Laying-Open No. 2011-151138 (Patent Document 3) discloses copper so that the surface is exposed to an insulating film layer (silicon oxide film, silicon nitride film, polysilicon film, etc.) formed on a semiconductor substrate. A step of forming a pad electrode, a step of contacting the copper pad electrode with a tantalum-based barrier layer to form a conductive adhesive layer on the insulating film layer, and the insulating film layer and the pad electrode. A step of bonding a conductive support plate to the first surface, which is a surface on the formed side, via the adhesive layer; and polishing the semiconductor substrate from a second surface opposite to the first surface. A step of thinning to a predetermined thickness, a step of selectively etching the thinned semiconductor substrate and the insulating film layer sequentially from the second surface side, and forming an opening reaching the pad electrode; Through the support plate and the adhesive layer A step of applying a predetermined potential to the pad electrode to form an insulating film on the surface of the semiconductor substrate on the second surface side and on the side wall of the opening; and a conductive material in the opening by plating. Proposed is a method for manufacturing a semiconductor device including a step of forming a through electrode reaching at least the pad electrode from the upper end of the opening by being grown and buried.
さらに、特開２０１０−９８３１８号公報（特許文献４）は、シリコン基板と、前記シリコン基板上に提供され、貫通して延長される第１及び第２開口を含む導電性パッドと、前記導電性パッド上に提供され、前記導電性パッド内の前記第１開口を貫通して前記基板内に延長される第１導電性ビア電極と、前記導電性パッド上に前記第１導電性ビア電極に隣接するように提供され、前記導電性パッド内の前記第２開口を貫通して前記基板内に延長される第２導電性ビア電極を有するマイクロ電子構造体を提案する。なお、上記導電層は、タンタル、チタン、窒化タンタル、窒化チタンから選ばれたバリアメタルおよび／または、銅、アルミニウム、タングステンより選ばれた配線金属を含んでもよい。また、シリコン配線基板の除去は、エッチング、化学機械研磨加工（ＣＭＰ）のいずれか又は両方の手段により行われることも記載されている。 Further, Japanese Patent Laid-Open No. 2010-98318 (Patent Document 4) discloses a silicon substrate, a conductive pad provided on the silicon substrate and including first and second openings extending therethrough, and the conductive material. A first conductive via electrode provided on the pad and extending through the first opening in the conductive pad and into the substrate; and adjacent to the first conductive via electrode on the conductive pad And providing a microelectronic structure having a second conductive via electrode extending through the second opening in the conductive pad and into the substrate. The conductive layer may include a barrier metal selected from tantalum, titanium, tantalum nitride, and titanium nitride and / or a wiring metal selected from copper, aluminum, and tungsten. It is also described that the removal of the silicon wiring substrate is performed by either or both of etching and chemical mechanical polishing (CMP).
現在のシリコン基板に内蔵された銅電極柱のシリコン表面からの頭出し方法は、次の工程を経由することが世界的標準となっている。
（１）．銅電極が露出しない程度（シリコン表面の銅汚染を防ぐため）までシリコン基板面を研削加工し、基板を薄化する。
（２）．ドライエッチングでシリコンのみをエッチングし、絶縁膜（酸化物）で被覆された銅電極を頭出しする。
（３）．頭出しされた銅電極頭を絶縁酸化膜、窒化珪素等の絶縁層で被覆する。
（４）．化学機械研磨加工（ＣＭＰ）により頭出しされた銅電極頭の上記絶縁層を除去し、銅電極をシリコン表面から頭出しする工程を終了する。
The cueing method from the silicon surface of the copper electrode pillar built in the current silicon substrate is to pass through the following steps as a global standard.
(1). The silicon substrate surface is ground until the copper electrode is not exposed (to prevent copper contamination of the silicon surface), and the substrate is thinned.
(2). Only silicon is etched by dry etching, and a copper electrode covered with an insulating film (oxide) is cued.
(3). The capped copper electrode head is covered with an insulating layer such as an insulating oxide film or silicon nitride.
(4). The insulating layer of the copper electrode head cueed by chemical mechanical polishing (CMP) is removed, and the step of cueing the copper electrode from the silicon surface is completed.
上記世界的標準銅電極柱頭出し方法は、多数の銅電極柱の径、面分布が均一な銅貫通電極柱の頭出しには適している。しかし、多数の銅電極柱の径が異なり、また、面分布が不均一な銅貫通電極シリコン基板の頭出しを行う場合には、上記第２工程のドライエッチングにおいてシリコン表面と頭出しされた貫通電極柱頂上の高さの差（ドライエッチング量）が貫通電極柱の分散位置によって大きく異なり、上記第４工程の実施により道電極が露出する場所と露出しない場所が生じ、チップ（半導体装置）合格品の歩留まりを大きく低下させている。また、頭出しの高い銅貫通電極柱の部分においては、ＣＭＰ加工時のせん断応力により倒れたり、破壊されたりする欠点もある。 The above-mentioned global standard copper electrode column cueing method is suitable for cueing a copper through electrode column having a large number of copper electrode columns having a uniform diameter and surface distribution. However, in the case of cueing a copper substrate having a large number of copper electrode pillars having different diameters and a non-uniform surface distribution, the silicon surface is penetrated from the silicon surface in the dry etching of the second step. The difference in height (dry etching amount) on the top of the electrode column varies greatly depending on the dispersion position of the through electrode column, and the place where the road electrode is exposed and the place where the road electrode is not exposed are generated by performing the above fourth step, and the chip (semiconductor device) passes. The yield of goods is greatly reduced. In addition, the copper penetrating electrode column portion having a high cue also has a drawback that it collapses or is destroyed due to the shear stress during CMP processing.
本願発明者らは、現在使用されている平面研削砥石を用いて、銅電極およびシリコンを同時研削加工(Ｃｕ／Ｓｉ)し、Ｃｕ−Ｓｉ段差を５０ｎｍ以下、銅電極の頭出し高さ均一化を行ったところ、図６に示すように複数の貫通電極柱の周辺のシリコン面に銅汚染（銅残渣）を生じることが判明した。 The inventors of the present application use a currently used surface grinding wheel to simultaneously grind a copper electrode and silicon (Cu / Si), to make a Cu-Si step 50 nm or less, and to make the height of the copper electrode uniform. As shown in FIG. 6, it was found that copper contamination (copper residue) occurs on the silicon surface around the plurality of through electrode columns as shown in FIG.
本発明の目的は、銅電極の頭出し高さが均一で、しかも貫通電極柱の周辺のシリコン面での銅汚染が１．０ｘ１０１1ａｔｏｍｓ／ｃｍ２以下である半導体装置のシリコン基板
面からの銅貫通電極の頭出し方法を提供するものである。
It is an object of the present invention to provide a semiconductor device having a uniform cue height of a copper electrode and copper contamination on a silicon surface around a through electrode column of 1.0 × 10 11 atoms / cm 2 or less from a silicon substrate surface of a semiconductor device. A method for cueing a copper through electrode is provided.
請求項１の発明は、次の工程を経て半導体装置のシリコン基板面からの銅貫通電極の頭出しを行う半導体装置の製造方法であって、銅貫通電極の第一次頭出し研削加工を行う下記工程（３）において、研削加工中のカップホイール型砥石の基板の研削加工に供していないカップホイール型砥石の砥石刃先に圧力が３〜２０ＭＰａの洗浄水を噴射する加圧水ドレッシングを行って前記砥石刃先に付着した屑を洗い流すことを特徴とする半導体装置の製造方法を提供するものである。
（１）．半導体回路を形成したシリコン基板の表面側に孔を多数穿孔し、この穿孔内面に絶縁膜とシード層を設け、更にこのシード層内面空間に銅（Ｃｕ）を充填した貫通電極柱を形成する工程。
（２）．接着剤シート材または接着剤を用いて前記銅貫通電極が形成されたシリコン基板の表面を基板チャック上に貼付する工程。
（３）．基板チャック上の前記銅貫通電極が形成されたシリコン基板の裏面をカップホイール型砥石によりシリコン（Ｓｉ）および銅（Ｃｕ）を同時に除く研削加工を行った後、更に、化学機械研磨（ＣＭＰ）加工を行い、５０ｎｍ以下のＳｉ−Ｃｕ段差の平坦化表面を得る銅貫通電極の第一次頭出し研削加工を行う工程。
（４）．前記シリコン基板の露出した銅貫通電極柱頭面にのみ、選択的にニッケル（Ｎｉ）無電解メッキ層（キャップ）を形成させる工程。
（５）．前記ニッケル無電解メッキ層（キャップ）の形成されていないシリコン（Ｓｉ）面を、アルカリエッチングまたは化学的機械研磨（ＣＭＰ）加工して銅貫通電極の第二次頭出し研削加工を行う工程。
（６）．前記銅貫通電極の第二次頭出し研削加工を行ったシリコン基板の表面に絶縁膜を堆積した後に、研磨加工またはエッチング加工により銅貫通電極柱上の前記絶縁膜（ｉｎｓｕｌａｔｏｒ）を除去する工程。
The invention of claim 1 is a method of manufacturing a semiconductor device in which the copper through electrode is cueed from the silicon substrate surface of the semiconductor device through the following steps, and the first cue grinding of the copper through electrode is performed. In the following step (3), the grindstone is subjected to pressurized water dressing in which cleaning water having a pressure of 3 to 20 MPa is sprayed onto a grindstone blade tip of a cupwheel grindstone that has not been subjected to grinding of the substrate of the cupwheel grindstone being ground. The present invention provides a method for manufacturing a semiconductor device, characterized in that wastes adhering to a blade edge are washed away .
(1). A step of drilling a large number of holes on the surface side of a silicon substrate on which a semiconductor circuit is formed, providing an insulating film and a seed layer on the inner surface of the hole, and further forming a through electrode pillar filled with copper (Cu) in the inner space of the seed layer .
(2). The process of sticking the surface of the silicon substrate in which the said copper penetration electrode was formed using an adhesive sheet material or an adhesive on a substrate chuck.
(3). After the back surface of the silicon substrate on which the copper through electrode is formed on the substrate chuck is subjected to grinding processing by simultaneously removing silicon (Si) and copper (Cu) with a cup wheel type grindstone, chemical mechanical polishing (CMP) processing is further performed. And performing a first cue grinding process of the copper through electrode to obtain a flattened surface with a Si-Cu step of 50 nm or less.
(4). A step of selectively forming a nickel (Ni) electroless plating layer (cap) only on the exposed copper penetrating electrode columnar surface of the silicon substrate.
(5). A step of subjecting the silicon (Si) surface on which the nickel electroless plating layer (cap) is not formed to an alkali etching or chemical mechanical polishing (CMP) process to perform a second cueing grinding process of the copper through electrode.
(6). A step of depositing an insulating film on the surface of the silicon substrate subjected to the second cueing grinding of the copper through electrode, and then removing the insulating film (insulator) on the copper through electrode pillar by polishing or etching.
請求項２の発明は、次の工程を経て半導体装置のシリコン基板面からの銅貫通電極の頭出しを行う半導体装置の製造方法であって、銅貫通電極の第一次頭出し研削加工を行う下記工程（３）において、研削加工中のカップホイール型砥石の基板の研削加工に供していないカップホイール型砥石の砥石刃先に圧力が３〜２０ＭＰａの洗浄水を噴射する加圧水ドレッシングを行って前記砥石刃先に付着した屑を洗い流すことを特徴とする半導体装置の製造方法を提供するものである。
（１）．半導体回路を形成したシリコン基板の表面側に孔を多数穿孔し、この穿孔内面に絶縁膜とシード層を設け、更にこのシード層内面空間に銅（Ｃｕ）を充填した貫通電極柱を形成する工程。
（２）．接着剤シート材または接着剤を用いて前記銅貫通電極が形成されたシリコン基板の表面を基板チャック上に貼付する工程。
（３）．基板チャック上の前記銅貫通電極が形成されたシリコン基板の裏面をカップホイール型砥石によりシリコン（Ｓｉ）および銅（Ｃｕ）を同時に除く研削加工を行った後、更に、化学機械研磨加工を行い、５０ｎｍ以下のＳｉ−Ｃｕ段差の平坦化表面を得る銅貫通電極の第一次頭出し研削加工を行う工程。
（４）．前記シリコン基板の露出した銅貫通電極柱頭面にのみ、選択的にニッケル無電解メッキ層（キャップ）を形成させる工程。
（５）．前記ニッケル無電解メッキ層（キャップ）の形成されていないシリコン（Ｓｉ）面を、アルカリエッチング加工して銅貫通電極の第二次頭出し加工を行う工程。
（６）．前記銅貫通電極の第二次頭出し研削加工を行ったシリコン基板の表面に絶縁膜を堆積した後に、研磨加工またはエッチング加工により銅貫通電極柱上の前記絶縁膜を除去する工程。
The invention according to claim 2 is a method of manufacturing a semiconductor device in which the copper through electrode is cueed from the silicon substrate surface of the semiconductor device through the following steps, and the first cue grinding of the copper through electrode is performed. In the following step (3), the grindstone is subjected to pressurized water dressing in which cleaning water having a pressure of 3 to 20 MPa is sprayed onto a grindstone blade tip of a cupwheel grindstone that has not been subjected to grinding of the substrate of the cupwheel grindstone being ground. The present invention provides a method for manufacturing a semiconductor device, characterized in that wastes adhering to a blade edge are washed away .
(1). A step of drilling a large number of holes on the surface side of a silicon substrate on which a semiconductor circuit is formed, providing an insulating film and a seed layer on the inner surface of the hole, and further forming a through electrode pillar filled with copper (Cu) in the inner space of the seed layer .
(2). The process of sticking the surface of the silicon substrate in which the said copper penetration electrode was formed using an adhesive sheet material or an adhesive on a substrate chuck.
(3). After performing grinding processing to remove silicon (Si) and copper (Cu) simultaneously with a cup wheel type grindstone on the back surface of the silicon substrate on which the copper through electrode is formed on the substrate chuck, further performing chemical mechanical polishing processing, A step of performing a first cueing grinding process of a copper through electrode to obtain a flattened surface of a Si-Cu step of 50 nm or less.
(4). A step of selectively forming a nickel electroless plating layer (cap) only on the exposed copper penetrating electrode pillar surface of the silicon substrate;
(5). A step of performing a second cueing process of the copper through electrode by performing an alkali etching process on a silicon (Si) surface on which the nickel electroless plating layer (cap) is not formed.
(6). A step of removing the insulating film on the copper through-electrode column by polishing or etching after depositing an insulating film on the surface of the silicon substrate subjected to the second cueing grinding of the copper through-electrode.
貫通電極柱の周辺でのシリコン面への銅汚染が１．０ｘ１０１1ａｔｏｍｓ／ｃｍ２未満である半導体装置が得られる。（図２および図３参照）。 A semiconductor device in which the copper contamination on the silicon surface around the through electrode pillar is less than 1.0 × 10 11 atoms / cm 2 is obtained. (See FIGS. 2 and 3).
以下、図１および図４を用いてシリコン基板表面からの銅貫通電極の頭出しを行う方法を詳細に説明する。 Hereinafter, a method of cueing the copper through electrode from the surface of the silicon substrate will be described in detail with reference to FIGS.
実施例１
シリコン基板面内に内蔵された銅貫通電極柱は、次の（１）から（５）の工程を経て半導体装置のシリコン基板面からの銅貫通電極（Ｃｕ−ｖｉａ）の頭出し加工を行う。
Example 1
The copper penetration electrode pillar built in the silicon substrate surface performs the cue processing of the copper penetration electrode (Cu-via) from the silicon substrate surface of the semiconductor device through the following steps (1) to (5).
（１）．半導体回路が形成されたシリコン基板表面側にエッチング加工またはレザー加工により多数の孔を穿孔し、この穿孔内面に絶縁膜を設けた後、タンタル（Ｔａ）系またはチタン（Ｔｉ）系メタルシード層を設け、更にこのメタルシード層内面空間に電解銅メッキ方法または銅樹脂ペーストを充填して銅貫通電極柱（プラグ）を形成する工程。(図１ａ参照) (1). A number of holes are drilled by etching or leather processing on the silicon substrate surface side where the semiconductor circuit is formed, and an insulating film is provided on the inner surface of the hole, and then a tantalum (Ta) or titanium (Ti) metal seed layer is formed. And a step of forming a copper through electrode column (plug) by filling the inner space of the metal seed layer with an electrolytic copper plating method or a copper resin paste. (See Figure 1a)
（２）．接着剤シートまたは接着剤を用いて前記銅貫通電極が形成されたシリコン基板の表面を研削装置の基板チャック２ａ上に貼付する。(図１ｂ参照) (2). The surface of the silicon substrate on which the copper penetrating electrode is formed is pasted on the substrate chuck 2a of the grinding apparatus using an adhesive sheet or an adhesive. (See Figure 1b)
（３）．上記基板チャック上の前記銅貫通電極が形成されたシリコン基板のＢＥＯＬ反対面をカップホイール型砥石によりシリコン（Ｓｉ）および銅（Ｃｕ）を同時に除く研削加工を行い、５０ｎｍ以下のＳｉ−Ｃｕ段差の平坦化表面を得る銅貫通電極の第一次頭出し加工を行う工程。(図１ｃ参照) (3). The BEOL opposite surface of the silicon substrate on which the copper through electrode is formed on the substrate chuck is subjected to grinding processing by simultaneously removing silicon (Si) and copper (Cu) with a cup wheel type grindstone, and a Si-Cu step difference of 50 nm or less is obtained. A step of performing a first cueing process of a copper through electrode to obtain a flattened surface. (See Figure 1c)
具体的には、図４に示す研削装置１を用い、銅貫通電極が形成されたシリコン基板ｗの表面をカップホイール型研削砥石３により表面平坦化加工を行う。 Specifically, using the grinding apparatus 1 shown in FIG. 4, the surface of the silicon substrate w on which the copper penetrating electrode is formed is subjected to surface flattening with a cup wheel grinding wheel 3.
前記研削装置１は、基板チャック２ａを回転軸２ｂに軸承させた基板吸着チャック機構２、砥石軸３ｂに軸承された高い砥番のカップホイール型研削砥石３ａを備える砥石ヘッド３、該研削砥石の砥石刃先３ａｇを高圧ジェット洗浄するノズル４ａを備える洗浄液噴射装置４および貫通電極付きセラミック基板の貫通電極が形成されている面に研削液を供給する研削液供給ノズル５を備える。図中、６は脱気管、７は給水管、および、８は流体室である。 The grinding apparatus 1 includes a substrate suction chuck mechanism 2 in which a substrate chuck 2a is supported on a rotary shaft 2b, a grinding wheel head 3 including a cup wheel type grinding wheel 3a having a high grinding number supported on a grinding wheel shaft 3b, and the grinding wheel the grinding wheel cutting edge 3a g comprising a grinding liquid supply nozzle 5 for supplying a grinding fluid to a surface cleaning liquid injection device 4 and the through electrode with the ceramic substrate through electrode is formed with a nozzle 4a of the high-pressure jet cleaning. In the figure, 6 is a deaeration pipe, 7 is a water supply pipe, and 8 is a fluid chamber.
前記カップホイール型研削砥石３は、砥粒素材として砥番＃３００〜＃１，２００のダイヤモンド、ｃＢＮ、ＳｉＣの砥粒を用いたビトリアイドボンド砥石、メタルボンド砥石、レジンボンド砥石などが利用できる。なかでも、ダイヤモンドビトリファイドボンドカップホイール型研削砥石が面平坦度仕上げおよび研削速度の面で優れる。 The cup wheel type grinding wheel 3 can use a vitriamide bond wheel, a metal bond wheel, a resin bond wheel, etc. using diamonds of diamond numbers # 300 to # 1,200, cBN, and SiC as abrasive materials. . Among these, diamond vitrified bond cup wheel type grinding wheels are excellent in terms of surface flatness finishing and grinding speed.
研削液供給ノズル５より供給される研削液としては、純水が一般であるが、セラミックおよび電極素材の金属によっては、純水以外のエタノールアミン水溶液、テトラメチルアンモニウムヒドロキシド水溶液、苛性カリ水溶液、酢酸、塩酸等の導電性水溶液、セリア水分散液、コロイダルシリカ水分散液、アルミナ水分散液なども利用してもよい。 As the grinding fluid supplied from the grinding fluid supply nozzle 5, pure water is generally used, but depending on the ceramic and the metal of the electrode material, an ethanolamine aqueous solution other than pure water, tetramethylammonium hydroxide aqueous solution, caustic potash aqueous solution, acetic acid A conductive aqueous solution such as hydrochloric acid, a ceria aqueous dispersion, a colloidal silica aqueous dispersion, an alumina aqueous dispersion, or the like may also be used.
洗浄液噴射装置４のノズル４ａより供給される洗浄液としては、上述の研削液を用いてもよいが、排水処理の面から純水が一般的である。洗浄水の砥石刃３ａｇへの噴射角度は５〜１８度の扇形状である。 As the cleaning liquid supplied from the nozzle 4a of the cleaning liquid injection device 4, the above-described grinding liquid may be used, but pure water is generally used from the viewpoint of wastewater treatment. Injection angle to the grindstone blade 3a g of washing water is sector-shaped in 5 to 18 degrees.
洗浄液噴射装置４としては、旭サナック株式会社の精密高圧ジェット水洗浄機械“ＨＰＭＪ ＡＦＳ５４００Ｓ”（商品名）が利用できる。 As the cleaning liquid injection device 4, a precision high-pressure jet water cleaning machine “HPMJ AFS5400S” (trade name) manufactured by Asahi Sunac Corporation can be used.
上記研削装置１のカップホイール型研削砥石３ｇを用いて銅貫通電極が形成されたシリコン基板（ワーク）ｗの表面平坦化加工を行う銅貫通電極の第一次頭出し加工作業は、回転軸２ｂを１００〜１５０ｍｉｎ−１回転させることによりワークを回転させ、高粒度カップホイール型研削砥石３の砥石軸３ｂを１，２００〜２，０００ｍｉｎ−１回転させながら３０μｍ／分の下降速度で下降させて、そのカップホイール型研削砥石の砥石刃先３ａｇを前記ワークｗ表面上で摺擦させて厚みを所望量（２〜５０μｍ）減少させるワークの仕上げ研削加工をするとともに、この研削加工中に前記カップホイール型研削砥石のセラミック基板の表面研削加工に供されていないポーラスセラミックテーブル２ａ外領域部分の砥石刃先３ａｇにこの砥石刃までの距離５〜２０ｍｍ位置にあるノズル噴出口４ａより圧力３〜２０ＭＰａ、好ましくは、１０〜１２ＭＰａの洗浄水を噴射させて砥石刃に付着した銅電極研削屑、絶縁層研削屑、樹脂研削屑等を洗い流す砥石刃洗浄工程（加圧水ドレッシング）を行う。上記研削加工中、ワークの表面には研削液供給ノズル５より研削液が１０〜２０リットル／分の割合で供給される。 The first cueing work of the copper through electrode that performs the surface flattening process of the silicon substrate (workpiece) w on which the copper through electrode is formed using the cup wheel type grinding wheel 3g of the grinding apparatus 1 is the rotating shaft 2b. the rotating the workpiece by causing 100～150Min -1 rotate, is lowered at a lowering speed of 30 [mu] m / min while the grindstone shaft 3b of Kotsubudo cup wheel grinding wheel 3 is 1,200～2,000Min -1 rotated , the cup with, during the grinding to finish grinding of the workpiece to the desired amount of thickness is rubbed grinding wheel cutting edge 3a g on the workpiece w surface of the cup wheel grinding wheel (2 to 50 [mu] m) decreased the abrasive in grinding the cutting edge 3a g of porous ceramic table 2a extracellular region portion which is not subjected to the surface grinding of the ceramic substrate of the wheel grinding wheel Copper electrode grinding waste, insulating layer grinding waste, resin grinding adhered to the grinding wheel blade by spraying cleaning water at a pressure of 3 to 20 MPa, preferably 10 to 12 MPa from the nozzle outlet 4a located at a distance of 5 to 20 mm from the blade. A grinding wheel cleaning process (pressurized water dressing) is performed to wash away debris and the like. During the grinding process, the grinding liquid is supplied from the grinding liquid supply nozzle 5 to the surface of the workpiece at a rate of 10 to 20 liters / minute.
（４）．前記シリコン基板のシリコン上面より突出した銅貫通電極柱頭面にのみ選択的にニッケル（Ｎｉ）無電解メッキ層（キャップ）を形成させる工程。(図１ｄ参照) (4). A step of selectively forming a nickel (Ni) electroless plating layer (cap) only on the top surface of the through silicon via electrode protruding from the silicon upper surface of the silicon substrate; (See Figure 1d)
ニッケル無電解メッキ方法は、公知の技術を用いる。キャップ層を形成するニッケル無電解メッキ液は、ニッケル（Ｎｉ）の他に硼素（Ｂ）、燐（Ｐ）、または、コバルト（Ｃｏ）を含有していてもよい。本願実施例では、ニッケル無電解メッキ液１リットルの組成は、クエン酸三ナトリウム ５８．８２ｇ、硫酸ニッケル ２６．２８ｇ、ジメチルアミノボラン ２．９４６ｇ、残余 純水 の組成物を使用した。 The nickel electroless plating method uses a known technique. The nickel electroless plating solution for forming the cap layer may contain boron (B), phosphorus (P), or cobalt (Co) in addition to nickel (Ni). In this embodiment, the composition of 1 liter of nickel electroless plating solution was 58.82 g of trisodium citrate, 26.28 g of nickel sulfate, 2.946 g of dimethylaminoborane, and the remaining pure water.
（５）．前記銅貫通電極柱頭に形成されたニッケル無電解メッキ層（キャップ層）の形成されていないＳｉ面をアルカリエッチングまたは化学的機械研磨（ＣＭＰ）加工して銅貫通電極の第二次頭出し加工を行う工程。(図１ｅ参照) (5). The Si surface on which the nickel electroless plating layer (cap layer) formed on the copper through electrode stigma is not formed is subjected to alkali etching or chemical mechanical polishing (CMP) processing to perform secondary cueing of the copper through electrode. The process to perform. (See Fig. 1e)
アルカリエッチング液としては、水酸化カリウム、水酸化ナトリウム、水酸化リチウム、テトラメチルアンモニウム、トリメチルアンモニウムヒドロキシド、テトラメチルアンモニウムヒドロキシド（ＴＭＡＨ）、テトラエチルアンモニウムヒドロキシド（ＴＥＡＨ）、テトラプロピルアンモニウムヒドロキシド（ＴＰＡＨ）、テトラブチルアンモニウムヒドロキシド（ＴＢＡＨ）、トリメチルヒドロキシエチルアンモニウムヒドロキシド（コリン）、メチルトリ（ヒドロキシエチル）アンモニウムヒドロキシド、テトラ（ヒドロキシエチル）アンモニウムヒドロキシド、ベンジルトリメチルアンモニウムヒドロキシド（ＢＴＭＡＨ）、エタノールアミン、ジエタノールアミン、トリエタノールアミン、第３ブチルジエタノールアミン、イソプロパノールアミン、ジエチレントリアミン、トリエチレンテトラミン等の塩基性化合物の１種単独又は２種以上を混合したｐＨ１０〜ｐＨ１２のアルカリ剤の水溶液を利用できる。塩基性化合物の含有量は、０．１〜５質量％であることが好ましい。また、化学的機械研磨液としては、コロイダルシリカ、上記塩基性化合物等の単独または２種水溶液、水分散液が使用できる。実施例１では、ｐＨ１２の水酸化カリウム、テトラメチルアンモニウムヒドロキシド（ＴＭＡＨ）混合水溶液を用いた。 Examples of the alkaline etching solution include potassium hydroxide, sodium hydroxide, lithium hydroxide, tetramethylammonium, trimethylammonium hydroxide, tetramethylammonium hydroxide (TMAH), tetraethylammonium hydroxide (TEAH), tetrapropylammonium hydroxide ( TPAH), tetrabutylammonium hydroxide (TBAH), trimethylhydroxyethylammonium hydroxide (choline), methyltri (hydroxyethyl) ammonium hydroxide, tetra (hydroxyethyl) ammonium hydroxide, benzyltrimethylammonium hydroxide (BTMAH), ethanol Amine, diethanolamine, triethanolamine, tert-butyldiethanolamine, iso Ropanoruamin available diethylenetriamine, an aqueous solution of one or two or more alkaline agents pH10~pH12 mixed basic compound such as triethylene tetramine. It is preferable that content of a basic compound is 0.1-5 mass%. Further, as the chemical mechanical polishing liquid, colloidal silica, the above basic compound or the like alone or two kinds of aqueous solutions and aqueous dispersions can be used. In Example 1, a pH 12 mixed aqueous solution of potassium hydroxide and tetramethylammonium hydroxide (TMAH) was used.
（６）．前記銅貫通電極の第二次頭出し加工を行ったシリコン基板の表面に絶縁膜（ｉｎｓｕｌａｔｏｒ）を堆積した後に、ＣＭＰ組成物、研磨パフを用いて研磨加工し、銅貫通電極柱上の前記絶縁膜を除去した。実施例１ではＣＭＰ組成物としてコロイダルシリカを５容量％のシリカ濃度で塩基性化合物（ＫＯＨ）の添加でｐＨが１２に調整されたシリカ水分散液を使用し、絶縁膜として酸化シリコン膜を用いた。(図１ｆ参照)。 (6). After an insulating film (insulator) is deposited on the surface of the silicon substrate subjected to the second cueing process of the copper through electrode, the insulating composition on the copper through electrode column is polished by using a CMP composition and a polishing puff. The membrane was removed. In Example 1, colloidal silica was used as a CMP composition, a silica aqueous dispersion whose pH was adjusted to 12 by adding a basic compound (KOH) at a silica concentration of 5% by volume, and a silicon oxide film was used as an insulating film. It was. (See FIG. 1f).
第二次頭出し加工を行った銅貫通電極シリコン基板（ｗ）のＴｏＦ−ＳＩＭＳ図（測定距離幅は２５０μｍで３つの銅電極柱頭が含まれる）を図２に、光学顕微鏡写真を図３に示す。 The ToF-SIMS figure of the copper through-electrode silicon substrate (w) subjected to the secondary cue processing (measurement distance width is 250 μm and includes three copper electrode stigmas) is shown in FIG. 2, and the optical micrograph is shown in FIG. Show.
実施例２
実施例１において、工程（３）を次の工程（３）に変更し、工程（６）における研磨加工をアルカリエッチング加工に変える外は、同様な工程（１）乃至（６）の工程を実施して銅貫通電極シリコン基板を製造した。
Example 2
In Example 1, the same steps (1) to (6) are performed except that the step (3) is changed to the next step (3) and the polishing process in the step (6) is changed to an alkali etching process. Thus, a copper through electrode silicon substrate was manufactured.
（３）．基板チャック上の前記銅貫通電極が形成されたシリコン基板の裏面をカップホイール型研削砥石によりシリコン（Ｓｉ）および銅（Ｃｕ）を同時に除く研削加工を行った後、更に、ＣＭＰ組成物、研磨パフを用いる化学機械研磨（ＣＭＰ）加工を行い、５０ｎｍ以下のＳｉ−Ｃｕ段差の平坦化表面を得る銅貫通電極の第一次頭出し加工を行った。 (3). After the back surface of the silicon substrate on which the copper through electrode is formed on the substrate chuck is subjected to grinding processing by simultaneously removing silicon (Si) and copper (Cu) with a cup wheel type grinding wheel, a CMP composition, a polishing puff Chemical mechanical polishing (CMP) processing using a copper was performed, and the first cueing processing of the copper through electrode for obtaining a planarized surface with a Si-Cu step of 50 nm or less was performed.
上記ＣＭＰ組成物としてコロイダルシリカを５容量％のシリカ濃度で塩基性化合物（ＫＯＨ）の添加でｐＨが１２に調整されたシリカ水分散液を使用した。 As the CMP composition, an aqueous silica dispersion in which colloidal silica was adjusted to pH 12 by adding a basic compound (KOH) at a silica concentration of 5 vol% was used.
第二次頭出し加工を行った銅貫通電極シリコン基板（ｗ）の貫通電極柱の周辺のシリコン面上に銅汚染（Ｓｍｅａｒｉｎｇ）は見受けられず、ＴｏＦ−ＳＩＭＳ図（測定距離幅は２５０μｍ）により測定された貫通電極柱の周辺でのシリコン面への銅汚染量が１．０ｘ１０１０ａｔｏｍｓ／ｃｍ２から８．０ｘ１０１０ａｔｏｍｓ／ｃｍ２である半導体装置が得られた。 No copper contamination (Smearing) was found on the silicon surface around the through electrode column of the copper through electrode silicon substrate (w) subjected to the second cueing processing, and the ToF-SIMS diagram (measurement distance width is 250 μm) A semiconductor device in which the measured amount of copper contamination on the silicon surface around the through electrode column was 1.0 × 10 10 atoms / cm 2 to 8.0 × 10 10 atoms / cm 2 was obtained.
シリコン基板表面からの銅貫通電極の露出（頭出し）高さのばらつきが小さく、銅貫通電極柱周辺のシリコン領域に銅汚染のない貫通電極シリコン基板が得られる。 The variation in the exposed (cue) height of the copper through electrode from the silicon substrate surface is small, and a through electrode silicon substrate free from copper contamination in the silicon region around the copper through electrode column can be obtained.
１ 研削装置
ｗ 銅貫通電極が形成されたシリコン基板
２ 基板チャック機構
３ カップホイール型研削砥石
４ 洗浄液噴射装置
４ａ 高圧ジェット洗浄するノズル
５ 研削液供給ノズル
DESCRIPTION OF SYMBOLS 1 Grinding device w Silicon substrate in which copper through electrode was formed 2 Substrate chuck mechanism 3 Cup wheel type grinding wheel 4 Cleaning fluid injection device 4a Nozzle for high-pressure jet cleaning 5 Grinding fluid supply nozzle
Claims (2)
（１）．半導体回路を形成したシリコン基板の表面側に孔を多数穿孔し、この穿孔内面に絶縁膜とシード層を設け、更にこのシード層内面空間に銅を充填した貫通電極柱を形成する工程。
（２）．接着剤シート材または接着剤を用いて前記銅貫通電極が形成されたシリコン基板の表面を基板チャック上に貼付する工程。
（３）．基板チャック上の前記銅貫通電極が形成されたシリコン基板の裏面をカップホイール型砥石によりシリコンおよび銅を同時に除く研削加工を行い、５０ｎｍ以下のＳｉ−Ｃｕ段差の平坦化表面を得る銅貫通電極の第一次頭出し研削加工を行う工程。
（４）．前記シリコン基板の露出した銅貫通電極柱頭面にのみ、選択的にニッケル無電解メッキ層を形成させる工程。
（５）．前記ニッケル無電解メッキ層の形成されていないシリコン面を、アルカリエッチングまたは化学的機械研磨加工して銅貫通電極の第二次頭出し研削加工を行う工程。
（６）．前記銅貫通電極の第二次頭出し研削加工を行ったシリコン基板の表面に絶縁膜を堆積した後に、研磨加工またはエッチング加工により銅貫通電極柱上の前記絶縁膜を除去する工程。 In the following step (3), a semiconductor device manufacturing method for cueing a copper through electrode from the silicon substrate surface of the semiconductor device through the following step, wherein the first cue grinding of the copper through electrode is performed, Washing off debris adhering to the grinding wheel edge by performing pressurized water dressing that injects cleaning water with a pressure of 3 to 20 MPa on the grinding wheel edge of the cup wheel grinding wheel that is not used for grinding of the substrate of the cup wheel grinding wheel being ground. A method for manufacturing a semiconductor device.
(1). A step of drilling a large number of holes on the surface side of a silicon substrate on which a semiconductor circuit is formed, providing an insulating film and a seed layer on the inner surface of the hole, and forming a through electrode column filled with copper in the inner space of the seed layer.
(2). The process of sticking the surface of the silicon substrate in which the said copper penetration electrode was formed using an adhesive sheet material or an adhesive on a substrate chuck.
(3). The back surface of the silicon substrate on which the copper through electrode is formed on the substrate chuck is ground by removing simultaneously silicon and copper with a cup wheel type grindstone to obtain a planarized surface of a Si-Cu step of 50 nm or less. The first cue grinding process.
(4). A step of selectively forming a nickel electroless plating layer only on the exposed copper through electrode column top surface of the silicon substrate;
(5). A step of performing a second cueing grinding process of the copper penetrating electrode by performing alkali etching or chemical mechanical polishing on the silicon surface on which the nickel electroless plating layer is not formed.
(6). A step of removing the insulating film on the copper through-electrode column by polishing or etching after depositing an insulating film on the surface of the silicon substrate subjected to the second cueing grinding of the copper through-electrode.
（１）．半導体回路を形成したシリコン基板の表面側に孔を多数穿孔し、この穿孔内面に絶縁膜とシード層を設け、更にこのシード層内面空間に銅を充填した貫通電極柱を形成する工程。
（２）．接着剤シート材または接着剤を用いて前記銅貫通電極が形成されたシリコン基板の表面を基板チャック上に貼付する工程。
（３）．基板チャック上の前記銅貫通電極が形成されたシリコン基板の裏面をカップホイール型砥石によりシリコンおよび銅を同時に除く研削加工を行った後、更に、化学機械研磨加工を行い、５０ｎｍ以下のＳｉ−Ｃｕ段差の平坦化表面を得る銅貫通電極の第一次頭出し研削加工を行う工程。
（４）．前記シリコン基板のシリコン上面より突出した銅貫通電極柱頭面にのみ選択的にニッケル無電解メッキ層を形成させる工程。
（５）．前記ニッケル無電解メッキ層の形成されていないシリコン面を、アルカリエッチング加工して銅貫通電極の第二次頭出し加工を行う工程。
（６）．前記銅貫通電極の第二次頭出し研削加工を行ったシリコン基板の表面に絶縁膜を堆積した後に、研磨加工またはエッチング加工により銅貫通電極柱上の前記絶縁膜を除去する工程。 In the following step (3), a semiconductor device manufacturing method for cueing a copper through electrode from the silicon substrate surface of the semiconductor device through the following step, wherein the first cue grinding of the copper through electrode is performed, Washing off debris adhering to the grinding wheel edge by performing pressurized water dressing that injects cleaning water with a pressure of 3 to 20 MPa on the grinding wheel edge of the cup wheel grinding wheel that is not used for grinding of the substrate of the cup wheel grinding wheel being ground. A method for manufacturing a semiconductor device.
(1). A step of drilling a large number of holes on the surface side of a silicon substrate on which a semiconductor circuit is formed, providing an insulating film and a seed layer on the inner surface of the hole, and forming a through electrode column filled with copper in the inner space of the seed layer.
(2). The process of sticking the surface of the silicon substrate in which the said copper penetration electrode was formed using an adhesive sheet material or an adhesive on a substrate chuck.
(3). After the back surface of the silicon substrate on which the copper through electrode is formed on the substrate chuck is subjected to a grinding process that simultaneously removes silicon and copper with a cup wheel type grindstone, a chemical mechanical polishing process is further performed to obtain a Si-Cu of 50 nm or less. A step of performing a first cueing grinding process of a copper through electrode to obtain a flattened surface of a step.
(4). A step of selectively forming a nickel electroless plating layer only on the top surface of the through silicon via electrode protruding from the silicon upper surface of the silicon substrate;
(5). A step of performing a second cueing process of the copper through electrode by performing an alkali etching process on the silicon surface on which the nickel electroless plating layer is not formed.
(6). A step of removing the insulating film on the copper through-electrode column by polishing or etching after depositing an insulating film on the surface of the silicon substrate subjected to the second cueing grinding of the copper through-electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013160954A JP5827277B2 (en) | 2013-08-02 | 2013-08-02 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013160954A JP5827277B2 (en) | 2013-08-02 | 2013-08-02 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2015032679A JP2015032679A (en) | 2015-02-16 |
| JP5827277B2 true JP5827277B2 (en) | 2015-12-02 |
Family
ID=52517767
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013160954A Active JP5827277B2 (en) | 2013-08-02 | 2013-08-02 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5827277B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6616174B2 (en) * | 2015-12-01 | 2019-12-04 | 株式会社岡本工作機械製作所 | Planarization method for bumped device silicon substrate |
| JP6850099B2 (en) * | 2016-09-23 | 2021-03-31 | 株式会社岡本工作機械製作所 | Semiconductor manufacturing method and semiconductor manufacturing equipment |
| JP7121499B2 (en) * | 2018-02-07 | 2022-08-18 | 株式会社岡本工作機械製作所 | Semiconductor device manufacturing method |
| JP7270373B2 (en) | 2018-12-20 | 2023-05-10 | 株式会社岡本工作機械製作所 | Grinding method and grinding apparatus for composite substrate containing resin |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63272053A (en) * | 1987-04-30 | 1988-11-09 | Oki Electric Ind Co Ltd | Method of forming multilayer interconnection |
| JPH0632885B2 (en) * | 1987-05-19 | 1994-05-02 | 日清工業株式会社 | Ceramic grinding method and device |
| JPH0812361A (en) * | 1994-06-30 | 1996-01-16 | Asahi Glass Co Ltd | Method for dressing grinding wheel and device therefor |
| JP2832184B2 (en) * | 1996-08-08 | 1998-12-02 | 直江津電子工業株式会社 | Method for manufacturing silicon semiconductor discrete wafer |
| JP2000133623A (en) * | 1998-10-28 | 2000-05-12 | Toshiba Corp | Planarizing method and equipment |
| JP3515449B2 (en) * | 1999-10-13 | 2004-04-05 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| JP2005109427A (en) * | 2003-09-12 | 2005-04-21 | Shinko Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP4340517B2 (en) * | 2003-10-30 | 2009-10-07 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
| JP3880602B2 (en) * | 2005-02-17 | 2007-02-14 | シャープ株式会社 | Semiconductor device manufacturing method, semiconductor device |
| JP2006315127A (en) * | 2005-05-12 | 2006-11-24 | Denso Corp | Removing method and grinding method |
| JP4927484B2 (en) * | 2006-09-13 | 2012-05-09 | 株式会社ディスコ | Method for manufacturing device for lamination |
| JP2009065019A (en) * | 2007-09-07 | 2009-03-26 | Sony Corp | Wiring structure, memory element and its fabrication method, and storage device |
| JP2011151138A (en) * | 2010-01-20 | 2011-08-04 | Panasonic Corp | Manufacturing method for semiconductor device |
| JP5560144B2 (en) * | 2010-08-31 | 2014-07-23 | 東京エレクトロン株式会社 | Manufacturing method of semiconductor device |
-
2013
- 2013-08-02 JP JP2013160954A patent/JP5827277B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2015032679A (en) | 2015-02-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8263497B2 (en) | High-yield method of exposing and contacting through-silicon vias | |
| US9224796B2 (en) | Process for producing a through-silicon via and a through-silicon capacitor in a substrate, and corresponding device | |
| TWI525720B (en) | Semiconductor device and method of forming the same | |
| JP5827277B2 (en) | Manufacturing method of semiconductor device | |
| US7074703B2 (en) | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument | |
| US20120018893A1 (en) | Methods of forming semiconductor elements using micro-abrasive particle stream | |
| JP6616174B2 (en) | Planarization method for bumped device silicon substrate | |
| US10074595B2 (en) | Self-alignment for redistribution layer | |
| US10600689B2 (en) | Vias and conductive routing layers in semiconductor substrates | |
| JP6850099B2 (en) | Semiconductor manufacturing method and semiconductor manufacturing equipment | |
| KR20130066561A (en) | Chemical planarization of copper wafer polishing | |
| JP2017103441A5 (en) | ||
| TW201724449A (en) | Semiconductor device and method for manufacturing same | |
| JP2006228947A (en) | Semiconductor device and method of manufacturing same | |
| EP3123499B1 (en) | Through-body via formation techniques | |
| US8535977B2 (en) | Semiconductor device manufacturing method | |
| TW201724293A (en) | Fabrication method for semiconductor device | |
| US20140238725A1 (en) | Method of flattening surface of conductive structure and conductive structure with flattened surface | |
| Watanabe et al. | Improvement of a TSV reveal process comprising direct Si/Cu grinding and residual metal removal | |
| CN111276397A (en) | Method for processing wafer | |
| JP5130740B2 (en) | Manufacturing method of semiconductor device and apparatus used for the method | |
| JP4085972B2 (en) | Manufacturing method of semiconductor device | |
| CN115179186B (en) | Method for manufacturing semiconductor device | |
| CN104143525B (en) | Through-silicon-via back metal flattening method | |
| Rudolph et al. | Challenges of TSV backside process integration |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20141210 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150602 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20151013 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20151015 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5827277 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313115 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |