JP5738750B2 - Oscillator circuit - Google Patents

Oscillator circuit Download PDF

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JP5738750B2
JP5738750B2 JP2011278523A JP2011278523A JP5738750B2 JP 5738750 B2 JP5738750 B2 JP 5738750B2 JP 2011278523 A JP2011278523 A JP 2011278523A JP 2011278523 A JP2011278523 A JP 2011278523A JP 5738750 B2 JP5738750 B2 JP 5738750B2
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initialization
oscillation
unit
power supply
supply voltage
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JP2013131832A (en
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島村　俊重
俊重 島村
宇賀神　守
守 宇賀神
中村　光男
光男 中村
賢一 松永
賢一 松永
尚一 大嶋
尚一 大嶋
原田　充
充 原田
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Nippon Telegraph and Telephone Corp
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Description

本発明は、電源電圧の変動に応じて負荷容量を制御し、発振周波数を安定化させる発振回路に関する。   The present invention relates to an oscillation circuit that stabilizes an oscillation frequency by controlling a load capacitance according to fluctuations in a power supply voltage.

図５は、従来の発振回路の構成例を示す（特許文献１）。
図５において、遅延回路を構成するインバータ３０に、トランジスタＰ５３とＮ５３からなる電圧制御型電流源部６０によって電源電圧依存性のない定電流Ｉ３１とＩ３２を供給し、インバータ３０の出力端子に容量素子Ｃ５１，Ｃ５２およびスイッチング用トランジスタＰ５５とＮ５５からなる負荷容量部６０を接続し、制御電圧発生部１０において電源電圧ＶDDまたは共通電位ＶSSからそれぞれ一定の電圧差を有する制御電圧ＶBP，ＶBNを生成し、これらの制御電圧に応じて負荷容量部６０の容量素子の充放電時に電圧の変動幅を一定に保ち、遅延回路の遅延時間を電源電圧に依存せず一定に保持する構成である。このような遅延回路により構成された発振回路は、電源電圧の変動に対して安定した発振周波数が得られる。 FIG. 5 shows a configuration example of a conventional oscillation circuit (Patent Document 1).
In FIG. 5, constant currents I31 and I32 having no power supply voltage dependency are supplied to an inverter 30 constituting a delay circuit by a voltage-controlled current source unit 60 composed of transistors P53 and N53, and a capacitive element is connected to the output terminal of the inverter 30. Control voltage V BP , V BN having a constant voltage difference from the power supply voltage V DD or the common potential V SS in the control voltage generator 10 is connected to the load capacitance unit 60 composed of C51, C52 and switching transistors P55 and N55. The voltage fluctuation range is kept constant during charging / discharging of the capacitive element of the load capacitance unit 60 according to these control voltages, and the delay time of the delay circuit is kept constant regardless of the power supply voltage. . An oscillation circuit constituted by such a delay circuit can obtain a stable oscillation frequency against fluctuations in the power supply voltage.

特開２００１−２８５０３６号公報JP 2001-285036 A

図５に示す発振回路の制御電圧発生部１０は、ダイオード接続トランジスタ（Ｐ５１，Ｐ５２、Ｎ５１，Ｎ５２）と抵抗素子（Ｒ５１，Ｒ５２）を直列接続した構成により、電源電圧の変動をモニタし、それに応じた制御電圧ＶBP，ＶBNを生成する構成である。そのため、所定の直流電流が流れ、マイクロファラッドレベルの容量素子に蓄えられた電荷を電源とする場合に、動作させることができなかった。 The control voltage generator 10 of the oscillation circuit shown in FIG. 5 monitors the fluctuation of the power supply voltage by the configuration in which the diode connection transistors (P51, P52, N51, N52) and the resistance elements (R51, R52) are connected in series. The control voltages V BP and V BN are generated accordingly. For this reason, when a predetermined direct current flows and the electric charge stored in the capacitance element at the microfarad level is used as a power source, it cannot be operated.

本発明は、マイクロファラッドレベルの容量で供給する電源を用い、電流供給が小さくかつ電圧変動が大きい電源電圧に対して、安定した発振周波数を得ることができる発振回路を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide an oscillation circuit that can obtain a stable oscillation frequency with respect to a power supply voltage that uses a power supply with a microfarad level capacity and has a small current supply and a large voltage fluctuation.

本発明は、電源電圧に応じて発振周波数が変化する発振部と、発振部に接続される抵抗値を可変させて発振周波数を制御する可変抵抗部と、電源電圧と接地電位との間にダイオード素子と容量素子を直列に接続し、ダイオード素子と容量素子との間から電源電圧に応じた制御電圧を取り出す構成であり、さらに容量素子に並列に初期化スイッチを接続し、任意または所定のタイミングで入力する初期化信号により初期化スイッチをオンとして容量素子の電荷を放電し、初期化スイッチオフ時に電源電圧に応じた制御電圧を出力できる状態とした後に初期化スイッチをオフとする初期化手段を含む制御電圧発生部とを備え、初期化スイッチのオフ期間に、電源電圧が低下すれば可変抵抗部の抵抗値を高くし、電源電圧が上昇すれば可変抵抗部の抵抗値を低くする制御電圧によって発振周波数を安定化する構成である。
The present invention relates to an oscillation unit whose oscillation frequency changes according to a power supply voltage, a variable resistance unit which controls the oscillation frequency by changing a resistance value connected to the oscillation unit, and a diode between the power supply voltage and the ground potential connect element and a capacitive element in series, a structure for taking out a control voltage corresponding to the power supply voltage from between the diode element and a capacitive element, further connects the initialization switch in parallel with the capacitive element, any or predetermined Initialization that turns off the initialization switch after turning on the initialization switch by the initialization signal input at the timing to discharge the charge of the capacitive element and enabling the output of the control voltage according to the power supply voltage when the initialization switch is off and a control voltage generator comprising means, during the off period of the initialization switch, if lowering the power supply voltage to increase the resistance of the variable resistor, the power supply voltage variable resistor unit of if elevated It is configured to stabilize the oscillation frequency by the control voltage to lower the anti-values.

本発明の発振回路において、並列接続の初期化スイッチと容量素子は、初期化信号によりオンオフするスイッチングトランジスタとその寄生容量である。
In the oscillation circuit of the present invention, the initialization switch and the capacitive element connected in parallel are a switching transistor that is turned on / off by an initialization signal and its parasitic capacitance.

本発明の発振回路において、初期化手段は、発振部の出力信号を初期化信号として制御電圧発生部の初期化スイッチに入力する構成である。   In the oscillation circuit of the present invention, the initialization means is configured to input the output signal of the oscillation unit as an initialization signal to the initialization switch of the control voltage generation unit.

本発明の発振回路において、初期化手段は、発振部の出力信号の分周信号を初期化信号として制御電圧発生部の初期化スイッチに入力する構成である。   In the oscillation circuit of the present invention, the initialization means is configured to input the frequency-divided signal of the output signal of the oscillation unit to the initialization switch of the control voltage generation unit as an initialization signal.

本発明の発振回路は、制御電圧発生部の直流電流を、初期化時を除きゼロ化することができ、消費電流を低減できるので、例えばマイクロファラッドレベルの容量素子から電荷が供給される電源でも動作させることができる。したがって、振動発電素子や太陽電池から生成される微小な電流でも、容量に蓄積することで、本発明の発振回路を動作させることができる。また、電源部の発電量を大きくする必要がないので、発電素子や蓄電用容量の体積を小さくすることができる。   The oscillation circuit of the present invention can zero out the DC current of the control voltage generator except during initialization, and can reduce current consumption. For example, the oscillation circuit operates even with a power source supplied with charge from a microfarad level capacitive element. Can be made. Therefore, the oscillation circuit of the present invention can be operated by accumulating even a minute current generated from the vibration power generation element or the solar cell in the capacitor. Further, since it is not necessary to increase the power generation amount of the power supply unit, it is possible to reduce the volume of the power generation element and the storage capacity.

本発明の発振回路の実施例１の構成を示す図である。It is a figure which shows the structure of Example 1 of the oscillation circuit of this invention. 実施例１の発振回路の動作例を示すタイムチャートである。3 is a time chart illustrating an operation example of the oscillation circuit according to the first embodiment. 本発明の発振回路の実施例２の構成を示す図である。It is a figure which shows the structure of Example 2 of the oscillation circuit of this invention. 本発明の発振回路の実施例３の構成を示す図である。It is a figure which shows the structure of Example 3 of the oscillation circuit of this invention. 従来の発振回路の構成例を示す図である。It is a figure which shows the structural example of the conventional oscillation circuit.

図１は、本発明の発振回路の実施例１の構成を示す。
図１において、実施例１の発振回路は、発振部１００、可変抵抗部２００および制御電圧発生部３００により構成される。 FIG. 1 shows a configuration of an oscillation circuit according to a first embodiment of the present invention.
1, the oscillation circuit according to the first embodiment includes an oscillation unit 100, a variable resistance unit 200, and a control voltage generation unit 300.

発振部１００は、図５に示す従来の発振回路におけるインバータ３０に相当し、ここではＮＡＮＤ回路１０１、インバータ１０２、インバータ１０３をループ接続したリングオシレータを示す。ＮＡＮＤ回路１０１の一方の入力端子に許可信号が入力して発振動作を開始し、発振信号がインバータ１０３の出力から分岐して出力端子に取り出される。なお、図５に示す電流源などは省略している。   The oscillating unit 100 corresponds to the inverter 30 in the conventional oscillating circuit shown in FIG. 5, and here shows a ring oscillator in which the NAND circuit 101, the inverter 102, and the inverter 103 are connected in a loop. An enable signal is input to one input terminal of the NAND circuit 101 to start an oscillation operation, and the oscillation signal is branched from the output of the inverter 103 and taken out to the output terminal. The current source shown in FIG. 5 is omitted.

可変抵抗部２００は、図５に示す従来の負荷容量部６０に相当し、ここでは容量素子２０１と可変抵抗素子２０２を直列接続した構成を示す。なお、可変抵抗素子２０２は、図５に示すスイッチングトランジスタであるＭＯＳＦＥＴのソース・ドレイン間抵抗を用いることができる。当該スイッチングトランジスタを制御電圧発生部３００から入力する制御電圧により制御することにより、可変抵抗素子２０２の抵抗値が制御される。   The variable resistance unit 200 corresponds to the conventional load capacitance unit 60 shown in FIG. 5, and here shows a configuration in which a capacitive element 201 and a variable resistive element 202 are connected in series. Note that the variable resistance element 202 can use the source-drain resistance of a MOSFET which is a switching transistor shown in FIG. By controlling the switching transistor with a control voltage input from the control voltage generator 300, the resistance value of the variable resistance element 202 is controlled.

制御電圧発生部３００は、図５に示す従来の制御電圧発生部１０を改良したものである。電源端子と接地端子との間にダイオード素子３０１と容量素子３０２を直列接続し、容量素子３０２に初期化スイッチ３０３を並列接続した構成であり、ダイオード素子３０１と容量素子３０２との間から可変抵抗部２００の可変抵抗素子２０２を制御する制御電圧を出力する。なお、ダイオード素子３０１は、図５に示す従来の制御電圧発生部１０のダイオード接続トランジスタと同等である。また、初期化スイッチ３０３をスイッチングトランジスタで構成する場合、その寄生容量を容量素子３０２として利用し、容量素子３０２を省略した構成としてもよい。   The control voltage generator 300 is an improvement of the conventional control voltage generator 10 shown in FIG. A diode element 301 and a capacitor element 302 are connected in series between a power supply terminal and a ground terminal, and an initialization switch 303 is connected in parallel to the capacitor element 302. A variable resistance is provided between the diode element 301 and the capacitor element 302. A control voltage for controlling the variable resistance element 202 of the unit 200 is output. The diode element 301 is equivalent to the diode-connected transistor of the conventional control voltage generator 10 shown in FIG. In the case where the initialization switch 303 is formed of a switching transistor, the parasitic capacitance may be used as the capacitor 302 and the capacitor 302 may be omitted.

本構成では、初期化信号がHigh状態で初期化スイッチ３０３がオンになる期間以外、すなわち初期化信号がLow 状態のときは直流電流が流れないので、電流供給が小さくかつ電圧変動が大きい電源電圧に対して、安定した発振周波数を得ることができる。以下、実施例１の発振回路において、電源電圧に応じて発振周波数が所定の範囲に安定化する動作について、図２を参照して説明する。   In this configuration, since the direct current does not flow except during the period when the initialization signal is in the high state and the initialization switch 303 is turned on, that is, when the initialization signal is in the low state, the power supply voltage with small current supply and large voltage fluctuation On the other hand, a stable oscillation frequency can be obtained. Hereinafter, an operation of stabilizing the oscillation frequency within a predetermined range in accordance with the power supply voltage in the oscillation circuit of the first embodiment will be described with reference to FIG.

初期化信号がLow 状態で、初期化スイッチ３０３がオフのとき、制御電圧発生部３００が出力する制御電圧は、電源電圧からダイオード素子３０１の閾値電圧だけ降下した電圧に設定され、電源電圧の変動に対応する制御電圧が可変抵抗部２００に出力される。しかし、このままでは、容量素子３０２に電荷が蓄積して電源電圧の変動に応じた制御電圧が得られなくなるので、定期的に初期化信号をHigh状態にすることにより初期化スイッチ３０３をオンとし、容量素子３０２を接地電位に接続して蓄積した電荷を放電する。このとき、制御電圧発生部３００から出力される制御電圧は接地電位となり、可変抵抗部２００は所定の抵抗値に設定され、発振部１００も所定の発振周波数に設定される。   When the initialization signal is in the low state and the initialization switch 303 is off, the control voltage output from the control voltage generator 300 is set to a voltage that is lowered from the power supply voltage by the threshold voltage of the diode element 301, and the power supply voltage varies. Is output to the variable resistance unit 200. However, in this state, charge is accumulated in the capacitive element 302 and a control voltage corresponding to the fluctuation of the power supply voltage cannot be obtained. Therefore, the initialization switch 303 is turned on by periodically setting the initialization signal to the high state, The accumulated charge is discharged by connecting the capacitive element 302 to the ground potential. At this time, the control voltage output from the control voltage generation unit 300 becomes the ground potential, the variable resistance unit 200 is set to a predetermined resistance value, and the oscillation unit 100 is also set to a predetermined oscillation frequency.

初期化信号がLow 状態になると初期化スイッチ３０３がオフとなり、制御電圧発生部３００の制御電圧は接地電位から、電源電圧からダイオード素子３０１の閾値電圧だけ降下した電圧になるまで上昇する。このとき、可変抵抗部２００の抵抗値は減少し、これに応じて発振部１００は電源電圧に対応する発振周波数まで低下する。このように、初期化信号を適切な間隔でHigh状態とすることにより、発振周波数を電源電圧の変動に応じた所定の範囲内に制御することができる。   When the initialization signal is in the low state, the initialization switch 303 is turned off, and the control voltage of the control voltage generator 300 increases from the ground potential until the voltage drops from the power supply voltage by the threshold voltage of the diode element 301. At this time, the resistance value of the variable resistance unit 200 decreases, and accordingly, the oscillation unit 100 decreases to an oscillation frequency corresponding to the power supply voltage. Thus, by setting the initialization signal to the high state at appropriate intervals, the oscillation frequency can be controlled within a predetermined range according to the fluctuation of the power supply voltage.

図３は、本発明の発振回路の実施例２の構成を示す。
図３において、実施例２の発振回路は、実施例１の発振部１００の出力端子の出力信号（発振信号）を、初期化信号として制御電圧発生部３００の初期化スイッチ３０３に入力し、制御電圧をリセットする構成である。これにより、発振部１００の出力信号の遷移のタイミングで、可変抵抗部２００の容量値が初期化され、発振周波数が所定の範囲内に制御される。本構成では、初期化信号を生成する回路が不要のため、回路面積および消費電力の低減が可能になる。 FIG. 3 shows a configuration of a second embodiment of the oscillation circuit of the present invention.
In FIG. 3, the oscillation circuit according to the second embodiment inputs an output signal (oscillation signal) from the output terminal of the oscillation unit 100 according to the first embodiment to the initialization switch 303 of the control voltage generation unit 300 as an initialization signal. In this configuration, the voltage is reset. Thereby, the capacitance value of the variable resistance unit 200 is initialized at the timing of transition of the output signal of the oscillation unit 100, and the oscillation frequency is controlled within a predetermined range. In this configuration, since a circuit for generating an initialization signal is not required, the circuit area and power consumption can be reduced.

図４は、本発明の発振回路の実施例３の構成を示す。
図４において、実施例３の発振回路は、実施例２の発振部１００の出力端子の出力信号（発振信号）を分周回路４００を介して分周し、その分周信号を初期化信号として制御電圧発生部３００の初期化スイッチ３０３に入力する構成である。これにより、単位時間当たりに初期化する回数を低減できるため、実施例２の構成に比べて消費電力の低減が可能である。 FIG. 4 shows the configuration of a third embodiment of the oscillation circuit of the present invention.
In FIG. 4, the oscillation circuit of the third embodiment divides the output signal (oscillation signal) of the output terminal of the oscillation unit 100 of the second embodiment through the frequency divider circuit 400, and uses the divided signal as an initialization signal. This is a configuration for inputting to the initialization switch 303 of the control voltage generator 300. As a result, the number of times of initialization per unit time can be reduced, so that power consumption can be reduced compared to the configuration of the second embodiment.

１００ 発振部
１０１ ＮＡＮＤ回路
１０２，１０３ インバータ
２００ 可変抵抗部
２０１ 容量素子
２０２ 可変抵抗素子
３００ 制御電圧発生部
３０１ ダイオード素子
３０２ 容量素子
３０３ 初期化スイッチ DESCRIPTION OF SYMBOLS 100 Oscillation part 101 NAND circuit 102,103 Inverter 200 Variable resistance part 201 Capacitance element 202 Variable resistance element 300 Control voltage generation part 301 Diode element 302 Capacitance element 303 Initialization switch

Claims (4)

電源電圧に応じて発振周波数が変化する発振部と、
前記発振部に接続される抵抗値を可変させて前記発振周波数を制御する可変抵抗部と、 前記電源電圧と接地電位との間にダイオード素子と容量素子を直列に接続し、ダイオード素子と容量素子との間から前記電源電圧に応じた制御電圧を取り出す構成であり、さらに容量素子に並列に初期化スイッチを接続し、任意または所定のタイミングで入力する初期化信号により初期化スイッチをオンとして容量素子の電荷を放電し、初期化スイッチオフ時に前記電源電圧に応じた制御電圧を出力できる状態とした後に前記初期化スイッチをオフとする初期化手段を含む制御電圧発生部と
を備え、前記初期化スイッチのオフ期間に、前記電源電圧が低下すれば前記可変抵抗部の抵抗値を高くし、前記電源電圧が上昇すれば前記可変抵抗部の抵抗値を低くする制御電圧によって前記発振周波数を安定化する構成である
ことを特徴とする発振回路。 An oscillation unit whose oscillation frequency changes according to the power supply voltage;
A variable resistance unit for controlling the oscillation frequency by varying a resistance value connected to the oscillation unit, and a diode element and a capacitive element connected in series between the power supply voltage and the ground potential, and the diode element and the capacitive element as the a configuration for taking out the power supply voltage control voltage according to the on the initialization switch the initialization signal further connects the initialization switch in parallel with the capacitive element, to enter any or a predetermined timing from between the and discharging the electric charge of the capacitor, and a control voltage generator comprising an initialization means for turning off the initializing switch after a state in which a control voltage can be output in accordance with the power supply voltage during initialization switch off
The provided, in the OFF period of the previous SL initialization switch, control the front Symbol supply voltage to increase the resistance value of the variable resistance portion when lowered, the power supply voltage is low the resistance value of the variable resistor unit if elevated an oscillation circuit which is a configuration to stabilize the oscillation frequency by a voltage. 請求項１に記載の発振回路において、
前記並列接続の初期化スイッチと容量素子は、初期化信号によりオンオフするスイッチングトランジスタとその寄生容量である
ことを特徴とする発振回路。 The oscillation circuit according to claim 1,
The oscillation circuit, wherein the parallel-connected initialization switch and the capacitive element are a switching transistor that is turned on and off by an initialization signal and a parasitic capacitance thereof. 請求項１に記載の発振回路において、
前記初期化手段は、前記発振部の出力信号を前記初期化信号として前記制御電圧発生部の初期化スイッチに入力する構成である
ことを特徴とする発振回路。 The oscillation circuit according to claim 1,
The initialization circuit is configured to input the output signal of the oscillation unit to the initialization switch of the control voltage generation unit as the initialization signal. 請求項１に記載の発振回路において、
前記初期化手段は、前記発振部の出力信号の分周信号を前記初期化信号として前記制御電圧発生部の初期化スイッチに入力する構成である
ことを特徴とする発振回路。 The oscillation circuit according to claim 1,
The oscillation circuit characterized in that the initialization means is configured to input a frequency-divided signal of the output signal of the oscillation unit as the initialization signal to an initialization switch of the control voltage generation unit.
JP2011278523A 2011-12-20 2011-12-20 Oscillator circuit Expired - Fee Related JP5738750B2 (en)

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