JP5728651B2 - 三次元集積回路、プロセッサ、半導体チップおよび三次元集積回路の製造方法 - Google Patents
三次元集積回路、プロセッサ、半導体チップおよび三次元集積回路の製造方法 Download PDFInfo
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Description
ここでは、本発明に係る一つの実施形態として、三次元集積回路1について説明する。
<1−1.概要>
先ず、本願発明者が三次元集積回路1を得るに至った経緯について説明する。
<1−2.積層構造>
図1は、三次元集積回路1の一部断面を模式的に示す図である。三次元集積回路1は、半導体チップ10を2個積層して構成される。
<1−3.配線パターン>
ここでは、図2を用いて、配線パターンについて説明する。配線パターンとは、半導体チップ10の配線層14に形成される電源用導電体領域およびグランド用導電体領域の配置および各種のビアの配置である。
<1−4.製造方法>
ここでは、三次元集積回路1の製造方法について説明する。
<1−5.効果>
以上説明したように、三次元集積回路1は、新たな部材や工程を追加することなく回路内部にデカップリングコンデンサを形成することができる。
<2.その他の変形例>
以上、本発明に係る三次元集積回路の実施形態を説明したが、例示した三次元集積回路1を以下のように変形することも可能であり、本発明が上述の実施形態で示した三次元集積回路1に限られないのは勿論である。
<補足>
以下、更に本発明の一態様しての三次元集積回路の構成およびその変形例と効果について説明する。
10、10a、10b、10c、10d、20 半導体チップ
11 トランジスタ層
12 多層配線層
13 絶縁層
14、14b、14c、14d 配線層
70 基板
80 インターポーザ
101 トランジスタ
102 配線
103 電源用導電体領域
104 グランド用導電体領域
105 層間絶縁膜
106 グランド用ビア
107 電源用ビア
108 送信用ビア
109 受信用ビア
111 プログラマブルビア(データ用ビア)
401 トライステートバッファ(スリーステートバッファ)
402 クロスバスイッチ回路
403 トライステートバッファ制御回路
404 ストリーム制御回路
405 画像伸張処理回路
406 画像出力処理回路
Claims (12)
- 第一の半導体チップおよび第二の半導体チップを積層して成る三次元集積回路であって、
前記第一の半導体チップおよび前記第二の半導体チップは、
負荷と複数の配線層とが積層されて構成され、
前記第一の半導体チップおよび前記第二の半導体チップの少なくとも一方は、チップ間の接合面を絶縁するための絶縁層を含み、
前記第一の半導体チップの全配線層のうち前記接合面に最も近い配線層における電源用導電体領域およびグランド用導電体領域の配置と、前記第二の半導体チップの全配線層のうち前記接合面に最も近い配線層における電源用導電体領域およびグランド用導電体領域の配置とが同一であり、
前記第一の半導体チップの前記接合面に最も近い配線層の電源用導電体領域の少なくとも一部が、前記絶縁層を介して、前記第二の半導体チップの前記接合面に最も近い配線層のグランド用導電体領域の少なくとも一部と対向する
ことを特徴とする三次元集積回路。 - 前記第一の半導体チップと前記第二の半導体チップとは、同一種類の半導体チップであり、共に、前記絶縁層を含む
ことを特徴とする請求項1に記載の三次元集積回路。 - 前記第一の半導体チップおよび前記第二の半導体チップの前記接合面に最も近い配線層には、前記接合面の中心線を対称軸として、電源用導電体領域とグランド用導電体領域とが互いに線対称に配置されている
ことを特徴とする請求項2に記載の三次元集積回路。 - 前記三次元集積回路は、
前記第一の半導体チップの前記絶縁層の全面と前記第二の半導体チップの前記絶縁層の全面とが接合されて構成された略直方体形状であり、
前記第一の半導体チップおよび前記第二の半導体チップの前記接合面に最も近い配線層には、前記配線層の中心線を前記対称軸として、電源用導電体領域とグランド用導電体領域とが互いに線対称に配置されている
ことを特徴とする請求項3に記載の三次元集積回路。 - 前記第一の半導体チップおよび前記第二の半導体チップは、前記絶縁層を貫通して相互に電源用導電体領域およびグランド用導電体領域を導通するための複数の電源用ビアおよび複数のグランド用ビアを含み、
前記複数の電源用ビアは、前記中心線を対称軸として線対称に配置されており、
前記複数のグランド用ビアは、前記中心線を対称軸として線対称に配置されている
ことを特徴とする請求項4に記載の三次元集積回路。 - 前記第一の半導体チップおよび前記第二の半導体チップは、前記絶縁層を貫通して相互にデータを送受信するための送信用ビアおよび受信用ビアを含み、
前記送信用ビアおよび前記受信用ビアは、前記中心線を対称軸として互いに線対称に配置されている
ことを特徴とする請求項4に記載の三次元集積回路。 - 前記第一の半導体チップおよび前記第二の半導体チップの前記接合面に最も近い配線層には、前記接合面の対角線を対称軸として、電源用導電体領域とグランド用導電体領域とが互いに線対称に配置されている
ことを特徴とする請求項2に記載の三次元集積回路。 - 前記第一の半導体チップに含まれる前記負荷と前記第二の半導体チップに含まれる前記負荷とは、所定機能を実現するために複数のトランジスタを含む同一構造のトランジスタ層である
ことを特徴とする請求項1に記載の三次元集積回路。 - 前記第一の半導体チップおよび前記第二の半導体チップの前記絶縁層は、高誘電体膜(High−k材料膜)である
ことを特徴とする請求項1に記載の三次元集積回路。 - 請求項1に記載の三次元集積回路で構成されたプロセッサ。
- 三次元集積回路の製造方法であって、
負荷と複数の配線層とを積層し、全配線層のうち他チップとの接合面に最も近い配線層における電源用導電体領域およびグランド用導電体領域の配置が同一である第一の半導体チップおよび第二の半導体チップを製造する第一ステップと、
前記第一の半導体チップの前記接合面に最も近い配線層の電源用導電体領域の少なくとも一部が、前記第二の半導体チップの前記接合面に最も近い配線層のグランド用導電体領域の少なくとも一部と対向するように、前記第一の半導体チップと前記第二の半導体チップとを貼り合わせる第二ステップとを含み、
前記第一ステップでは、さらに、前記第一の半導体チップまたは前記第二の半導体チップの少なくとも一方に、前記接合面を絶縁するための絶縁層を積層する
ことを特徴とする三次元集積回路の製造方法。 - 前記第一ステップでは、
共に前記絶縁層を含む同一種類の前記第一の半導体チップと第二の半導体チップとを製造する
ことを特徴とする請求項11に記載の三次元集積回路の製造方法。
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