JP5692780B2 - マルチコア型誤り訂正処理システムおよび誤り訂正処理装置 - Google Patents
マルチコア型誤り訂正処理システムおよび誤り訂正処理装置 Download PDFInfo
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Description
図1を参照すると、本発明の第1の実施形態によるマルチコア型誤り訂正処理装置は、複数のメモリバンク部10a、10b、10cと、インタコネクト部11と、複数の誤り訂正処理部12a、12b、12cとから構成されている。図1はメモリバンク部、誤り訂正処理部が3個の場合を示しているが、説明を簡素化するためであり、3個に限定されるものでないことは言うまでも無い。これは、後述される実施形態においても同様である。複数のメモリバンク部10a〜10cは処理対象データ(入力データと呼ぶ)や演算途中のデータ、結果を格納するために使用される。インタコネクト部(データ列変換手段)11は、主にターボ復号で使用されるクロスバ部11aと、LDPC復号処理時に使用されるバレルシフタ部11bとグループ構成、動作等を制御するインタコネクト制御部11cを含む。インタコネクト部11は、メモリバンク部の他に誤り訂正処理部と接続している。誤り訂正処理部12a〜12cは誤り訂正処理を行う。複数の誤り訂正処理部12a〜12cはインタコネクト部11と接続している。誤り訂正処理部12a、12b、12cはそれぞれ、受け取った入力データを実際に処理する誤り訂正演算部13a、13b、13cと、誤り訂正演算部13a、13b、13cの制御やメモリバンク部10a、10b、10cに対するメモリアドレス、インタコネクト部11に必要なインタコネクトパラメータを生成する誤り訂正処理制御部15a、15b、15cと、外部IF(Interface)(外部入力手段)16から受け取る誤り訂正処理部12a、12b、12やインタコネクト部11をどのようなグループに構成するかを示した構成パラメータを保持するコンフィグデータ保持部(外部パラメータ格納手段)14a、14b、14cを含む。
次に、本発明の第2の実施形態によるマルチコア型誤り訂正処理装置について図面を参照して詳細に説明する。
次に、本発明の第3の実施形態について図面を参照して詳細に説明する。第3の実施形態は第1の実施形態の変形である。第2の実施形態と第1の実施形態との違いは以下の通りである。第1の実施形態ではインタコネクト部11内部のインタコネクト制御部11cへの入力が、誤り訂正処理制御部15a、15b、15cとコンフィグデータ保持部14a、14b、14cの2方からであったのに対し、第3の実施形態では、誤り訂正処理制御部35a、35b、35cからのみとなっている点である。
次に、本発明の第4の実施形態について図面を参照して詳細に説明する。第4の実施形態は第1の実施形態の変形である。第4の実施形態と第1の実施形態との違いは以下の通りである。第4の実施形態におけるマルチコア型誤り訂正装置では、第1の実施形態におけるクロスバ部11aが省略されている。すなわち、第4の実施形態による誤り訂正装置は、インタコネクト部41がバレルシフタ部41bとインタコネクト制御部41cのみとなっている。動作は第1の実施形態と同様である。第4の実施形態では、LDPC符号化に最適化された誤り訂正処理システムとすることができ、回路規模をより削減できる効果がある。
11、21、31、41、51 インタコネクト部
11a、21a、31a、51a クロスバ部
11b、21b、31b、41b、51b、61 バレルシフタ部
11c、21c、31c、41c、51c インタコネクト制御部
12a〜12c、22a〜22c、32a〜32c、42a〜42c、52a〜52c 誤り訂正処理部
13a〜13c、23a〜23c、33a〜33c、43a〜43c、53a〜53c 誤り訂正演算部
14a〜14c、24a〜24c、34a〜34c、44a〜44c コンフィグデータ保持部
15a〜15c、25a〜25c、35a〜35c、45a〜45c、55a〜55c 誤り訂正処理制御部
16、26、36、46、 外部IF
Claims (5)
- データ列を格納する複数のデータ列格納部と、
外部入力部から入力される情報に基づいて制御情報を出力する複数の誤り訂正処理手段と、
前記制御情報に基づいて前記データ列のデータ順を変換するデータ列変換手段と、を備え、
前記複数の誤り訂正処理手段は、前記制御情報に基づいて前記データ列変換手段から出力される前記データ列に所定の誤り訂正処理を行い、
前記制御情報は、前記データ列変換手段が行うデータ列変換を制御する情報と、前記データ列変換手段が前記データ列変換を行うためのグループ構成に関する情報と、を含み、
前記データ列変換手段は、前記制御情報に基づいて内部のグループ構成を変更するとともに、シフト処理に基づくローテーション動作を含むバレルシフタ動作によるデータ列変換を行い、
前記バレルシフタ動作は、前記グループ構成に関する情報に基づいて、出力すべき前記複数の誤り訂正処理手段のグループをまとめて指示するか、又は、前記複数の誤り訂正処理手段を個別に指示することを特徴とするマルチコア型誤り訂正処理システム。 - 請求項1に記載のマルチコア型誤り訂正処理システムであって、
前記データ列変換手段は、
前記バレルシフタ動作を実行するバレルシフタと、
前記複数のデータ列格納部と前記バレルシフタとの間に設けられ、前記制御情報に基づいて前記複数のデータ列格納部から出力される前記データ列を前記バレルシフタに出力するクロスバーと、を備えることを特徴とするマルチコア型誤り訂正処理システム。 - データ列を格納する複数のメモリバンク部と、
外部インタフェースから入力される情報に基づいて制御情報を出力する複数の誤り訂正処理部と、
前記制御情報に基づいて前記データ列のデータ順を変換するインタコネクト部と、を備え、
前記複数の誤り訂正処理部は、前記制御情報に基づいて前記インタコネクト部から出力される前記データ列に所定の誤り訂正処理を行い、
前記制御情報は、前記インタコネクト部が行うデータ列変換を制御する情報と、前記インタコネクト部が前記データ列変換を行うためのグループ構成に関する情報と、を含み、
前記インタコネクト部は、前記制御情報に基づいて内部のグループ構成を変更するとともに、シフト処理に基づくローテーション動作を含むバレルシフタ動作によるデータ列変換を行い、
前記バレルシフタ動作は、前記グループ構成に関する情報に基づいて、出力すべき前記複数の誤り訂正処理部のグループをまとめて指示するか、又は、前記複数の誤り訂正処理部を個別に指示することを特徴とするマルチコア型誤り訂正処理装置。 - 請求項3に記載のマルチコア型誤り訂正処理装置であって、
前記インタコネクト部は、
前記バレルシフタ動作を実行するバレルシフタと、
前記複数のメモリバンク部と前記バレルシフタとの間に設けられ、前記制御情報に基づいて前記複数のメモリバンク部から出力される前記データ列を前記バレルシフタに出力するクロスバーと、を備えることを特徴とするマルチコア型誤り訂正処理装置。 - データ列を格納する複数のデータ列格納部と、外部入力部から入力される情報に基づいて制御情報を出力する複数の誤り訂正処理手段と、前記制御情報に基づいて前記データ列のデータ順を変換するデータ列変換手段と、を備えるマルチコア型誤り訂正処理システムに使用されるマルチコア型誤り訂正処理方法であって、
前記複数の誤り訂正処理手段は、前記制御情報に基づいて前記データ列変換手段から出力される前記データ列に所定の誤り訂正処理を行い、
前記制御情報は、前記データ列変換手段が行うデータ列変換を制御する情報と、前記データ列変換手段が前記データ列変換を行うためのグループ構成に関する情報と、を含み、
前記データ列変換手段は、前記制御情報に基づいて内部のグループ構成を変更するとともに、シフト処理に基づくローテーション動作を含むバレルシフタ動作によるデータ列変換を行い、
前記バレルシフタ動作は、前記グループ構成に関する情報に基づいて、出力すべき前記複数の誤り訂正処理手段のグループをまとめて指示するか、又は、前記複数の誤り訂正処理手段を個別に指示することを特徴とするマルチコア型誤り訂正処理方法。
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PCT/JP2011/073281 WO2012046864A2 (en) | 2010-10-05 | 2011-10-04 | Multicore type error correction processing system and error correction processing apparatus |
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US9459956B2 (en) * | 2013-07-19 | 2016-10-04 | Seagate Technology Llc | Data decoder with trapping set flip bit mapper |
JP5768100B2 (ja) * | 2013-09-10 | 2015-08-26 | 株式会社東芝 | メモリ装置、サーバ装置、及びメモリ制御方法 |
US9317361B2 (en) | 2013-11-27 | 2016-04-19 | Seagate Technology Llc | Bit-line defect detection using unsatisfied parity code checks |
US11170294B2 (en) | 2016-01-07 | 2021-11-09 | Intel Corporation | Hardware accelerated machine learning |
US10817802B2 (en) | 2016-05-07 | 2020-10-27 | Intel Corporation | Apparatus for hardware accelerated machine learning |
US11120329B2 (en) | 2016-05-07 | 2021-09-14 | Intel Corporation | Multicast network and memory transfer optimizations for neural network hardware acceleration |
US11157037B1 (en) * | 2020-11-13 | 2021-10-26 | Marvell Asia Pte, Ltd. | Method and device for clock generation and synchronization for time interleaved networks |
US11750166B2 (en) | 2021-01-13 | 2023-09-05 | Marvell Asia Pte. Ltd. | Method and device for high bandwidth receiver for high baud-rate communications |
US11309904B1 (en) | 2021-02-24 | 2022-04-19 | Marvell Asia Pte Ltd. | Method and device for synchronization of large-scale systems with multiple time interleaving sub-systems |
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US5369652A (en) * | 1993-06-14 | 1994-11-29 | International Business Machines Corporation | Error detection and correction having one data format recordable on record media using a diverse number of concurrently recorded tracks |
US6330374B1 (en) * | 1998-11-13 | 2001-12-11 | Ricoh Company, Ltd. | Image manipulation for a digital copier which operates on a block basis |
US6304927B1 (en) * | 1998-11-13 | 2001-10-16 | Ricoh Company, Ltd. | Digital copier with scalable architecture |
JP2000196467A (ja) * | 1998-12-28 | 2000-07-14 | Nec Corp | 誤り訂正符号化器および誤り訂正復号器 |
KR100357126B1 (ko) * | 1999-07-30 | 2002-10-18 | 엘지전자 주식회사 | 메모리 주소 발생 장치 및 그를 이용한 무선 단말기 |
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US7127664B2 (en) | 2000-09-18 | 2006-10-24 | Lucent Technologies Inc. | Reconfigurable architecture for decoding telecommunications signals |
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CA2447204C (en) * | 2002-11-29 | 2010-03-23 | Memory Management Services Ltd. | Error correction scheme for memory |
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WO2008069231A1 (ja) * | 2006-12-07 | 2008-06-12 | Nec Corporation | 復号装置、復号方法 |
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JP4874312B2 (ja) * | 2007-09-20 | 2012-02-15 | 三菱電機株式会社 | ターボ符号復号装置、ターボ符号復号方法及び通信システム |
KR101504101B1 (ko) * | 2007-10-02 | 2015-03-19 | 삼성전자주식회사 | 적어도 두 개의 디코딩 매소드를 디코딩하기 위한 asip 아키텍처 |
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US8035537B2 (en) * | 2008-06-13 | 2011-10-11 | Lsi Corporation | Methods and apparatus for programmable decoding of a plurality of code types |
US8090896B2 (en) * | 2008-07-03 | 2012-01-03 | Nokia Corporation | Address generation for multiple access of memory |
US8281214B2 (en) * | 2008-10-17 | 2012-10-02 | Lsi Corporation | Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel |
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JP5293322B2 (ja) | 2009-03-24 | 2013-09-18 | 凸版印刷株式会社 | 有機elパネル及びその製造方法 |
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US20140040700A1 (en) | 2014-02-06 |
WO2012046864A2 (en) | 2012-04-12 |
JP2013179378A (ja) | 2013-09-09 |
US9250996B2 (en) | 2016-02-02 |
WO2012046864A3 (en) | 2012-08-30 |
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