JP5671220B2 - 半導体装置の製造方法 - Google Patents
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
- H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Description
図1は第1の実施形態に係る半導体装置の要部の構成を示す断面図である。図2及び図3は第1の実施形態に係る半導体装置の製造方法を説明するための一連の工程図であり、それぞれ半導体装置の要部の切断端面を示す。図4は配線層絶縁膜を構成する材料と層間絶縁膜(ビア層間絶縁膜)を構成する材料との好ましい組み合わせの例を示す図である。図5は第1の実施形態による効果を説明するための図である。
本実施形態に係る半導体装置の製造方法では、第1の配線層絶縁膜(例えば、第1の低誘電率膜4及び第1のキャップ絶縁膜5)を形成する工程と、第1の配線層絶縁膜に複数の第1の銅配線8を埋め込み形成する工程と、第1の銅配線8上及び第1の配線層絶縁膜上に層間絶縁膜(例えば、第2の低誘電率膜10)を形成する工程と、層間絶縁膜上に第2の配線層絶縁膜(例えば、第3の低誘電率膜11及び第2のキャップ絶縁膜12)を形成する工程と、第2の配線層絶縁膜に複数の第2の銅配線16を埋め込み形成する工程と、をこの順に行う。第1の配線層絶縁膜は、比誘電率が3.0よりも小さい絶縁膜材料により構成される第1の低誘電率膜(例えば、第1の低誘電率膜4)を含む。第2の配線層絶縁膜は、比誘電率が3.0よりも小さい絶縁膜材料により構成される第2の低誘電率膜(例えば、第3の低誘電率膜11)を含む。層間絶縁膜を形成する工程では、層間絶縁膜を第1及び第2の低誘電率膜よりも高強度に形成する。
以下、詳細に説明する。
図6は第2の実施形態に係る半導体装置の構成を示す断面図である。
2 第1の層間絶縁膜
3 溝エッチング停止層
4 第1の低誘電率膜
5 第1のキャップ絶縁膜
6 第1の配線形成用溝
7 第1のバリアメタル
8 第1の銅配線
9 ビアエッチング停止層
10 第2の低誘電率膜(層間絶縁膜)
11 第3の低誘電率膜(第2の低誘電率膜)
12 第2のキャップ絶縁膜
13 ビアホール
14 第2の配線形成用溝
15 第2のバリアメタル
16 第2の銅配線
17a 紫外線
17b 紫外線
18 有機膜
19 第2の配線溝形成用フォトレジスト
320 溝エッチング停止層
Claims (6)
- 第1の配線層絶縁膜を形成する工程と、
前記第1の配線層絶縁膜に複数の第1の銅配線を埋め込み形成する工程と、
前記第1の銅配線上及び前記第1の配線層絶縁膜上に層間絶縁膜を形成する工程と、
前記層間絶縁膜上に第2の配線層絶縁膜を形成する工程と、
前記第2の配線層絶縁膜に複数の第2の銅配線を埋め込み形成する工程と、
をこの順に行い、
前記第1の配線層絶縁膜は、比誘電率が3.0よりも小さい絶縁膜材料により構成される第1の低誘電率膜を含み、
前記第2の配線層絶縁膜は、比誘電率が3.0よりも小さい絶縁膜材料により構成される第2の低誘電率膜を含み、
前記層間絶縁膜を形成する前記工程では、前記層間絶縁膜を前記第1及び第2の低誘電率膜よりも高強度に形成し、
前記層間絶縁膜、前記第1の低誘電率膜、及び前記第2の低誘電率膜は、同じ材料からなり、それぞれ厚さ方向の全体がポーラス膜であり、
前記層間絶縁膜は、前記第1及び第2の低誘電率膜よりも空孔占有率が小さく、
前記層間絶縁膜を形成する前記工程は、前記層間絶縁膜に対し、熱のみによる焼成を行う工程を含み、
前記第2の配線層絶縁膜を形成する前記工程は、前記第2の低誘電率膜に対し、紫外線照射を伴う焼成を行うことにより、該第2の低誘電率膜を表裏に亘って改質する工程を含み、
前記第1の配線層絶縁膜を形成する前記工程は、前記第1の低誘電率膜に対し、紫外線照射を伴う焼成を行うことにより、該第1の低誘電率膜を表裏に亘って改質する工程を含む、半導体装置の製造方法。 - 前記第1及び第2の低誘電率膜の空孔の径を、前記層間絶縁膜の空孔の径よりも大きくする請求項1に記載の半導体装置の製造方法。
- 前記層間絶縁膜を、ポーラスSiOC、ポーラスSiOCH、及びポーラスSiOのうちの少なくとも何れか1つを含むものとして形成する請求項1又は2に記載の半導体装置の製造方法。
- 前記第1の配線層絶縁膜は、前記第1の低誘電率膜上に形成される第1のキャップ絶縁膜を更に含み、
前記第2の配線層絶縁膜は、前記第2の低誘電率膜上に形成される第2のキャップ絶縁膜を更に含み、
前記第2の銅配線を埋め込み形成する前記工程の後で、
前記第2の銅配線の構成材料のうち該第2の銅配線の形成領域からはみ出た余剰分をCMPにより除去する工程を行う、請求項1乃至3の何れか一項に記載の半導体装置の製造方法。 - 前記紫外線照射を伴う前記焼成において照射する紫外線の波長は200nm以上500nm以下である請求項1乃至4の何れか一項に記載の半導体装置の製造方法。
- 前記層間絶縁膜を形成する前記工程は、成膜原料としてDEMS(diethoxymethylsilane)又はDMOMS(dimethoxymethylsilane)を用いてポーラスSiOC膜を形成する工程を含む請求項1乃至5の何れか一項に記載の半導体装置の製造方法。
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JP2009194145A JP5671220B2 (ja) | 2009-08-25 | 2009-08-25 | 半導体装置の製造方法 |
US12/837,069 US8330276B2 (en) | 2009-08-25 | 2010-07-15 | Semiconductor device and method for manufacturing the same |
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US8951907B2 (en) * | 2010-12-14 | 2015-02-10 | GlobalFoundries, Inc. | Semiconductor devices having through-contacts and related fabrication methods |
JP5925611B2 (ja) | 2012-06-21 | 2016-05-25 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US9136221B2 (en) * | 2012-09-28 | 2015-09-15 | Intel Corporation | Methods of providing dielectric to conductor adhesion in package structures |
US9536832B1 (en) * | 2015-12-30 | 2017-01-03 | International Business Machines Corporation | Junctionless back end of the line via contact |
US11069526B2 (en) * | 2018-06-27 | 2021-07-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Using a self-assembly layer to facilitate selective formation of an etching stop layer |
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US6583048B2 (en) * | 2001-01-17 | 2003-06-24 | Air Products And Chemicals, Inc. | Organosilicon precursors for interlayer dielectric films with low dielectric constants |
JP3762732B2 (ja) * | 2002-09-27 | 2006-04-05 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP2004292636A (ja) * | 2003-03-27 | 2004-10-21 | Shin Etsu Chem Co Ltd | 多孔質膜形成用組成物、多孔質膜の製造方法、多孔質膜、層間絶縁膜、及び半導体装置 |
WO2004105123A1 (ja) * | 2003-05-21 | 2004-12-02 | Fujitsu Limited | 半導体装置 |
JP4408816B2 (ja) | 2005-01-07 | 2010-02-03 | 富士通株式会社 | 半導体装置の製造方法 |
US7265437B2 (en) * | 2005-03-08 | 2007-09-04 | International Business Machines Corporation | Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties |
JP2006319116A (ja) * | 2005-05-12 | 2006-11-24 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP4523535B2 (ja) * | 2005-08-30 | 2010-08-11 | 富士通株式会社 | 半導体装置の製造方法 |
JP5060037B2 (ja) * | 2005-10-07 | 2012-10-31 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2007214403A (ja) | 2006-02-10 | 2007-08-23 | Renesas Technology Corp | 半導体装置の製造方法 |
JP4788415B2 (ja) * | 2006-03-15 | 2011-10-05 | ソニー株式会社 | 半導体装置の製造方法 |
JP2009094123A (ja) * | 2007-10-04 | 2009-04-30 | Fujitsu Microelectronics Ltd | 半導体装置の製造方法 |
JP2009094380A (ja) * | 2007-10-11 | 2009-04-30 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2009188250A (ja) * | 2008-02-07 | 2009-08-20 | Panasonic Corp | 半導体装置及びその製造方法 |
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