JP5660462B2 - Printed wiring board - Google Patents

Printed wiring board Download PDF

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Publication number
JP5660462B2
JP5660462B2 JP2011108413A JP2011108413A JP5660462B2 JP 5660462 B2 JP5660462 B2 JP 5660462B2 JP 2011108413 A JP2011108413 A JP 2011108413A JP 2011108413 A JP2011108413 A JP 2011108413A JP 5660462 B2 JP5660462 B2 JP 5660462B2
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layer
conductor
resin insulation
conductor layer
insulation layer
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JP2012238804A (en
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礼雄 仁木
礼雄 仁木
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Ibiden Co Ltd
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Ibiden Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

本発明は、電子部品を内蔵するプリント配線板に関する。 The present invention relates to a printed wiring board incorporating an electronic component.

特許文献１は、薄型化のため半導体素子を絶縁層に埋め込むことを開示している。該特許文献１は、片面に外部端子を備えるプリント配線板と、両面に外部端子を備えるプリント配線板を開示している。 Patent Document 1 discloses embedding a semiconductor element in an insulating layer for thinning. The patent document 1 discloses a printed wiring board having an external terminal on one side and a printed wiring board having an external terminal on both sides.

特開２００６−２２２１６４号公報JP 2006-222164 A

しかしながら、特許文献１のプリント配線板に、更に絶縁層と導体層が積層されると、電子部品の電極と絶縁層上の導体層との間での接続信頼性が低くなると考えられる。 However, if an insulating layer and a conductor layer are further laminated on the printed wiring board of Patent Document 1, it is considered that the connection reliability between the electrode of the electronic component and the conductor layer on the insulating layer is lowered.

特許文献１のプリント配線板は、薄型化のため補強用のコア基板を有していない上に、電子部品を絶縁層に内蔵している。このため、電子部品を内蔵する絶縁層の上に別の絶縁層が積層されると、電子部品を内蔵している層と、別の絶縁層とで、ヒートサイクル下において収縮量が大きく異なると考えられる。その結果、プリント配線板の反り量が大きくなると考えられる。そのため、電子部品の電極と絶縁層上の導体層との間の接続信頼性が低くなると考えられる。 The printed wiring board disclosed in Patent Document 1 does not have a reinforcing core substrate for thinning, and incorporates electronic components in an insulating layer. For this reason, if another insulating layer is laminated on the insulating layer containing the electronic component, the amount of shrinkage differs greatly under the heat cycle between the layer containing the electronic component and the other insulating layer. Conceivable. As a result, it is considered that the amount of warpage of the printed wiring board increases. Therefore, it is considered that the connection reliability between the electrode of the electronic component and the conductor layer on the insulating layer is lowered.

本発明の目的は、電子部品を内蔵し薄く接続信頼性の高いプリント配線板を提供することである。 An object of the present invention is to provide a thin printed wiring board with built-in electronic components and high connection reliability.

本発明に係るプリント配線板は、第１導体層と、第１面と該第１面とは反対側の第２面とを有し、該第２面が前記第１導体層と対向するように前記第１導体層上に積層されている第１樹脂絶縁層と、前記第１樹脂絶縁層内に収容されていて電極を有する電子部品と、前記第１樹脂絶縁層の第１面に形成されている第２導体層と、前記第１樹脂絶縁層を貫通し、前記第１導体層と前記第２導体層とを接続している第１ビア導体と、前記第１樹脂絶縁層に形成されていて前記電子部品の電極と前記第２導体層とを接続している接続ビア導体と、第１面と該第１面とは反対側の第２面とを有し、該第２面が前記第１樹脂絶縁層の第１面と対向するように前記第２導体層と前記第１樹脂絶縁層上に積層されている第２樹脂絶縁層と、前記第２樹脂絶縁層の第１面上に形成されている第３導体層と、前記第２樹脂絶縁層を貫通し、前記第２導体層と前記第３導体層とを接続している第２ビア導体と、を有する。そして、前記第２導体層の厚みは前記第３導体層の厚みより厚い。 The printed wiring board according to the present invention has a first conductor layer, a first surface, and a second surface opposite to the first surface, and the second surface faces the first conductor layer. Formed on the first surface of the first resin insulation layer, the first resin insulation layer laminated on the first conductor layer, the electronic component housed in the first resin insulation layer and having an electrode. Formed in the first resin insulation layer, the first via conductor passing through the first resin insulation layer, and connecting the first conductor layer and the second conductor layer. A connection via conductor connecting the electrode of the electronic component and the second conductor layer, a first surface and a second surface opposite to the first surface, the second surface , The second resin insulation layer laminated on the first resin insulation layer, the second resin insulation layer so as to face the first surface of the first resin insulation layer, and the second resin insulation A third conductor layer formed on the first surface, and a second via conductor penetrating the second resin insulation layer and connecting the second conductor layer and the third conductor layer, Have. The second conductor layer is thicker than the third conductor layer.

本発明の実施形態に係るプリント配線板の製造工程図。The manufacturing process figure of the printed wiring board which concerns on embodiment of this invention. 実施形態のプリント配線板の製造工程図。The manufacturing process figure of the printed wiring board of embodiment. 実施形態のプリント配線板の製造工程図。The manufacturing process figure of the printed wiring board of embodiment. 実施形態のプリント配線板の製造工程図。The manufacturing process figure of the printed wiring board of embodiment. 実施形態のプリント配線板の製造工程図。The manufacturing process figure of the printed wiring board of embodiment. 実施形態のプリント配線板の製造工程図。The manufacturing process figure of the printed wiring board of embodiment. 本発明の実施形態に係るプリント配線板の断面図。Sectional drawing of the printed wiring board which concerns on embodiment of this invention. 図７のプリント配線板の応用例。Application example of the printed wiring board of FIG. 本発明の実施形態の改変例に係るプリント配線板の断面図。Sectional drawing of the printed wiring board which concerns on the modification of embodiment of this invention. 本発明の実施形態の別改変例に係るプリント配線板の断面図。Sectional drawing of the printed wiring board which concerns on another modification of embodiment of this invention. ビア導体用開口の径を示す平面図。The top view which shows the diameter of the opening for via conductors.

[実施形態１]
図７、８を参照して本発明の実施形態１に係るプリント配線板が以下に説明されている。
図７は実施形態１のプリント配線板を示し、図８は、実施形態１のプリント配線板にパッケージ基板１００が搭載されている。そして、実施形態１のプリント配線板はマザーボードに搭載されている。 [Embodiment 1]
A printed wiring board according to Embodiment 1 of the present invention will be described below with reference to FIGS.
FIG. 7 shows a printed wiring board according to the first embodiment, and FIG. 8 shows a package substrate 100 mounted on the printed wiring board according to the first embodiment. The printed wiring board of Embodiment 1 is mounted on the motherboard.

図７に示されるように、半田バンプを有するプリント配線板１０００は、第１導体層４２と、該第１導体層上の第１樹脂絶縁層５０と、該第１樹脂絶縁層上の第２導体層５８と、該第１樹脂絶縁層及び第２導体層上の第２樹脂絶縁層６０と、第２樹脂絶縁層上の第３導体層６８とを有する。
第１導体層は外部端子４２を含んでいて、図７では、この外部端子に半田バンプ８６Ｄが形成されている。第１樹脂絶縁層にＩＣチップなどの電子部品９０が内蔵されている。電子部品は電極９２を有している。第１樹脂絶縁層５０と第２樹脂絶縁層６０は第１面と第１面とは反対側の第２面を有している。第１樹脂絶縁層の第２面は第１導体層と対向していて、第１樹脂絶縁層の第１面に複数の導体回路やビアランドを含む第２導体層５８が形成されている。 As shown in FIG. 7, the printed wiring board 1000 having solder bumps includes a first conductor layer 42, a first resin insulating layer 50 on the first conductor layer, and a second conductor on the first resin insulating layer. It has a conductor layer 58, a second resin insulation layer 60 on the first resin insulation layer and the second conductor layer, and a third conductor layer 68 on the second resin insulation layer.
The first conductor layer includes an external terminal 42. In FIG. 7, solder bumps 86D are formed on the external terminal. An electronic component 90 such as an IC chip is built in the first resin insulating layer. The electronic component has an electrode 92. The first resin insulation layer 50 and the second resin insulation layer 60 have a first surface and a second surface opposite to the first surface. The second surface of the first resin insulation layer faces the first conductor layer, and a second conductor layer 58 including a plurality of conductor circuits and via lands is formed on the first surface of the first resin insulation layer.

第１導体層と第２導体層は第１樹脂絶縁層を貫通する第１ビア導体５９Ａで接続されている。また、第２導体層と電子部品の電極は第１樹脂絶縁層を貫通する接続ビア導体５９Bで接続されている。第１樹脂絶縁層の第１面と第２導体層上に第２樹脂絶縁層が形成されている。第１樹脂絶縁層の第１面と第２樹脂絶縁層の第２面が対向している。
第２樹脂絶縁層の第１面上に第３導体層が形成されていて、第３導体層は複数の導体回路やビアランドを含んでいる。第２導体層と第３導体層は第２樹脂絶縁層を貫通している第２ビア導体６９で接続されている。第２樹脂絶縁層の第１面と第３導体層上にソルダーレジスト層８０が形成されている。ソルダーレジスト層は開口８０ａを有し、その開口８０ａにより露出している第２ビア導体や第３導体層上に半田バンプ８６Ｕが形成されている。 The first conductor layer and the second conductor layer are connected by a first via conductor 59A that penetrates the first resin insulating layer. The second conductor layer and the electrode of the electronic component are connected by a connection via conductor 59B that penetrates the first resin insulating layer. A second resin insulation layer is formed on the first surface of the first resin insulation layer and the second conductor layer. The first surface of the first resin insulation layer and the second surface of the second resin insulation layer are opposed to each other.
A third conductor layer is formed on the first surface of the second resin insulation layer, and the third conductor layer includes a plurality of conductor circuits and via lands. The second conductor layer and the third conductor layer are connected by a second via conductor 69 penetrating the second resin insulating layer. A solder resist layer 80 is formed on the first surface of the second resin insulation layer and the third conductor layer. The solder resist layer has an opening 80a, and a solder bump 86U is formed on the second via conductor or the third conductor layer exposed through the opening 80a.

実施形態１では、ＩＣチップ９０のバック面（背面）に銀ペーストなどからなるダイアタッチ４４が形成されている。ダイアタッチは必須でなく、ＩＣチップのバック面が外部に露出してもよい。ダイアタッチが露出することにより、さらに、放熱性が向上する In the first embodiment, a die attach 44 made of silver paste or the like is formed on the back surface (back surface) of the IC chip 90. Die attach is not essential, and the back surface of the IC chip may be exposed to the outside. Heat dissipation is further improved by exposing the die attach.

図８では、図７のプリント配線板が反転されている。プリント配線板１０００の半田バンプ８６Ｄにパッケージ基板１００のパッド１０２が接続されている。パッケージ基板１００にメモリー１０４が搭載されていて、ワイヤー１０６によりメモリーとパッケージ基板１００は接続されている。一方、プリント配線板１０００の半田バンプ８６Ｕを介して、プリント配線板はマザーボード２００のパッド２０２に接続されている。 In FIG. 8, the printed wiring board of FIG. 7 is inverted. The pads 102 of the package substrate 100 are connected to the solder bumps 86D of the printed wiring board 1000. A memory 104 is mounted on the package substrate 100, and the memory and the package substrate 100 are connected by a wire 106. On the other hand, the printed wiring board is connected to the pads 202 of the motherboard 200 via the solder bumps 86U of the printed wiring board 1000.

図７に示されているように、第１樹脂絶縁層５０には、ＩＣチップが内蔵されていて、第２樹脂絶縁層６０にはＩＣチップが内蔵されていない。このため、プリント配線板の温度が変化すると、第１樹脂絶縁層と第２樹脂絶縁層で伸縮量が異なると考えられる。また、硬化により第１樹脂絶縁層と第２樹脂絶縁層で収縮する量が異なると考えられる。そのため、プリント配線板１０に反りやうねりが発生しやすいと考えられる。しかしながら、実施形態１では、第２導体層の厚み（ｄ１）は第３導体層の厚み（ｄ２）より厚い。導体層は樹脂絶縁層より剛性に優れるので、第２導体層を厚くすることでプリント配線板の反りやうねりを防止できると考えられる。第３導体層の厚みは第２導体層より薄い。第２導体層と同様に第３導体層の厚みが厚いと、第３導体層に微細な配線を形成することが困難になる。そのため、２層の樹脂絶縁層で形成されるはずのプリント配線板が３層の樹脂絶縁層で形成される。その結果、硬化による収縮量が大きくなり、プリント配線板の反りやうねりが大きくなると考えられる。実施形態１では、第２導体層は電子部品を内蔵している第１樹脂絶縁層と電子部品を内蔵していない第２樹脂絶縁層の間に存在している。隣接する樹脂絶縁層間で伸縮量が比較されると、電子部品の有無により、第１樹脂絶縁層と第２樹脂絶縁層で温度変化による伸縮量の差や硬化による収縮量の差が最も大きいと考えられる。従って、第１樹脂絶縁層と第２樹脂絶縁層の界面に大きな応力が働くと考えられる。第１樹脂絶縁層と第２樹脂絶縁層の界面を起点としてプリント配線板に反りやうねりが発生すると考えられる。その反りやうねりを効果的に防止するため、実施形態１では、第１樹脂絶縁層と第２樹脂絶縁層の間に厚い導体層が形成されている。また、第１樹脂絶縁層と第２樹脂絶縁層の界面に掛かる応力を小さくするため、第３導体層の厚みは第２導体層の厚みより薄い。 As shown in FIG. 7, the first resin insulation layer 50 contains an IC chip, and the second resin insulation layer 60 does not contain an IC chip. For this reason, when the temperature of a printed wiring board changes, it is thought that the amount of expansion and contraction differs between the first resin insulating layer and the second resin insulating layer. Further, it is considered that the amount of shrinkage differs between the first resin insulating layer and the second resin insulating layer due to curing. Therefore, it is considered that the printed wiring board 10 is likely to warp or swell. However, in Embodiment 1, the thickness (d1) of the second conductor layer is thicker than the thickness (d2) of the third conductor layer. Since the conductor layer is more rigid than the resin insulating layer, it is considered that warping and undulation of the printed wiring board can be prevented by increasing the thickness of the second conductor layer. The third conductor layer is thinner than the second conductor layer. If the third conductor layer is thick like the second conductor layer, it is difficult to form fine wiring on the third conductor layer. Therefore, a printed wiring board that should be formed of two resin insulating layers is formed of three resin insulating layers. As a result, it is considered that the amount of shrinkage due to curing increases, and warping and undulation of the printed wiring board increase. In the first embodiment, the second conductor layer is present between the first resin insulating layer containing the electronic component and the second resin insulating layer not containing the electronic component. When the expansion / contraction amount is compared between adjacent resin insulation layers, the difference in expansion / contraction amount due to temperature change and the difference in shrinkage amount due to curing between the first resin insulation layer and the second resin insulation layer is greatest depending on the presence or absence of electronic components Conceivable. Therefore, it is considered that a large stress acts on the interface between the first resin insulation layer and the second resin insulation layer. It is considered that the printed wiring board is warped or undulated starting from the interface between the first resin insulating layer and the second resin insulating layer. In order to effectively prevent the warpage and waviness, in Embodiment 1, a thick conductor layer is formed between the first resin insulating layer and the second resin insulating layer. The thickness of the third conductor layer is smaller than the thickness of the second conductor layer in order to reduce the stress applied to the interface between the first resin insulation layer and the second resin insulation layer.

また、反り量は、内蔵されている電子部品から離れるほど大きくなると考えられる。そのため、電子部品を内蔵することで発生する反りを所定の導体層で抑制するには、電子部品から遠い導体層ほど厚みを厚くする必要があると考えられる。しかしながら、実施形態１では、電子部品を内蔵している第１樹脂絶縁層上の第２導体層の厚みが、第３導体層の厚みよりも厚い。そのため、実施形態１のプリント配線板は反りやうねりを効率的に抑制できる。 Further, the warpage amount is considered to increase as the distance from the built-in electronic component increases. For this reason, in order to suppress the warpage generated by incorporating the electronic component with the predetermined conductor layer, it is considered that the conductor layer farther from the electronic component needs to be thicker. However, in Embodiment 1, the thickness of the second conductor layer on the first resin insulation layer containing the electronic component is thicker than the thickness of the third conductor layer. Therefore, the printed wiring board of Embodiment 1 can efficiently suppress warpage and undulation.

第２導体層５８の厚さ（ｄ１）／第３導体層６８の厚さ（ｄ２）は１．２〜５であることが望ましい。第２導体層５８の厚みｄ１は１０μｍから１２５μｍであり、第３導体層６８の厚みｄ２は７μｍから３０μｍである。 The thickness (d1) of the second conductor layer 58 / the thickness (d2) of the third conductor layer 68 is desirably 1.2 to 5. The thickness d1 of the second conductor layer 58 is 10 μm to 125 μm, and the thickness d2 of the third conductor layer 68 is 7 μm to 30 μm.

第１導体層４２の厚みｄ４は１０μｍから７５μｍである。第１導体層の厚みは第３導体層の厚み以上であって、第２導体層の厚み以下である。第２導体層５８の厚さ（ｄ１）／第１導体層６８の厚さ（ｄ４）は１〜３であって、第１導体層の厚み（ｄ４）／第３導体層の厚み（ｄ２）は１〜２であることが望ましい。プリント配線板の反りやうねりが小さくなる。もしくは、樹脂絶縁層の層数を減らすことができる。 The thickness d4 of the first conductor layer 42 is 10 μm to 75 μm. The thickness of the first conductor layer is not less than the thickness of the third conductor layer and not more than the thickness of the second conductor layer. The thickness (d1) of the second conductor layer 58 / the thickness (d4) of the first conductor layer 68 is 1 to 3, and the thickness of the first conductor layer (d4) / the thickness of the third conductor layer (d2). Is preferably 1-2. The warpage and undulation of the printed wiring board are reduced. Alternatively, the number of resin insulating layers can be reduced.

第１導体層の厚みは第３導体層の厚みより厚く、第２導体層の厚みより薄いことが好ましい。第１導体層の厚み／第３導体層の厚みは１．１〜１．５であることが望ましく、第２導体層の厚み／第１導体層の厚みは１．５〜３であることが望ましい。この範囲であると、第１導体層と第３導体層に微細な導体回路を形成することができる。そのため、樹脂絶縁層の層数が少なくなるので、プリント配線板の反り量が小さくなる。第２導体層の厚みが必要以上に厚くならない。効果的にプリント配線板の反りが低減される。そのため、第２導体層にも信号線を形成することができる。樹脂絶縁層の層数が少なくなる。従って、反り量が小さく薄いプリント配線板が得られる。 The first conductor layer is preferably thicker than the third conductor layer and thinner than the second conductor layer. The thickness of the first conductor layer / the thickness of the third conductor layer is preferably 1.1 to 1.5, and the thickness of the second conductor layer / the thickness of the first conductor layer is 1.5 to 3. desirable. Within this range, fine conductor circuits can be formed in the first conductor layer and the third conductor layer. Therefore, since the number of resin insulation layers is reduced, the amount of warpage of the printed wiring board is reduced. The thickness of the second conductor layer does not become larger than necessary. The warpage of the printed wiring board is effectively reduced. Therefore, a signal line can be formed also in the second conductor layer. The number of resin insulation layers is reduced. Therefore, a thin printed wiring board with a small amount of warpage can be obtained.

第１導体層の厚み（ｄ４）は第２導体層の厚み（ｄ１）と同等であって、第３導体層の厚み（ｄ２）より厚いことが好ましい。第１導体層の厚み／第３導体層の厚みは１．２〜３であることが望ましい。第１樹脂絶縁層の両面に厚みの厚い第２導体層５８、第１導体層４２を設けることで、第１樹脂絶縁層の反りが抑えられる。 The thickness (d4) of the first conductor layer is equivalent to the thickness (d1) of the second conductor layer, and is preferably thicker than the thickness (d2) of the third conductor layer. The thickness of the first conductor layer / the thickness of the third conductor layer is preferably 1.2-3. By providing the thick second conductor layer 58 and the first conductor layer 42 on both surfaces of the first resin insulation layer, warpage of the first resin insulation layer can be suppressed.

第１導体層４２は、他の基板や電子部品と接続するための外部端子を含む。第１導体層は第１樹脂絶縁層５０の第２面と同一レベルまたは第２面から凹んでいる。凹むことが望ましい。ＩＣチップの背面が第１樹脂絶縁層の第２面に向くようにＩＣチップが第１樹脂絶縁層の第２面側に内蔵されると、第２面側の第１樹脂絶縁層は第１面側の第１樹脂絶縁層よりＩＣチップの影響を受けると考えられる。しかしながら、実施形態１では、第１導体層４２が第１樹脂絶縁層５０の第２面から凹んでいて、第１樹脂絶縁層内に形成されているので、第２面側の第１樹脂絶縁層は第１導体層で補強されると考えられる。そのため、第１樹脂絶縁層にＩＣチップを埋め込むことで発生する応力は、第１導体層を第１樹脂絶縁層の第２面側に埋め込むことにより緩和されると考えられる。第１樹脂絶縁層にクラックが発生し難い。 The first conductor layer 42 includes external terminals for connecting to other substrates and electronic components. The first conductor layer is recessed at the same level as the second surface of the first resin insulation layer 50 or from the second surface. It is desirable to dent. When the IC chip is built in the second surface side of the first resin insulation layer so that the back surface of the IC chip faces the second surface of the first resin insulation layer, the first resin insulation layer on the second surface side is the first resin insulation layer. It is thought that the first resin insulation layer on the surface side is affected by the IC chip. However, in the first embodiment, since the first conductor layer 42 is recessed from the second surface of the first resin insulation layer 50 and is formed in the first resin insulation layer, the first resin insulation on the second surface side. The layer is believed to be reinforced with a first conductor layer. Therefore, it is considered that the stress generated by embedding the IC chip in the first resin insulation layer is alleviated by embedding the first conductor layer on the second surface side of the first resin insulation layer. Cracks are unlikely to occur in the first resin insulation layer.

第１樹脂絶縁層５０の厚み（ｆ１）は５５μｍから１９０μｍであり、電子部品９０の厚みより１５〜４０μｍ程度厚い。第１樹脂絶縁層は複数の樹脂絶縁層５０Ａ、５０Ｂで形成されてもよい（図１０）。図１０では、第１樹脂絶縁層は２層の樹脂絶縁層で形成されている。２層の樹脂絶縁層を第１ビア導体が貫通している。この場合、第１樹脂絶縁層は電子部品を内蔵している各樹脂絶縁層を含む。各樹脂絶縁層の厚みは略同じであることが好ましい。第２樹脂絶縁層６０の厚み（ｆ２）は２０μｍから５０μｍである。第２樹脂絶縁層の厚みは第１樹脂絶縁層の厚みより薄いことが好ましい。硬化による収縮が小さくなるので、プリント配線板の反り量やうねり量が小さくなる。 The thickness (f1) of the first resin insulating layer 50 is 55 μm to 190 μm, and is about 15 to 40 μm thicker than the thickness of the electronic component 90. The first resin insulation layer may be formed of a plurality of resin insulation layers 50A and 50B (FIG. 10). In FIG. 10, the first resin insulation layer is formed of two resin insulation layers. The first via conductor passes through the two resin insulating layers. In this case, the first resin insulation layer includes each resin insulation layer containing an electronic component. It is preferable that the thickness of each resin insulation layer is substantially the same. The thickness (f2) of the second resin insulation layer 60 is 20 μm to 50 μm. The thickness of the second resin insulation layer is preferably thinner than the thickness of the first resin insulation layer. Since shrinkage due to curing is reduced, the amount of warping and waviness of the printed wiring board is reduced.

第１ビア導体５９Ａのボトム径ｅ１は３０μｍから１２０μｍであり、トップ径ｅ２は３０μｍから２００μｍである。第２ビア導体６９のボトム径ｅ５は３０μｍから８０μｍであり、トップ径ｅ６は３０μｍから１００μｍである。接続ビア導体５９Ｂのボトム径ｅ３は３０μｍから８０μｍであり、トップ径ｅ４は３０μｍから１００μｍである。図７に示されているように、ボトム径は導体層やビア導体、電子部品の電極上のビア導体用開口の径であり、トップ径は樹脂絶縁層の第１面でのビア導体用開口の径である（図１１参照）。 The bottom diameter e1 of the first via conductor 59A is 30 μm to 120 μm, and the top diameter e2 is 30 μm to 200 μm. The bottom diameter e5 of the second via conductor 69 is 30 μm to 80 μm, and the top diameter e6 is 30 μm to 100 μm. The bottom diameter e3 of the connection via conductor 59B is 30 μm to 80 μm, and the top diameter e4 is 30 μm to 100 μm. As shown in FIG. 7, the bottom diameter is the diameter of the conductor layer, via conductor, and via conductor opening on the electrode of the electronic component, and the top diameter is the via conductor opening on the first surface of the resin insulating layer. (See FIG. 11).

第１ビア導体５９Ａのトップ径が、第２ビア導体６９のトップ径よりも大きいことが好ましい。電子部品を内蔵している第１樹脂絶縁層に占めるビア導体の体積が大きくなる。これにより、第１樹脂絶縁層の剛性が高くなるので、プリント配線板が反り難くなる。第１ビア導体のトップ径／第２ビア導体のトップ径は１．０５〜４であることが望ましい。 The top diameter of the first via conductor 59 </ b> A is preferably larger than the top diameter of the second via conductor 69. The volume of the via conductor in the first resin insulating layer containing the electronic component is increased. Thereby, since the rigidity of the 1st resin insulation layer becomes high, a printed wiring board becomes difficult to warp. The top diameter of the first via conductor / the top diameter of the second via conductor is desirably 1.05 to 4.

接続ビア導体５９Ｂのトップ径も第２導体のトップ径より大きいことが望ましい。接続ビア導体のトップ径／第２ビア導体のトップ径は１．０５〜３であることが望ましい。さらに、第１樹脂絶縁層の剛性が高くなる。また、第２樹脂絶縁層に小さなビア導体を形成することができる。従って、第２樹脂絶縁層に形成可能なビア導体の数が増える。また、第２導体層に形成されるビアランドが小さくなるので、樹脂絶縁層の層数が少なくなる。その結果、反り量が小さく薄いプリント配線板が得られる。接続ビア導体のトップ径は第１ビア導体のトップ径と同等もしくは第１ビア導体のトップ径より小さい。接続ビア導体のトップ径が第１ビア導体のトップ径より小さい場合、電極数の多いＩＣチップを内蔵することができる。 It is desirable that the top diameter of the connection via conductor 59B is also larger than the top diameter of the second conductor. The top diameter of the connection via conductor / the top diameter of the second via conductor is preferably 1.05 to 3. Furthermore, the rigidity of the first resin insulating layer is increased. In addition, a small via conductor can be formed in the second resin insulating layer. Therefore, the number of via conductors that can be formed in the second resin insulation layer increases. Moreover, since the via land formed in the second conductor layer is reduced, the number of resin insulating layers is reduced. As a result, a thin printed wiring board with a small amount of warpage can be obtained. The top diameter of the connection via conductor is equal to or smaller than the top diameter of the first via conductor. When the top diameter of the connection via conductor is smaller than the top diameter of the first via conductor, an IC chip having a large number of electrodes can be incorporated.

図１〜図８を参照し、実施形態１のプリント配線板の製造方法が以下に説明される。
厚さ０．２〜０．８ｍｍの両面銅張積層板３０と、厚さ５〜１００μｍの銅箔４０が準備される（図１（Ａ）。 With reference to FIGS. 1-8, the manufacturing method of the printed wiring board of Embodiment 1 is demonstrated below.
A double-sided copper clad laminate 30 having a thickness of 0.2 to 0.8 mm and a copper foil 40 having a thickness of 5 to 100 μm are prepared (FIG. 1A).

両面銅張積層板３０に銅箔４０が接着剤又は超音波接続により接合される（図１（Ｂ））。銅箔上に所定パターンのめっきレジストが形成され、めっきレジスト非形成部に電解めっきによりニッケル膜４２Ｎが形成される。ニッケル膜の厚さは５μｍである。ニッケル膜上に電解めっきで金膜４２Ａとニッケル膜４２０Ｎが形成される。ニッケル膜４２０Ｎ上に電解銅めっきで第１導体層４２が形成される。第１導体層の厚みは１０〜７５μｍである。めっきレジストが除去される（図１（Ｃ））。銅箔４０のＩＣチップ取り付け位置にＡｕ−Ｓｎペーストなどの導電性ペーストによりダイアタッチ４４が形成される（図１（Ｄ））。 The copper foil 40 is joined to the double-sided copper clad laminate 30 by an adhesive or ultrasonic connection (FIG. 1 (B)). A plating resist having a predetermined pattern is formed on the copper foil, and a nickel film 42N is formed on the plating resist non-formed portion by electrolytic plating. The thickness of the nickel film is 5 μm. A gold film 42A and a nickel film 420N are formed on the nickel film by electrolytic plating. The first conductor layer 42 is formed on the nickel film 420N by electrolytic copper plating. The thickness of the first conductor layer is 10 to 75 μm. The plating resist is removed (FIG. 1C). A die attach 44 is formed by a conductive paste such as an Au-Sn paste at the IC chip attachment position of the copper foil 40 (FIG. 1D).

該ダイアタッチ４４上にＩＣチップなどの電子部品９０が搭載される（図２（Ａ））。実施形態１では、ＩＣチップの背面がダイアタッチに接着される。電子部品の厚み（Ｔ）は４０〜１５０μｍである。熱処理でダイアタッチが硬化する。シリカなどの無機粒子とエポキシ樹脂を含むＢステージの樹脂フィルムが電子部品９０と第１導体層上に積層される。樹脂フィルムの厚みは電子部品の厚み（Ｔ）より１５〜４０μｍ程度厚い。その後、熱処理で樹脂フィルムは硬化する。第１樹脂絶縁層が銅箔と第１導体層上に形成される。電子部品が第１樹脂絶縁層に収容される（図２（Ｂ））。第１樹脂絶縁層の厚みは５５〜１９０μｍであり、電子部品の厚みより１５〜４０μｍ程度厚い。電子部品の電極の上面から第１樹脂絶縁層の第１面までの距離（Ｌ）は１５〜４０μｍである。第１樹脂絶縁層５０にレーザで、第１ビア導体を形成するための開口５０ａと、接続ビア導体を形成するための開口５０ｂが形成される（図２（Ｃ））。開口５０ａのトップ径（ｅ２）と開口５０ｂのトップ径（ｅ４）は異なっていてｅ２はｅ４より大きいことが好ましい。ｅ２／ｅ４は１．１〜２であることが好ましい。第１ビア導体が太くなるので、電子部品が内蔵されていない部分の第１樹脂絶縁層が第１ビア導体で補強される。プリント配線板の反りやうねりが抑えられる。
無電解めっき処理により第１樹脂絶縁層５０の表面に無電解めっき膜５１が形成される（図２（Ｄ））。 An electronic component 90 such as an IC chip is mounted on the die attach 44 (FIG. 2A). In the first embodiment, the back surface of the IC chip is bonded to the die attach. The thickness (T) of the electronic component is 40 to 150 μm. The die attach is cured by heat treatment. A B-stage resin film containing inorganic particles such as silica and an epoxy resin is laminated on the electronic component 90 and the first conductor layer. The thickness of the resin film is about 15 to 40 μm thicker than the thickness (T) of the electronic component. Thereafter, the resin film is cured by heat treatment. A first resin insulation layer is formed on the copper foil and the first conductor layer. The electronic component is accommodated in the first resin insulating layer (FIG. 2B). The thickness of the first resin insulation layer is 55 to 190 μm, which is about 15 to 40 μm thicker than the thickness of the electronic component. The distance (L) from the upper surface of the electrode of the electronic component to the first surface of the first resin insulation layer is 15 to 40 μm. An opening 50a for forming the first via conductor and an opening 50b for forming the connection via conductor are formed in the first resin insulating layer 50 with a laser (FIG. 2C). The top diameter (e2) of the opening 50a and the top diameter (e4) of the opening 50b are different, and e2 is preferably larger than e4. It is preferable that e2 / e4 is 1.1-2. Since the first via conductor is thickened, the first resin insulating layer in the portion where the electronic component is not incorporated is reinforced with the first via conductor. Warping and undulation of the printed wiring board can be suppressed.
An electroless plating film 51 is formed on the surface of the first resin insulating layer 50 by the electroless plating process (FIG. 2D).

電解めっき膜５１上に所定パターンのめっきレジスト５４が形成される（図３（Ａ））。電解めっき処理により、開口５０ａ、開口５０ｂがめっきで充填されると共に、めっきレジスト非形成部に電解めっき膜５６が形成される（図３（Ｂ））。めっきレジスト５４が除去され、電解めっき膜５６間の無電解めっき膜５１が除去される。第２導体層５８及び第１ビア導体５９Ａ、接続ビア導体５９Ｂが完成する（図３（Ｃ））。
第２導体層と第１樹脂絶縁層上に第２樹脂絶縁層６０が形成される（図３（Ｄ））。第２樹脂絶縁層の厚みは２５〜４５μｍであることが好ましい。第２樹脂絶縁層はシリカなどの無機粒子とエポキシ樹脂を含む。さらに、第２樹脂絶縁層はガラスクロスなどの補強材を含んでも良い。 A plating resist 54 having a predetermined pattern is formed on the electrolytic plating film 51 (FIG. 3A). Through the electrolytic plating treatment, the openings 50a and 50b are filled with plating, and an electrolytic plating film 56 is formed in the portion where the plating resist is not formed (FIG. 3B). The plating resist 54 is removed, and the electroless plating film 51 between the electrolytic plating films 56 is removed. The second conductor layer 58, the first via conductor 59A, and the connection via conductor 59B are completed (FIG. 3C).
A second resin insulation layer 60 is formed on the second conductor layer and the first resin insulation layer (FIG. 3D). The thickness of the second resin insulation layer is preferably 25 to 45 μm. The second resin insulating layer includes inorganic particles such as silica and an epoxy resin. Furthermore, the second resin insulating layer may include a reinforcing material such as glass cloth.

第２樹脂絶縁層６０にレーザで、第２ビア導体を形成するための開口６０ａが形成される（図４（Ａ））。第２ビア導体のトップ径は第１ビア導体や接続ビア導体のトップ径より小さいことが好ましい。樹脂絶縁層の層数が少なくなる。無電解めっき処理により第２樹脂絶縁層６０の表面に無電解めっき膜６１が形成される（図４（Ｂ））。無電解めっき膜６１上に所定パターンのめっきレジスト６４が形成される（図４（Ｃ））。 An opening 60a for forming a second via conductor is formed in the second resin insulating layer 60 with a laser (FIG. 4A). The top diameter of the second via conductor is preferably smaller than the top diameter of the first via conductor or the connection via conductor. The number of resin insulation layers is reduced. An electroless plating film 61 is formed on the surface of the second resin insulating layer 60 by the electroless plating process (FIG. 4B). A plating resist 64 having a predetermined pattern is formed on the electroless plating film 61 (FIG. 4C).

電解めっき処理により、開口６０ａはめっきで充填されると共に、めっきレジスト非形成部に電解めっき膜６６が形成される（図５（Ａ））。めっきレジスト６４が除去され、電解めっき膜６６間の無電解めっき膜６１が除去される。第３導体層６８及び第２ビア導体６９が完成する（図５（Ｂ））。第３導体層の厚みは第２導体層の厚みより薄い。さらに、第３導体層の厚みは第１導体層の厚みより薄いことが好ましい。 Through the electrolytic plating process, the opening 60a is filled with plating, and an electrolytic plating film 66 is formed in the portion where the plating resist is not formed (FIG. 5A). The plating resist 64 is removed, and the electroless plating film 61 between the electrolytic plating films 66 is removed. The third conductor layer 68 and the second via conductor 69 are completed (FIG. 5B). The thickness of the third conductor layer is thinner than the thickness of the second conductor layer. Further, the thickness of the third conductor layer is preferably thinner than the thickness of the first conductor layer.

第２樹脂絶縁層と第３導体層上に開口８０ａを備えるソルダーレジスト層８０が形成される（図６（Ａ））。両面銅張積層板３０と銅箔４０が分離される（図６（Ｂ））。銅箔４０が選択エッチング液でエッチングにより除去される（図６（Ｃ））。エッチング液として、例えば、特開２００５−１０５４１１に開示されているエッチング液が用いられる。
続いて、外部端子４２上のニッケル膜４２Ｎが選択エッチング液でエッチングにより除去される。外部端子上の金膜が露出する。プリント配線板１０が完成する。エッチング液として、例えば、日本化学産業株式会社製のNickel selective etchant-NCが用いられる。 A solder resist layer 80 having an opening 80a is formed on the second resin insulating layer and the third conductor layer (FIG. 6A). The double-sided copper-clad laminate 30 and the copper foil 40 are separated (FIG. 6B). The copper foil 40 is removed by etching with a selective etchant (FIG. 6C). As the etchant, for example, an etchant disclosed in JP-A-2005-105411 is used.
Subsequently, the nickel film 42N on the external terminal 42 is removed by etching with a selective etchant. The gold film on the external terminal is exposed. The printed wiring board 10 is completed. As an etchant, for example, Nickel selective etchant-NC manufactured by Nippon Chemical Industry Co., Ltd. is used.

ソルダーレジスト層８０の開口８０ａにより露出する第３導体層または第２ビア導体に半田バンプ８６Ｕが形成され、第１導体層４２に半田バンプ８６Ｄが形成される。半田バンプを有するプリント配線板１０００が完成する（図７）。そして、半田バンプ８６Ｄを介してパッケージ基板１００がプリント配線板１０に搭載され、半田バンプ８６Ｕを介してドータボード２００にプリント配線板１０００が実装される（図８）。 A solder bump 86U is formed on the third conductor layer or the second via conductor exposed through the opening 80a of the solder resist layer 80, and a solder bump 86D is formed on the first conductor layer. A printed wiring board 1000 having solder bumps is completed (FIG. 7). Then, the package substrate 100 is mounted on the printed wiring board 10 via the solder bumps 86D, and the printed wiring board 1000 is mounted on the daughter board 200 via the solder bumps 86U (FIG. 8).

[実施形態２]
実施形態１では樹脂絶縁層の層数が２層である。但し、層数は２層に限定されない。
上述の図３（Ｄ）〜図５（Ｂ）と同様の工程により、第２樹脂絶縁層と第３導体層上に第３樹脂絶縁層７０、第３ビア導体７９と第４導体層７８を形成することができる。第３樹脂絶縁層の厚みは第２樹脂絶縁層の厚みと同じである。第３ビア導体用の開口のトップ径とボトム径の大きさは第２ビア導体用の開口のトップ径とボトム径の大きさと同様である。第４導体層の厚みは第３導体層の厚みと同様であり、第２導体層の厚み／第４導体層の厚みの関係は第２導体層の厚み／第３導体層の厚みの関係と同様である。第１導体層の厚み／第４導体層の厚みの関係は、第１導体層の厚み／第３導体層の厚みの関係と同様である。 [Embodiment 2]
In Embodiment 1, the number of resin insulation layers is two. However, the number of layers is not limited to two.
The third resin insulation layer 70, the third via conductor 79, and the fourth conductor layer 78 are formed on the second resin insulation layer and the third conductor layer by the same process as that shown in FIGS. Can be formed. The thickness of the third resin insulation layer is the same as the thickness of the second resin insulation layer. The sizes of the top diameter and the bottom diameter of the opening for the third via conductor are the same as the sizes of the top diameter and the bottom diameter of the opening for the second via conductor. The thickness of the fourth conductor layer is the same as the thickness of the third conductor layer, and the relationship of the thickness of the second conductor layer / the thickness of the fourth conductor layer is the relationship of the thickness of the second conductor layer / the thickness of the third conductor layer. It is the same. The relationship of the thickness of the first conductor layer / the thickness of the fourth conductor layer is the same as the relationship of the thickness of the first conductor layer / the thickness of the third conductor layer.

図６（Ａ）と同様に第３樹脂絶縁層と第４導体層上にソルダーレジスト層が形成される。それ以降、実施形態１と同様な工程で半田バンプを有するプリント配線板が製造される（図９）。 Similar to FIG. 6A, a solder resist layer is formed on the third resin insulating layer and the fourth conductor layer. Thereafter, a printed wiring board having solder bumps is manufactured in the same process as in the first embodiment (FIG. 9).

[実施例]
図１〜図６を参照し、実施例のプリント配線板の製造方法が以下に説明される。
厚さ０．８ｍｍの両面銅張積層板３０と、厚さ５μｍの銅箔４０が準備される（図１（Ａ）。 [Example]
With reference to FIGS. 1-6, the manufacturing method of the printed wiring board of an Example is demonstrated below.
A double-sided copper clad laminate 30 having a thickness of 0.8 mm and a copper foil 40 having a thickness of 5 μm are prepared (FIG. 1A).

両面銅張積層板３０に銅箔４０が超音波により接合される（図１（Ｂ））。銅箔上に所定パターンのめっきレジストが形成され、めっきレジスト非形成部に電解めっきによりニッケル膜４２Ｎが形成される。ニッケル膜の厚さは５μｍである。ニッケル膜上に電解めっきで金膜４２Ａとニッケル膜４２０Ｎが形成される。ニッケル膜４２０Ｎ上に電解銅めっきで第１導体層４２が形成される。第１導体層の厚みは１５μｍである。めっきレジストが除去される（図１（Ｃ））。銅箔４０のＩＣチップ取り付け位置にＡｕ−Ｓｎペーストによりダイアタッチ４４が形成される（図１（Ｄ））。 The copper foil 40 is joined to the double-sided copper clad laminate 30 by ultrasonic waves (FIG. 1B). A plating resist having a predetermined pattern is formed on the copper foil, and a nickel film 42N is formed on the plating resist non-formed portion by electrolytic plating. The thickness of the nickel film is 5 μm. A gold film 42A and a nickel film 420N are formed on the nickel film by electrolytic plating. The first conductor layer 42 is formed on the nickel film 420N by electrolytic copper plating. The thickness of the first conductor layer is 15 μm. The plating resist is removed (FIG. 1C). The die attach 44 is formed by the Au-Sn paste at the IC chip attachment position of the copper foil 40 (FIG. 1D).

該ダイアタッチ４４上にＩＣチップ９０が搭載される（図２（Ａ））。ＩＣチップの背面がダイアタッチに接着される。電子部品の厚み（Ｔ）は１００μｍである。熱処理でダイアタッチが硬化する。シリカ粒子とエポキシ樹脂を含むＢステージの樹脂フィルムが電子部品９０と第１導体層上に積層される。その後、熱処理で樹脂フィルムは硬化する。第１樹脂絶縁層が銅箔と第１導体層上に形成される。ＩＣチップが内蔵される（図２（Ｂ））。第１樹脂絶縁層の厚みは１４０μｍである。第１樹脂絶縁層５０にレーザで、第１ビア導体を形成するための開口５０ａと、接続ビア導体を形成するための開口５０ｂが形成される（図２（Ｃ））。開口５０ａのトップ径（ｅ２）は１２０μｍであり、開口５０ｂのトップ径（ｅ４）は６０μｍである。両者のボトム径（ｅ１、ｅ３）は４５μｍである。
無電解銅めっき処理により第１樹脂絶縁層５０の表面に無電解銅めっき膜５１が形成される（図２（Ｄ））。 An IC chip 90 is mounted on the die attach 44 (FIG. 2A). The back surface of the IC chip is bonded to the die attach. The thickness (T) of the electronic component is 100 μm. The die attach is cured by heat treatment. A B-stage resin film containing silica particles and an epoxy resin is laminated on the electronic component 90 and the first conductor layer. Thereafter, the resin film is cured by heat treatment. A first resin insulation layer is formed on the copper foil and the first conductor layer. An IC chip is incorporated (FIG. 2B). The thickness of the first resin insulation layer is 140 μm. An opening 50a for forming the first via conductor and an opening 50b for forming the connection via conductor are formed in the first resin insulating layer 50 with a laser (FIG. 2C). The top diameter (e2) of the opening 50a is 120 μm, and the top diameter (e4) of the opening 50b is 60 μm. Both bottom diameters (e1, e3) are 45 μm.
An electroless copper plating film 51 is formed on the surface of the first resin insulation layer 50 by the electroless copper plating process (FIG. 2D).

無電解銅めっき膜５１上に所定パターンのめっきレジスト５４が形成される（図３（Ａ））。電解銅めっき処理により、開口５０ａ、開口５０ｂが銅めっきで充填されると共に、めっきレジスト非形成部に電解銅めっき膜５６が形成される（図３（Ｂ））。めっきレジスト５４が除去され、電解銅めっき膜５６間の無電解銅めっき膜５１が除去される。第２導体層５８及び第１ビア導体５９Ａ、接続ビア導体５９Ｂが完成する（図３（Ｃ））。第２導体層の厚みは３０μｍである。
第２導体層と第１樹脂絶縁層上に第２樹脂絶縁層６０が形成される。（図３（Ｄ））。第２樹脂絶縁層の厚みは３５μｍである。第２樹脂絶縁層はシリカ粒子とエポキシ樹脂とガラスクロスを含む。 A plating resist 54 having a predetermined pattern is formed on the electroless copper plating film 51 (FIG. 3A). Through the electrolytic copper plating treatment, the openings 50a and 50b are filled with copper plating, and an electrolytic copper plating film 56 is formed in the plating resist non-forming portion (FIG. 3B). The plating resist 54 is removed, and the electroless copper plating film 51 between the electrolytic copper plating films 56 is removed. The second conductor layer 58, the first via conductor 59A, and the connection via conductor 59B are completed (FIG. 3C). The thickness of the second conductor layer is 30 μm.
A second resin insulation layer 60 is formed on the second conductor layer and the first resin insulation layer. (FIG. 3D). The thickness of the second resin insulation layer is 35 μm. The second resin insulation layer includes silica particles, epoxy resin, and glass cloth.

第２樹脂絶縁層６０にレーザで、第２ビア導体を形成するための開口６０ａが形成される（図４（Ａ））。開口６０ａのトップ径は５０μｍであり、ボトム径は４５μｍである。無電解銅めっき処理により第２樹脂絶縁層６０の表面に無電解銅めっき膜６１が形成される（図４（Ｂ））。無電解銅めっき膜６１上に所定パターンのめっきレジスト６４が形成される（図４（Ｃ））。 An opening 60a for forming a second via conductor is formed in the second resin insulating layer 60 with a laser (FIG. 4A). The top diameter of the opening 60a is 50 μm, and the bottom diameter is 45 μm. An electroless copper plating film 61 is formed on the surface of the second resin insulating layer 60 by the electroless copper plating process (FIG. 4B). A plating resist 64 having a predetermined pattern is formed on the electroless copper plating film 61 (FIG. 4C).

電解銅めっき処理により、開口６０ａは銅めっきで充填されると共に、めっきレジスト非形成部に電解銅めっき膜６６が形成される（図５（Ａ））。めっきレジスト６４が除去され、電解銅めっき膜６６間の無電解銅めっき膜６１が除去される。第３導体層６８及び第２ビア導体６９が完成する（図５（Ｂ））。第３導体層の厚みは１２μｍである。 By the electrolytic copper plating treatment, the opening 60a is filled with copper plating, and an electrolytic copper plating film 66 is formed in the portion where the plating resist is not formed (FIG. 5A). The plating resist 64 is removed, and the electroless copper plating film 61 between the electrolytic copper plating films 66 is removed. The third conductor layer 68 and the second via conductor 69 are completed (FIG. 5B). The thickness of the third conductor layer is 12 μm.

第２樹脂絶縁層と第３導体層上に開口８０ａを備えるソルダーレジスト層８０が形成される（図６（Ａ））。両面銅張積層板３０と銅箔４０が分離される（図６（Ｂ））。銅箔４０が特開２００５−１０５４１１に開示されているエッチング液で除去される。続いて、外部端子上のニッケル膜４２Ｎが選択エッチング液でエッチングにより除去される。外部端子上の金膜が露出する。エッチング液として、例えば、日本化学産業株式会社製のNickel selective etchant-NCが用いられる。プリント配線板１０が完成する（図６（Ｃ））。 A solder resist layer 80 having an opening 80a is formed on the second resin insulating layer and the third conductor layer (FIG. 6A). The double-sided copper-clad laminate 30 and the copper foil 40 are separated (FIG. 6B). The copper foil 40 is removed with an etching solution disclosed in JP-A-2005-105411. Subsequently, the nickel film 42N on the external terminal is removed by etching with a selective etching solution. The gold film on the external terminal is exposed. As an etchant, for example, Nickel selective etchant-NC manufactured by Nippon Chemical Industry Co., Ltd. is used. The printed wiring board 10 is completed (FIG. 6C).

１０ プリント配線板
５０ 第１樹脂絶縁層
５８ 第２導体層
５９Ａ 第１ビア導体
６０ 第２樹脂絶縁層
６８ 第３導体層
６９ 第２ビア導体
７０ 第３樹脂絶縁層
７８ 第３導体層
７９ 第３ビア導体
９０ 電子部品 DESCRIPTION OF SYMBOLS 10 Printed wiring board 50 1st resin insulation layer 58 2nd conductor layer 59A 1st via conductor 60 2nd resin insulation layer 68 3rd conductor layer 69 2nd via conductor 70 3rd resin insulation layer 78 3rd conductor layer 79 3rd Via conductor 90 Electronic parts

Claims (14)

第１導体層と、
第１面と該第１面とは反対側の第２面とを有し、該第２面が前記第１導体層と対向するように前記第１導体層上に積層されている第１樹脂絶縁層と、
前記第１樹脂絶縁層内に収容されていて電極を有する電子部品と、
前記第１樹脂絶縁層の第１面に形成されている第２導体層と、
前記第１樹脂絶縁層を貫通し、前記第１導体層と前記第２導体層とを接続している第１ビア導体と、
前記第１樹脂絶縁層に形成されていて前記電子部品の電極と前記第２導体層とを接続している接続ビア導体と、
第１面と該第１面とは反対側の第２面とを有し、該第２面が前記第１樹脂絶縁層の第１面と対向するように前記第２導体層と前記第１樹脂絶縁層上に積層されている第２樹脂絶縁層と、
前記第２樹脂絶縁層の第１面上に形成されている第３導体層と、
前記第２樹脂絶縁層を貫通し、前記第２導体層と前記第３導体層とを接続している第２ビア導体と、を有するプリント配線板において、
前記第２導体層の厚みは前記第３導体層の厚みより厚い。 A first conductor layer;
A first resin having a first surface and a second surface opposite to the first surface, the second surface being laminated on the first conductor layer so as to face the first conductor layer An insulating layer;
An electronic component housed in the first resin insulation layer and having an electrode;
A second conductor layer formed on the first surface of the first resin insulation layer;
A first via conductor passing through the first resin insulation layer and connecting the first conductor layer and the second conductor layer;
A connection via conductor formed in the first resin insulation layer and connecting the electrode of the electronic component and the second conductor layer;
The second conductor layer and the first surface have a first surface and a second surface opposite to the first surface, and the second surface faces the first surface of the first resin insulation layer. A second resin insulation layer laminated on the resin insulation layer;
A third conductor layer formed on the first surface of the second resin insulation layer;
A printed wiring board having a second via conductor penetrating the second resin insulation layer and connecting the second conductor layer and the third conductor layer;
The second conductor layer is thicker than the third conductor layer. 請求項１のプリント配線板において、
前記第１樹脂絶縁層の厚みは前記第２樹脂絶縁層の厚みより厚い。 In the printed wiring board of Claim 1,
The first resin insulation layer is thicker than the second resin insulation layer. 請求項２のプリント配線板において、
前記第１樹脂絶縁層の第１面での前記第１ビア導体の径（トップ径）は前記第２樹脂絶縁層の第１面での前記第２ビア導体の径（トップ径）より大きい。 In the printed wiring board of Claim 2,
The diameter (top diameter) of the first via conductor on the first surface of the first resin insulation layer is larger than the diameter (top diameter) of the second via conductor on the first surface of the second resin insulation layer. 請求項１のプリント配線板において、
前記第１導体層上の前記第１ビア導体の径（ボトム径）は前記電子部品の電極上の前記接続ビア導体の径（ボトム径）より小さい。 In the printed wiring board of Claim 1,
The diameter (bottom diameter) of the first via conductor on the first conductor layer is smaller than the diameter (bottom diameter) of the connection via conductor on the electrode of the electronic component. 請求項１のプリント配線板において：
前記第２導体層の厚さを前記第３導体層の厚さで割ることで得られる値は、１．２〜５である。 The printed wiring board of claim 1:
A value obtained by dividing the thickness of the second conductor layer by the thickness of the third conductor layer is 1.2 to 5. 請求項３のプリント配線板において：
前記第１ビア導体のトップ径を前記第２ビア導体のトップ径で割ることで得られる値は、１．０５〜４である。 The printed wiring board of claim 3:
A value obtained by dividing the top diameter of the first via conductor by the top diameter of the second via conductor is 1.05-4. 請求項１のプリント配線板において、
さらに、第１面と該第１面とは反対側の第２面とを有し、該第２面が前記第２樹脂絶縁層の第１面と対向するように前記第３導体層と前記第２樹脂絶縁層上に積層されている第３樹脂絶縁層と前記第３樹脂絶縁層の第１面上に形成されている第４導体層と前記第３樹脂絶縁層を貫通し、前記第３導体層と前記第４導体層とを接続している第３ビア導体とを有し、前記第４導体層の厚みと前記第３導体層の厚みは略等しい。 In the printed wiring board of Claim 1,
Further, the third conductor layer and the second surface have a first surface and a second surface opposite to the first surface, and the second surface faces the first surface of the second resin insulation layer. A third resin insulation layer laminated on the second resin insulation layer, a fourth conductor layer formed on the first surface of the third resin insulation layer, and the third resin insulation layer; A third via conductor connecting the third conductor layer and the fourth conductor layer, and the fourth conductor layer and the third conductor layer are substantially equal in thickness. 請求項７のプリント配線板において、
前記第２樹脂絶縁層の厚みと前記第３樹脂絶縁層の厚みは略等しい。 In the printed wiring board of Claim 7,
The thickness of the second resin insulation layer and the thickness of the third resin insulation layer are substantially equal. 請求項５のプリント配線板において、
さらに、第１面と該第１面とは反対側の第２面とを有し、該第２面が前記第２樹脂絶縁層の第１面と対向するように前記第３導体層と前記第２樹脂絶縁層上に積層されている第３樹脂絶縁層と前記第３樹脂絶縁層の第１面上に形成されている第４導体層と前記第３樹脂絶縁層を貫通し、前記第３導体層と前記第４導体層とを接続している第３ビア導体とを有し、前記第４導体層の厚みと前記第３導体層の厚みは略等しく、前記第２樹脂絶縁層の厚みと前記第３樹脂絶縁層の厚みは略等しい。 In the printed wiring board of Claim 5,
Further, the third conductor layer and the second surface have a first surface and a second surface opposite to the first surface, and the second surface faces the first surface of the second resin insulation layer. A third resin insulation layer laminated on the second resin insulation layer, a fourth conductor layer formed on the first surface of the third resin insulation layer, and the third resin insulation layer; A third via conductor connecting the third conductor layer and the fourth conductor layer, wherein the thickness of the fourth conductor layer is substantially equal to the thickness of the third conductor layer; The thickness and the thickness of the third resin insulating layer are substantially equal. 請求項１のプリント配線板において、前記第１樹脂絶縁層は補強材を有さない。 2. The printed wiring board according to claim 1, wherein the first resin insulating layer does not have a reinforcing material. 請求項１０のプリント配線板において、前記補強材は繊維で形成されている。 The printed wiring board according to claim 10, wherein the reinforcing material is formed of fibers. 請求項１のプリント配線板において、前記第１樹脂絶縁層は最外の樹脂絶縁層である。 2. The printed wiring board according to claim 1, wherein the first resin insulation layer is an outermost resin insulation layer. 請求項１２のプリント配線板において、前記第２樹脂絶縁層の第１面上にソルダーレジスト層が形成されている。 13. The printed wiring board according to claim 12, wherein a solder resist layer is formed on the first surface of the second resin insulation layer. 請求項１０のプリント配線板において、前記第２樹脂絶縁層は補強材を有している。 The printed wiring board according to claim 10, wherein the second resin insulating layer has a reinforcing material.
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