JP5600698B2 - Power semiconductor module with SiC element - Google Patents

Power semiconductor module with SiC element Download PDF

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JP5600698B2
JP5600698B2 JP2012056618A JP2012056618A JP5600698B2 JP 5600698 B2 JP5600698 B2 JP 5600698B2 JP 2012056618 A JP2012056618 A JP 2012056618A JP 2012056618 A JP2012056618 A JP 2012056618A JP 5600698 B2 JP5600698 B2 JP 5600698B2
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resin layer
electric field
semiconductor device
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和弘 鈴木
秀勝 小野瀬
睦宏 森
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株式会社 日立パワーデバイス
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

本発明は、ＳｉＣ素子を搭載した高耐圧パワー半導体モジュールのＳｉＣ素子実装構造に関する。   The present invention relates to a SiC element mounting structure of a high withstand voltage power semiconductor module equipped with a SiC element.

省エネルギー化、省資源、環境保全などへの規制・要請を背景に、パワー半導体モジュールを用いた電力制御システムが不可欠なものになっている。特に、近年より小型で耐圧性に優れたパワー半導体モジュールの開発が求められている。しかし、パワー半導体モジュールを小型化して高耐圧の用途で用いようとすると、電位の分布が集中してしまう素子端部で、絶縁破壊が起こってしまう。   Power control systems using power semiconductor modules have become indispensable against the background of regulations and requests for energy saving, resource saving, environmental conservation, and the like. In particular, in recent years, there has been a demand for the development of power semiconductor modules that are smaller and have superior pressure resistance. However, if the power semiconductor module is miniaturized and used for high withstand voltage applications, dielectric breakdown occurs at the end of the element where the potential distribution is concentrated.

そこで、従来の素子では、素子上面周辺領域を取り囲むようにガードリングを形成し、電位分布を安定化させることで主耐圧特性を確保している。特許文献１には、主耐圧特性等が悪化するのを防止するため、ガードリング上にシリコン窒化膜を形成し、さらにオーバーコート膜を形成することが記載されている。また、近年より高耐圧性に優れたＳｉＣ素子やＧａＮ素子を含むワイドギャップ半導体素子の開発が進められている。特にＳｉＣ素子は、高耐圧性に優れた材料物性から高耐圧用途への展開に有利であり、このような素子を用いたパワー半導体装置の開発が進められている。   Therefore, in the conventional element, the main breakdown voltage characteristic is ensured by forming a guard ring so as to surround the peripheral area of the upper surface of the element and stabilizing the potential distribution. Patent Document 1 describes that a silicon nitride film is formed on a guard ring and an overcoat film is formed on the guard ring in order to prevent deterioration of main breakdown voltage characteristics and the like. In recent years, development of wide gap semiconductor elements including SiC elements and GaN elements having excellent high voltage resistance has been promoted. In particular, SiC elements are advantageous for the development of materials having excellent high voltage resistance to high voltage applications, and power semiconductor devices using such elements are being developed.

特開２０１０−３４３０６号公報JP 2010-34306 A

一方、特許文献１に記載のパワー半導体モジュールで、素子をＳｉＣ素子とした場合、ＳｉＣ素子では、デバイス内部の電界がＳｉよりも約１０倍大きくなるため、周辺電界緩和領域に発生する電界強度はＳｉ素子に比べて非常に大きくなってしまう。図５は、ゲル中に発生する最大電界を解析的に見積もったものである。ＳｉＣ素子を単純にシリコーンゲル封止した場合には（図５の横軸０μｍに相当）、ゲル中にゲル自体の絶縁破壊強度の５倍程度の電界が発生することを示している。このため、ＳｉＣ素子を用いた場合に安定した耐圧特性を確保するためにはゲル中の最大電界を低減させることが必要である。   On the other hand, in the power semiconductor module described in Patent Document 1, when the element is a SiC element, in the SiC element, the electric field inside the device is about 10 times larger than that of Si. It becomes very large compared with the Si element. FIG. 5 is an analytical estimate of the maximum electric field generated in the gel. When the SiC element is simply sealed with silicone gel (corresponding to 0 μm on the horizontal axis in FIG. 5), an electric field of about 5 times the dielectric breakdown strength of the gel itself is generated in the gel. For this reason, it is necessary to reduce the maximum electric field in the gel in order to ensure a stable breakdown voltage characteristic when the SiC element is used.

したがって、本発明では上記課題に鑑み、ＳｉＣ素子端部の耐圧特性を確保したＳｉＣ素子搭載パワー半導体モジュールを提供することを目的とする。   Therefore, in view of the above problems, an object of the present invention is to provide an SiC element-mounted power semiconductor module that ensures the breakdown voltage characteristics of the SiC element end.

上記課題を解決するために、本発明に係るパワー半導体モジュールは、素子上面周辺部に電界緩和領域を有するＳｉＣからなる半導体素子と、前記半導体素子を封止するシリコーンゲルと、を有する半導体装置において、前記電界緩和領域とシリコーンゲルとの間には、ＳｉＯ2から成る無機層と、当該無機層の上部に形成された樹脂層とを有し、前記樹脂層の誘電率は、前記無機層の誘電率以下であり、且つシリコーンゲルの誘電率以上であることを特徴とする。 In order to solve the above-described problems, a power semiconductor module according to the present invention is a semiconductor device having a semiconductor element made of SiC having an electric field relaxation region at the periphery of the upper surface of the element, and a silicone gel for sealing the semiconductor element. In addition, between the electric field relaxation region and the silicone gel, there is an inorganic layer made of SiO 2 and a resin layer formed on the inorganic layer, and the dielectric constant of the resin layer is that of the inorganic layer. It is characterized by being below the dielectric constant and above the dielectric constant of the silicone gel.

本発明によれば、ＳｉＣ素子端部の耐圧特性を確保したＳｉＣ素子搭載パワー半導体モジュールを提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the SiC element mounting power semiconductor module which ensured the pressure | voltage resistant characteristic of the SiC element edge part can be provided.

本発明に係るＳｉＣ素子搭載パワー半導体モジュールの模式断面図である。It is a schematic cross section of the SiC element mounting power semiconductor module which concerns on this invention. 本発明に係るＳｉＣ素子部の模式断面図である。It is a schematic cross section of the SiC element part which concerns on this invention. 本発明に係るＳｉＣ素子端部の模式断面図である。It is a schematic cross section of the SiC element end part concerning the present invention. 本発明の第二の実施形態に係るＳｉＣ素子部の模式断面図である。It is a schematic cross section of the SiC element part which concerns on 2nd embodiment of this invention. 本発明に係るゲル中電界強度の解析結果を示す図である。It is a figure which shows the analysis result of the electric field strength in the gel which concerns on this invention. 本発明の第二の実施形態に係るＳｉＣ素子端部の模式断面図である。It is a schematic cross section of the SiC element end part concerning a second embodiment of the present invention. 本発明の第三の実施形態に係るＳｉＣ素子端部の模式断面図である。It is a schematic cross section of the SiC element end part concerning a third embodiment of the present invention.

以下、本発明の実施例を図面に基づき説明する。   Embodiments of the present invention will be described below with reference to the drawings.

（第一の実施形態）
本発明に係るＳｉＣ素子搭載パワー半導体モジュール１００の模式断面を図１に示す。本発明が対象とするＳｉＣ素子搭載パワー半導体モジュールは、ＳｉＣ素子がスイッチング素子として搭載されていても良いし、フリーホイールダイオード素子として搭載されていても良いし、両方の素子として搭載されていても良い。 (First embodiment)
FIG. 1 shows a schematic cross section of an SiC element-mounted power semiconductor module 100 according to the present invention. The SiC element-mounted power semiconductor module targeted by the present invention may be mounted with a SiC element as a switching element, a free wheel diode element, or both elements. good.

図１では、ＩＧＢＴにＳｉ素子を用い、ダイオードにＳｉＣ素子を用いたものを例に説明する。本実施形態に係るパワー半導体モジュール１００は、放熱ベース１１、セラミックス回路基板６、ＳｉＣ素子（ダイオード）１Ａ、Ｓｉ素子（ＩＧＢＴ）１Ｂ、外部出力端子９Ａ、９Ｂ、及びモジュールケース１０を有している。セラミックス回路基板６は、一方の面に、ＳｉＣ素子１Ａ、Ｓｉ素子１Ｂと接続される配線パターン６Ａ１及び外部出力端子９Ｂが接続される６Ａ２が設けられ、他方の面に、放熱ベース１１と接続される金属パターン６Ｃを有している。金属パターン６Ｃと放熱ベース１１とは、はんだもしくは金属ペーストを焼結した接合層５Ｂを介して接合される。一方、配線パターン６Ａ１とＳｉＣ素子１Ａ及びＳｉ素子１Ｂは、はんだもしくは金属ペーストを焼結した接合層５Ａを介して接合される。また、正極側と接続される外部出力端子９Ａ（９）は、配線パターン６Ａ１（６Ａ）と直接超音波接合で接合されており、負極側と接続される外部出力端子９Ｂ（９）は、配線パターン６Ａ２（６Ａ）と直接超音波接合で接合されている。なお、ここでは外部出力端子９と配線パターン６との接続は超音波接合としたが、他の接合方法を用いても良いのは言うまでもない。   In FIG. 1, an example in which a Si element is used for the IGBT and a SiC element is used for the diode will be described. A power semiconductor module 100 according to this embodiment includes a heat dissipation base 11, a ceramic circuit board 6, a SiC element (diode) 1A, a Si element (IGBT) 1B, external output terminals 9A and 9B, and a module case 10. . The ceramic circuit board 6 is provided with a wiring pattern 6A1 connected to the SiC element 1A and the Si element 1B and 6A2 connected to the external output terminal 9B on one surface, and connected to the heat dissipation base 11 on the other surface. A metal pattern 6C. The metal pattern 6C and the heat dissipation base 11 are bonded via a bonding layer 5B obtained by sintering solder or metal paste. On the other hand, the wiring pattern 6A1, the SiC element 1A, and the Si element 1B are bonded via a bonding layer 5A obtained by sintering solder or metal paste. Further, the external output terminal 9A (9) connected to the positive electrode side is directly joined to the wiring pattern 6A1 (6A) by ultrasonic bonding, and the external output terminal 9B (9) connected to the negative electrode side is connected to the wiring pattern 6A1 (6A). It is joined to the pattern 6A2 (6A) by direct ultrasonic joining. Here, the connection between the external output terminal 9 and the wiring pattern 6 is ultrasonic bonding, but it goes without saying that other bonding methods may be used.

この外部出力端子９Ａ及び９Ｂは、モジュールケース１０の外部に引き出されて他の機器と接続される。   The external output terminals 9A and 9B are drawn out of the module case 10 and connected to other devices.

ＳｉＣ素子１Ａ及びＳｉ素子１Ｂにおける配線パターン６Ａ１側と反対側の面は、ボンディングワイヤ４を介して、外部出力端子９Ｂが接続される配線パターン６Ａ２に接続されている。なお、ＳｉＣ素子１Ａの詳細構造については、下記で詳細に説明する。   The surface opposite to the wiring pattern 6A1 side of the SiC element 1A and the Si element 1B is connected via a bonding wire 4 to a wiring pattern 6A2 to which the external output terminal 9B is connected. The detailed structure of SiC element 1A will be described in detail below.

モジュールケース１０は、放熱ベース１１に固定されており、内部がシリコーンゲル３で満たされている。   The module case 10 is fixed to the heat dissipation base 11, and the inside is filled with the silicone gel 3.

図２は図１のＳｉＣ素子搭載部１１０を拡大したものである。ＳｉＣ素子１Ａの表面には樹脂材２が塗布されており、ＳｉＣ素子１Ａの端部の樹脂材２の厚さが厚くなった構造をしている。この構造が本発明の一つの特徴となっている。   FIG. 2 is an enlarged view of the SiC element mounting portion 110 of FIG. Resin material 2 is applied to the surface of SiC element 1A, and the thickness of resin material 2 at the end of SiC element 1A is increased. This structure is one of the features of the present invention.

図２のＳｉＣ素子端部１２０のより詳細な構造を図３に示す。まず、ＳｉＣ素子１Ａの具体的な構造から説明する。ＳｉＣ素子１Ａは、接合層５Ａと接続されるカソード電極７Ｃ、アノード電極７Ａ、電極７Ｂ、及びｐ領域やｎ領域を有するＳｉＣ層２５を有している。ＳｉＣ層２５は、カソード電極７Ｃと接しているｎリッチ（ｎ+）領域２０、当該ｎリッチ（ｎ+）領域２０と接しており当該ｎリッチ（ｎ+）領域よりもエレクトロン濃度の薄いｎ領域２１、当該ｎ領域２１内であってＳｉＣ素子１Ａの表面に設けられたｐ領域からなる電界緩和領域３０、及び電極７Ｂが接している領域に設けられているｎリッチ（ｎ+）領域２３から構成される。このｎリッチ（ｎ+）領域２３は、チャネルストッパの役割を果たしており、当該ｎリッチ（ｎ+）領域２３がＳｉＣ素子１Ａの端部にあるため、ｎリッチ（ｎ+）領域２３よりも外部への電界の漏れを抑制できる。 A more detailed structure of the SiC element end portion 120 of FIG. 2 is shown in FIG. First, the specific structure of the SiC element 1A will be described. The SiC element 1A includes a cathode electrode 7C, an anode electrode 7A, an electrode 7B connected to the bonding layer 5A, and an SiC layer 25 having a p region and an n region. The SiC layer 25 is in contact with the n-rich (n + ) region 20 that is in contact with the cathode electrode 7C, and the n region that is in contact with the n-rich (n + ) region 20 and has a lower electron concentration than the n-rich (n + ) region. 21, an electric field relaxation region 30 formed of a p region provided on the surface of the SiC element 1A in the n region 21 and an n-rich (n + ) region 23 provided in a region in contact with the electrode 7B. Composed. The n-rich (n + ) region 23 serves as a channel stopper, and since the n-rich (n + ) region 23 is located at the end of the SiC element 1A, the n-rich (n + ) region 23 is more external than the n-rich (n + ) region 23. The leakage of the electric field to the

本発明に係るＳｉＣ素子１Ａの表面部には、上述したように素子周辺の電界緩和領域３０（ｐ領域で構成されるもので、ガードリングと呼ぶ）が設けられている。なお、本実施形態のように電界緩和領域（ガードリング）３０の濃度を、アノード電極７Ａ側からＳｉＣ素子１Ａの素子端部に向かって、最もホールの濃度が濃い第一のｐ領域、当該第一のｐ領域よりもホールの濃度が低い第二のｐ領域、当該第二のｐ領域よりもさらにホールの濃度が低い第三のｐ領域の順に並べると、半導体素子を作る工程数は増加するが、電界集中を緩和する効果が高まり、シリコーンゲル３の分極を抑制できるので効果的である。   On the surface portion of SiC element 1A according to the present invention, as described above, electric field relaxation region 30 (consisting of a p region and called a guard ring) around the element is provided. Note that, as in the present embodiment, the concentration of the electric field relaxation region (guard ring) 30 is set to the first p region having the highest hole concentration from the anode electrode 7A side toward the element end of the SiC element 1A. When the second p region having a hole concentration lower than that of one p region and the third p region having a hole concentration lower than that of the second p region are arranged in this order, the number of steps for manufacturing a semiconductor element increases. However, the effect of relaxing the electric field concentration is enhanced and the polarization of the silicone gel 3 can be suppressed, which is effective.

この電界緩和領域３０で最も電界が集中するのは第一のｐ領域３０Ａと第二のｐ領域３０Ｂの界面、及び第二のｐ領域３０Ｂと第三のｐ領域３０Ｃの界面である。したがって、素子の大型化を防ぎつつ、十分に素子の耐圧を確保するためには、例えば３.３ｋＶ耐圧のＳｉＣダイオードである場合には、アノード電極７Ａの端部から電界緩和領域３０のＳｉＣ素子端部側（つまり、第三のｐ領域３０Ｃの素子側端部）までの距離Ｌをアノード電極７Ａの端部よりも外側であって、アノード電極７Ａの端部から１０００μｍ以下とするのが好ましい。アノード電極７Ａの端部からの距離を１０００μｍ以下とする理由は、電界集中を防ぐと言う意味では効果的だが、素子自体が大型化してしまうためである。一方で、Ｌをアノード電極７Ａの端部以上とするのは、アノード電極７Ａの端部よりも素子中心部に第三のｐ領域３０Ｃの端部が寄ってしまうと、電界集中を十分に防ぐことができなくなるからである。またより好ましくは、Ｌを２００μｍ〜５００μｍとすると、電界集中を防ぎつつ小型化できるという意味でより好ましい。絶縁破壊電界３００ｋＶ／cm（Ｓｉと同程度まで低下と仮定）、耐圧３.３ｋＶから計算すると３.３／３００＝１１０μｍとなり、信頼性の観点からその２倍程度（２００μｍ程度）は必要となるからである。なお、下記で述べる樹脂や樹脂厚を用いると、２００μｍ以下として小型化したとしても、十分に電界集中による分極を防ぐことが可能となり、小型化と高耐圧性を両立することが可能となる。   The electric field is most concentrated in the electric field relaxation region 30 at the interface between the first p region 30A and the second p region 30B, and the interface between the second p region 30B and the third p region 30C. Therefore, in order to sufficiently secure the breakdown voltage of the element while preventing an increase in the size of the element, for example, when the SiC diode has a breakdown voltage of 3.3 kV, the SiC element in the electric field relaxation region 30 from the end of the anode electrode 7A. The distance L to the end portion side (that is, the element side end portion of the third p region 30C) is preferably outside the end portion of the anode electrode 7A and 1000 μm or less from the end portion of the anode electrode 7A. . The reason why the distance from the end of the anode electrode 7A is set to 1000 μm or less is effective in terms of preventing electric field concentration, but the element itself is enlarged. On the other hand, the reason why L is set to be equal to or greater than the end of the anode electrode 7A is that the electric field concentration is sufficiently prevented when the end of the third p region 30C is closer to the element center than the end of the anode 7A. Because it becomes impossible. More preferably, L is set to 200 μm to 500 μm in the sense that the size can be reduced while preventing electric field concentration. The dielectric breakdown electric field is 300 kV / cm (assumed to be reduced to the same level as Si) and the breakdown voltage is 3.3 kV, which is 3.3 / 300 = 110 μm. From the viewpoint of reliability, about twice that (about 200 μm) is necessary. Because. If the resin and resin thickness described below are used, even if the size is reduced to 200 μm or less, polarization due to electric field concentration can be sufficiently prevented, and both size reduction and high pressure resistance can be achieved.

続いて、電界緩和領域３０上の構成について説明する。電界緩和領域３０及びチャネルストッパ７Ｂ上にＳｉＯ2無機層８が配置されている。これはプラズマＣＶＤ法等による堆積手法で形成可能であるが、本手法に限定されず他の手法で形成してもよい。ＳｉＣ素子では素子周辺の電界緩和領域に発生する電界強度がＳｉ素子に比べ非常に大きくなってしまうので、特性変動を避けるため、高温処理が必要でエネルギー準位を作り易いシリコン窒化膜ではなく、高純度膜を形成可能なシリコン酸化膜（ＳｉＯ2膜）を使っている。また、ＳｉＯ2の誘電率は、４.１となっており、シリコーンゲルの２.７という誘電率に近いものとなっている。各種構成材料の誘電率差が大きいと界面に電荷が蓄積し易くなり、特性変動の原因になる。そのため、無機層８としてシリコーンゲルの誘電率に近いＳｉＯ2を用いると、ＳｉＣ素子１Ａ表面からシリコーンゲル３に至るまでの経路で誘電率の差を小さいものとできるため、特性変動を抑制することが可能となり、分極を抑制でき高耐圧のパワー半導体モジュールを提供できる。 Next, the configuration on the electric field relaxation region 30 will be described. The SiO 2 inorganic layer 8 is disposed on the electric field relaxation region 30 and the channel stopper 7B. This can be formed by a deposition technique such as plasma CVD, but is not limited to this technique and may be formed by another technique. In the SiC element, the electric field intensity generated in the electric field relaxation region around the element becomes very large as compared with the Si element. Therefore, in order to avoid characteristic variation, it is not a silicon nitride film that requires high temperature processing and easily creates an energy level. A silicon oxide film (SiO 2 film) capable of forming a high purity film is used. The dielectric constant of SiO 2 is 4.1, which is close to the dielectric constant of 2.7 of silicone gel. If the difference in dielectric constant between the various constituent materials is large, charges are likely to accumulate at the interface, which causes characteristic fluctuations. Therefore, if SiO 2 close to the dielectric constant of the silicone gel is used as the inorganic layer 8, the difference in dielectric constant can be made small in the path from the surface of the SiC element 1 A to the silicone gel 3. Therefore, polarization can be suppressed and a high breakdown voltage power semiconductor module can be provided.

さらに、無機層８の上には順に、第一の樹脂層２Ａ、第二の樹脂層２Ｂ、シリコーンゲル３が配置される。ＳｉＯ2を使うことで、これら材料の誘電率を狭い範囲に設定することが可能で、さらに、ＳｉＯ2≧第一及び第二の樹脂層≧シリコーンゲルとなるように樹脂材２Ａ及び２Ｂを用いると、さらにＳｉＯ2からシリコーンゲル３に至るまでの誘電率の変化を急激なものではなく、段階的に緩やかに変化させることができるため、より電荷の蓄積による影響を抑えることが可能になる。具体的な材料としては下記で述べるが、例えば第一の樹脂層２Ａにポリイミド（誘電率２.９）を用い、第二の樹脂層２Ｂにポリエーテルアミド（３.２）を用いた場合には、ＳｉＯ2無機層８と第一の樹脂層２Ａとの誘電率の差が１.２、第一の樹脂層２Ａと第二の樹脂層２Ｂとの誘電率の差が０.３、第二の樹脂層２Ｂとシリコーンゲル３の誘電率の差が０.５となるため、非常に誘電率の変化が小さく、電荷の蓄積による影響を抑えることが可能になる。 Furthermore, on the inorganic layer 8, the 1st resin layer 2A, the 2nd resin layer 2B, and the silicone gel 3 are arrange | positioned in order. By using SiO 2 , it is possible to set the dielectric constant of these materials in a narrow range, and furthermore, resin materials 2A and 2B are used so that SiO 2 ≧ first and second resin layers ≧ silicone gel. In addition, since the change in dielectric constant from SiO 2 to the silicone gel 3 can be changed gradually in a stepwise manner, the influence of charge accumulation can be further suppressed. Specific materials are described below. For example, when polyimide (dielectric constant 2.9) is used for the first resin layer 2A and polyether amide (3.2) is used for the second resin layer 2B. The difference in dielectric constant between the SiO 2 inorganic layer 8 and the first resin layer 2A is 1.2, the difference in dielectric constant between the first resin layer 2A and the second resin layer 2B is 0.3, Since the difference in dielectric constant between the second resin layer 2B and the silicone gel 3 is 0.5, the change in the dielectric constant is very small, and it is possible to suppress the influence due to the accumulation of charges.

また、第二の樹脂層２Ｂの厚さを厚くすると、ゲル中の最大電界を低減することができる。図５は、ゲル中に発生する最大電界を解析的に見積もったものである。ＳｉＣ素子を単純にシリコーンゲル封止した場合には（図５の横軸０μｍに相当）、ゲル中にゲル自体の絶縁破壊強度の５倍程度の電界が発生するが、第二の樹脂層２Ｂを設けると劇的に最大電界の抑制が可能となり、第二の樹脂層２Ｂの厚さを５０μｍ以上にするとゲル自体の絶縁破壊強度と同等まで最大電界を抑制することができる。一方で、第二の樹脂層２Ｂの厚さを５００μｍ以上とすると、樹脂自体にクラックが発生しやすくなり、却って素子耐圧性を損なうこととなる。したがって、ＳｉＣ素子１Ａの上に設けられる第二の樹脂層２Ｂの厚さは５０μｍ〜５００μｍとなることが好ましい。より具体的には、電界緩和領域３０内であって、特に電界の集中する第二のｐ領域３０Ｂと第三のｐ領域３０Ｃの界面上部での第二の樹脂層２Ｂの厚さＷを５０μｍ〜５００μｍとすると絶縁性能にも優れ、かつ小型なパワー半導体装置を提供することが可能となる。   Further, when the thickness of the second resin layer 2B is increased, the maximum electric field in the gel can be reduced. FIG. 5 is an analytical estimate of the maximum electric field generated in the gel. When the SiC element is simply sealed with silicone gel (corresponding to 0 μm in FIG. 5), an electric field of about 5 times the dielectric breakdown strength of the gel itself is generated in the gel, but the second resin layer 2B When the thickness of the second resin layer 2B is 50 μm or more, the maximum electric field can be suppressed to the same level as the dielectric breakdown strength of the gel itself. On the other hand, if the thickness of the second resin layer 2B is 500 μm or more, cracks are likely to occur in the resin itself, and the device pressure resistance is impaired. Therefore, the thickness of the second resin layer 2B provided on the SiC element 1A is preferably 50 μm to 500 μm. More specifically, the thickness W of the second resin layer 2B in the electric field relaxation region 30 and particularly in the upper part of the interface between the second p region 30B and the third p region 30C where the electric field is concentrated is 50 μm. When the thickness is ˜500 μm, it is possible to provide a power semiconductor device that is excellent in insulation performance and is small.

続いて、ＳｉＯ2無機層８の上の第一の樹脂層２Ａについて説明する。第一の樹脂層２Ａは高耐熱性を有することが必要なため、ポリイミド樹脂が適当である。スピンコート等で塗布後、加熱硬化、リソグラフィーでパターン化して形成する。膜厚は、１μｍ以下になるとピンホールが発生し易くなって特性が安定せず、一方２０μｍ以上に厚くなると膜応力が大きくなり剥離し易くなるため、１〜２０μｍの膜厚になるよう形成することが必要である。 Next, the first resin layer 2A on the SiO 2 inorganic layer 8 will be described. Since the first resin layer 2A needs to have high heat resistance, a polyimide resin is suitable. After coating by spin coating or the like, it is formed by patterning by heat curing and lithography. When the film thickness is 1 μm or less, pinholes are easily generated and the characteristics are not stable. On the other hand, when the film thickness is 20 μm or more, the film stress increases and the film is easily peeled off. It is necessary.

上記のようにしてＳｉＣ素子を作製したが、以降の工程は図２を使って説明する。ＳｉＣ素子１Ａを、セラミックス回路基板の金属パターン６Ａ１の所定の位置にはんだを含む各種金属接合材料で接合して接合層５Ａを形成する。ＳｉＣ素子１Ａ上面にワイヤーボンディング４を行った後、ディスペンサー等を用いてＳｉＣ素子１Ａ上面全体が濡れるように絶縁性樹脂ワニス（上述した第二の樹脂層２Ｂを構成する樹脂）を滴下する。絶縁性樹脂としては、高耐圧かつ耐熱性樹脂である次の樹脂から選択して使う必要がある。具体的には、ポリアミドイミド樹脂、ポリエーテルアミドイミド樹脂、ポリエーテルアミド樹脂などである。それから加熱処理を行い、ＳｉＣ素子１Ａ上面に第二の樹脂層２Ｂを形成する。絶縁性樹脂ワニスの表面張力と濡れ性のため、形成される皮膜は図２の２Ｂに示すように素子周辺部の電界緩和領域が厚い形状になる。絶縁性樹脂の厚さは、滴下する絶縁性樹脂ワニスの量や濃度で調整することができる。さらに、絶縁性樹脂ワニスをＳｉＣ素子１Ａ上面を越えて外側にも塗布してしまうと絶縁性樹脂厚さの制御が困難になるため、ＳｉＣ素子上面に絶縁性樹脂ワニスを留めることが必要である。   Although the SiC element was manufactured as described above, the subsequent steps will be described with reference to FIG. SiC element 1A is bonded to a predetermined position of metal pattern 6A1 of the ceramic circuit board with various metal bonding materials including solder to form bonding layer 5A. After wire bonding 4 is performed on the upper surface of the SiC element 1A, an insulating resin varnish (resin constituting the second resin layer 2B described above) is dropped using a dispenser or the like so that the entire upper surface of the SiC element 1A is wet. As the insulating resin, it is necessary to select from the following resins that are high pressure resistant and heat resistant resins. Specific examples include polyamide imide resins, polyether amide imide resins, and polyether amide resins. Then, heat treatment is performed to form second resin layer 2B on the upper surface of SiC element 1A. Due to the surface tension and wettability of the insulating resin varnish, the formed film has a thick electric field relaxation region around the element as shown in 2B of FIG. The thickness of the insulating resin can be adjusted by the amount and concentration of the insulating resin varnish to be dropped. Furthermore, if the insulating resin varnish is applied to the outside beyond the upper surface of the SiC element 1A, it becomes difficult to control the thickness of the insulating resin, and therefore it is necessary to keep the insulating resin varnish on the upper surface of the SiC element. .

この後の工程は図１を用いて説明する。素子等部品を搭載したセラミックス回路基板６を放熱ベース１１上にはんだ等で接合し、モジュールケース１０接着、シリコーンゲル３注入・硬化等の所定のプロセスを経てパワー半導体モジュール１００が完成する。   The subsequent steps will be described with reference to FIG. The ceramic circuit board 6 on which components such as elements are mounted is joined to the heat dissipation base 11 with solder or the like, and the power semiconductor module 100 is completed through a predetermined process such as adhesion of the module case 10 and injection / curing of the silicone gel 3.

このように、本実施例によれば、ＳｉＣ素子上面周辺部の電界緩和領域に絶縁性樹脂の厚い皮膜形成が可能になるため、シリコーンゲル中に発生する最大電界は低減し、耐圧特性の安定したＳｉＣ素子搭載パワー半導体モジュールを実現することができる。また、本実施形態では、第一の樹脂層２Ａと第二の樹脂層２Ｂの誘電率の大小関係については言及しなかったが、第二の樹脂層２Ｂの誘電率が第一の樹脂層２Ａの誘電率よりも小さいと電界分布が拡がり、耐圧特性の確保により有利な構成となり、よりシリコーンゲル中に発生する最大電界を低減することができる。   As described above, according to this embodiment, since a thick film of insulating resin can be formed in the electric field relaxation region around the upper surface of the SiC element, the maximum electric field generated in the silicone gel is reduced, and the withstand voltage characteristic is stabilized. An SiC element-mounted power semiconductor module can be realized. In the present embodiment, the magnitude relationship between the dielectric constants of the first resin layer 2A and the second resin layer 2B is not mentioned, but the dielectric constant of the second resin layer 2B is the first resin layer 2A. If the dielectric constant is smaller than the above, the electric field distribution is widened, and it is advantageous in securing the withstand voltage characteristics, and the maximum electric field generated in the silicone gel can be further reduced.

（第二の実施形態）
本発明の第二の実施形態に係るＳｉＣ素子部の模式断面を図４に示す。第一の実施形態と異なるのは、第一の実施形態のＳｉＣ素子部１１０の代わりに、第二の樹脂２ＢをＳｉＣ素子上面周辺部の電界緩和領域３０を含む周辺部のみに配置したＳｉＣ素子部２１０を設けた点である。 (Second embodiment)
FIG. 4 shows a schematic cross section of the SiC element portion according to the second embodiment of the present invention. The difference from the first embodiment is that the SiC element in which the second resin 2B is disposed only in the peripheral portion including the electric field relaxation region 30 in the peripheral portion on the upper surface of the SiC element, instead of the SiC element portion 110 of the first embodiment. The point is that the portion 210 is provided.

ＳｉＣ素子部２１０は、最低限の領域に樹脂材２２５を有した構造をしている。シリコーンゲル３中に最大電界が発生するのは素子上面周辺部の電界緩和領域３０であるため、最低限この領域に絶縁性樹脂皮膜を形成すれば、耐圧特性確保の目的を実現できるからである。   The SiC element part 210 has a structure having a resin material 225 in a minimum area. The reason why the maximum electric field is generated in the silicone gel 3 is the electric field relaxation region 30 at the periphery of the upper surface of the element. Therefore, if the insulating resin film is formed at least in this region, the purpose of ensuring the breakdown voltage characteristic can be realized. .

ＳｉＣ素子端部２２０の詳細な図を図６に示す。樹脂材２２５は、第一の実施形態でも用いられた第一の樹脂層２Ａと、最低限の領域に設けられた第二の樹脂層２２５Ｂをからなる。ここで、言う最小限の領域とは、電界緩和層３０における最もＳｉＣ素子１Ａ中心部に近い領域であり、具体的には、第一のｐ領域のＳｉＣ素子１Ａの中心側の端部２２６である。   A detailed view of the SiC element end 220 is shown in FIG. The resin material 225 includes a first resin layer 2A used in the first embodiment and a second resin layer 225B provided in a minimum area. Here, the minimum region is a region in the electric field relaxation layer 30 that is closest to the center of the SiC element 1A. Specifically, at the end 226 on the center side of the SiC element 1A in the first p region. is there.

続いて、本実施形態に係るＳｉＣ素子端部２２０の形成方法である。ＳｉＣ素子周辺部のみの絶縁性樹脂皮膜形成は、流れ性の低い絶縁性樹脂ペースト（本実施形態の第二の樹脂層２２５Ｂとなる材料）を使い、ディスペンサー等で塗布して行う。但し、この工程はＳｉＣ素子１Ａ上のワイヤーボンディング４を接合する前に行う。絶縁性樹脂ペーストとしては、前記絶縁性樹脂ワニスの高濃度品や高粘度シリコン樹脂を使うことができる。塗布後、加熱処理を行い、ＳｉＣ素子上面周辺部に第二の樹脂２Ｂを形成する。以降の工程は実施例１と同様である。   Then, it is the formation method of the SiC element edge part 220 which concerns on this embodiment. The insulating resin film only on the periphery of the SiC element is formed by applying an insulating resin paste having low flowability (a material that becomes the second resin layer 225B of the present embodiment) with a dispenser or the like. However, this process is performed before bonding the wire bonding 4 on the SiC element 1A. As the insulating resin paste, a high-concentration product of the insulating resin varnish or a high-viscosity silicon resin can be used. After the application, heat treatment is performed to form the second resin 2B around the upper surface of the SiC element. The subsequent steps are the same as in the first embodiment.

このように、本実施形態によれば、シリコーンゲル中に発生する最大電界は低減し、耐圧特性の安定したＳｉＣ素子搭載パワー半導体モジュールを実現し、さらにＳｉＣ素子上面周辺部の電界緩和領域を含む周辺部のみに絶縁性樹脂皮膜を形成するため、樹脂使用量を最小限に抑えることが可能になる。   As described above, according to the present embodiment, the maximum electric field generated in the silicone gel is reduced to realize a SiC element-mounted power semiconductor module having stable breakdown voltage characteristics, and further includes an electric field relaxation region around the upper surface of the SiC element. Since the insulating resin film is formed only on the peripheral portion, the amount of resin used can be minimized.

（第三の実施形態）
本発明の第二の実施形態に係るＳｉＣ素子端部２３０の模式断面を図７に示す。第一の実施形態と異なるのは、電界緩和層の構造である。本実施形態では、電界緩和領域６０を構成する第一のｐ領域６０Ａ、第二のｐ領域６０Ｂ、第三のｐ領域６０Ｃのホール濃度に差を設けず、互いに接しないように配置してある。このように構成することによって、段階的にｐ濃度の差をつけた領域を複数回に分けて設ける必要が無く、簡易にＳｉＣ素子１Ａを作成することができる。なお、本実施形態を用いる場合、距離Ｌとは、アノード電極７Ａから第三のｐ領域６０Ｃの素子外周部側端部２３６との距離を意味し、幅Ｗは第二のｐ領域６０Ｂと第三のｐ領域６０Ｃとの間の領域の中間点２３７を意味する。 (Third embodiment)
FIG. 7 shows a schematic cross section of the SiC element end portion 230 according to the second embodiment of the present invention. The difference from the first embodiment is the structure of the electric field relaxation layer. In the present embodiment, the first p region 60A, the second p region 60B, and the third p region 60C constituting the electric field relaxation region 60 are arranged so as not to contact each other without making a difference in hole concentration. . By configuring in this way, it is not necessary to provide a region with a difference in p concentration in stages, and the SiC element 1A can be easily created. When this embodiment is used, the distance L means the distance from the anode electrode 7A to the element outer peripheral side end 236 of the third p region 60C, and the width W is the second p region 60B and the second p region 60B. This means the middle point 237 of the region between the third p region 60C.

以上、上述したように、本発明を用いることによって、シリコーンゲル中に発生する最大電界を低減し、耐圧特性の安定したＳｉＣ素子搭載パワー半導体モジュールを提供することが可能となる。   As described above, by using the present invention, it is possible to provide an SiC element-mounted power semiconductor module in which the maximum electric field generated in the silicone gel is reduced and the breakdown voltage characteristics are stable.

１Ａ ＳｉＣ素子
１Ｂ Ｓｉ素子
２Ａ 第一の樹脂層
２Ｂ 第二の樹脂層
３ シリコーンゲル
４ ワイヤーボンディング
５ 接合層
６ セラミックス回路基板
６Ａ１、６Ａ２ 配線パターン
６Ｂ セラミックス絶縁板
６Ｃ 金属パターン 1A SiC element 1B Si element 2A First resin layer 2B Second resin layer 3 Silicone gel 4 Wire bonding 5 Bonding layer 6 Ceramic circuit boards 6A1, 6A2 Wiring pattern 6B Ceramic insulating plate 6C Metal pattern

Claims (7)

素子上面周辺部に電界緩和領域を有するＳｉＣからなる半導体素子と、
前記半導体素子を封止するシリコーンゲルと、を有する半導体装置において、
前記電界緩和領域とシリコーンゲルとの間には、ＳｉＯ2から成る無機層と、当該無機層の上部に形成された樹脂層とを有し、
前記樹脂層の誘電率は、前記無機層の誘電率以下であり、且つシリコーンゲルの誘電率以上であり、
前記樹脂層は、前記無機物と直接接触する第一の樹脂層と、当該第一の樹脂層の上に形成された第二の樹脂層からなり、
前記第二の樹脂層の厚みは前記第一の樹脂層の厚みよりも厚いことを特徴とする半導体装置。 A semiconductor element made of SiC having an electric field relaxation region around the upper surface of the element;
In a semiconductor device having a silicone gel for sealing the semiconductor element,
Between the electric field relaxation region and the silicone gel, an inorganic layer made of SiO 2 and a resin layer formed on the inorganic layer,
The dielectric constant of the resin layer is less than or equal to the dielectric constant of the inorganic layer state, and are and more the dielectric constant of silicone gel,
The resin layer comprises a first resin layer that is in direct contact with the inorganic material, and a second resin layer formed on the first resin layer,
The semiconductor device according to claim 1, wherein the second resin layer has a thickness greater than that of the first resin layer . 請求項１に記載の半導体装置において、
前記第二の樹脂層の厚さは５０μｍ以上５００μｍ以下であることを特徴とする半導体装置。 The semiconductor device according to claim 1 ,
A thickness of the second resin layer is not less than 50 μm and not more than 500 μm. 請求項１または２に記載の半導体装置において、
前記第二の樹脂層はポリアミドイミド樹脂、ポリエーテルアミドイミド樹脂、ポリエーテルアミド樹脂から選ばれる一種あるいは複数種類で構成されていることを特徴とする半導体装置。 The semiconductor device according to claim 1 or 2 ,
The semiconductor device, wherein the second resin layer is composed of one kind or plural kinds selected from a polyamideimide resin, a polyetheramideimide resin, and a polyetheramide resin. 請求項１乃至３のいずれかに記載の半導体装置において、
前記第一の樹脂層の厚さは１μｍ以上２０μｍ以下であることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 3 ,
The semiconductor device according to claim 1, wherein the first resin layer has a thickness of 1 μm to 20 μm. 請求項１乃至４のいずれかに記載の半導体装置において、
前記第一の樹脂層はポリイミド樹脂であることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 4,
The semiconductor device, wherein the first resin layer is a polyimide resin. 請求項１または２に記載の半導体装置において、
前記第二の樹脂層は、前記第一の樹脂層の誘電率よりも小さいことを特徴とする半導体装置。 The semiconductor device according to claim 1 or 2 ,
The semiconductor device, wherein the second resin layer has a dielectric constant smaller than that of the first resin layer. 請求項１乃至６のいずれかに記載の半導体装置において、
前記電界緩和領域は濃度の異なる複数のｐ領域で構成されることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 6,
The semiconductor device, wherein the electric field relaxation region is composed of a plurality of p regions having different concentrations.
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