JP5600698B2 - Power semiconductor module with SiC element - Google Patents
Power semiconductor module with SiC element Download PDFInfo
- Publication number
- JP5600698B2 JP5600698B2 JP2012056618A JP2012056618A JP5600698B2 JP 5600698 B2 JP5600698 B2 JP 5600698B2 JP 2012056618 A JP2012056618 A JP 2012056618A JP 2012056618 A JP2012056618 A JP 2012056618A JP 5600698 B2 JP5600698 B2 JP 5600698B2
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- electric field
- semiconductor device
- region
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本発明は、SiC素子を搭載した高耐圧パワー半導体モジュールのSiC素子実装構造に関する。 The present invention relates to a SiC element mounting structure of a high withstand voltage power semiconductor module equipped with a SiC element.
省エネルギー化、省資源、環境保全などへの規制・要請を背景に、パワー半導体モジュールを用いた電力制御システムが不可欠なものになっている。特に、近年より小型で耐圧性に優れたパワー半導体モジュールの開発が求められている。しかし、パワー半導体モジュールを小型化して高耐圧の用途で用いようとすると、電位の分布が集中してしまう素子端部で、絶縁破壊が起こってしまう。 Power control systems using power semiconductor modules have become indispensable against the background of regulations and requests for energy saving, resource saving, environmental conservation, and the like. In particular, in recent years, there has been a demand for the development of power semiconductor modules that are smaller and have superior pressure resistance. However, if the power semiconductor module is miniaturized and used for high withstand voltage applications, dielectric breakdown occurs at the end of the element where the potential distribution is concentrated.
そこで、従来の素子では、素子上面周辺領域を取り囲むようにガードリングを形成し、電位分布を安定化させることで主耐圧特性を確保している。特許文献1には、主耐圧特性等が悪化するのを防止するため、ガードリング上にシリコン窒化膜を形成し、さらにオーバーコート膜を形成することが記載されている。また、近年より高耐圧性に優れたSiC素子やGaN素子を含むワイドギャップ半導体素子の開発が進められている。特にSiC素子は、高耐圧性に優れた材料物性から高耐圧用途への展開に有利であり、このような素子を用いたパワー半導体装置の開発が進められている。 Therefore, in the conventional element, the main breakdown voltage characteristic is ensured by forming a guard ring so as to surround the peripheral area of the upper surface of the element and stabilizing the potential distribution. Patent Document 1 describes that a silicon nitride film is formed on a guard ring and an overcoat film is formed on the guard ring in order to prevent deterioration of main breakdown voltage characteristics and the like. In recent years, development of wide gap semiconductor elements including SiC elements and GaN elements having excellent high voltage resistance has been promoted. In particular, SiC elements are advantageous for the development of materials having excellent high voltage resistance to high voltage applications, and power semiconductor devices using such elements are being developed.
一方、特許文献1に記載のパワー半導体モジュールで、素子をSiC素子とした場合、SiC素子では、デバイス内部の電界がSiよりも約10倍大きくなるため、周辺電界緩和領域に発生する電界強度はSi素子に比べて非常に大きくなってしまう。図5は、ゲル中に発生する最大電界を解析的に見積もったものである。SiC素子を単純にシリコーンゲル封止した場合には(図5の横軸0μmに相当)、ゲル中にゲル自体の絶縁破壊強度の5倍程度の電界が発生することを示している。このため、SiC素子を用いた場合に安定した耐圧特性を確保するためにはゲル中の最大電界を低減させることが必要である。 On the other hand, in the power semiconductor module described in Patent Document 1, when the element is a SiC element, in the SiC element, the electric field inside the device is about 10 times larger than that of Si. It becomes very large compared with the Si element. FIG. 5 is an analytical estimate of the maximum electric field generated in the gel. When the SiC element is simply sealed with silicone gel (corresponding to 0 μm on the horizontal axis in FIG. 5), an electric field of about 5 times the dielectric breakdown strength of the gel itself is generated in the gel. For this reason, it is necessary to reduce the maximum electric field in the gel in order to ensure a stable breakdown voltage characteristic when the SiC element is used.
したがって、本発明では上記課題に鑑み、SiC素子端部の耐圧特性を確保したSiC素子搭載パワー半導体モジュールを提供することを目的とする。 Therefore, in view of the above problems, an object of the present invention is to provide an SiC element-mounted power semiconductor module that ensures the breakdown voltage characteristics of the SiC element end.
上記課題を解決するために、本発明に係るパワー半導体モジュールは、素子上面周辺部に電界緩和領域を有するSiCからなる半導体素子と、前記半導体素子を封止するシリコーンゲルと、を有する半導体装置において、前記電界緩和領域とシリコーンゲルとの間には、SiO2から成る無機層と、当該無機層の上部に形成された樹脂層とを有し、前記樹脂層の誘電率は、前記無機層の誘電率以下であり、且つシリコーンゲルの誘電率以上であることを特徴とする。 In order to solve the above-described problems, a power semiconductor module according to the present invention is a semiconductor device having a semiconductor element made of SiC having an electric field relaxation region at the periphery of the upper surface of the element, and a silicone gel for sealing the semiconductor element. In addition, between the electric field relaxation region and the silicone gel, there is an inorganic layer made of SiO 2 and a resin layer formed on the inorganic layer, and the dielectric constant of the resin layer is that of the inorganic layer. It is characterized by being below the dielectric constant and above the dielectric constant of the silicone gel.
本発明によれば、SiC素子端部の耐圧特性を確保したSiC素子搭載パワー半導体モジュールを提供することができる。 ADVANTAGE OF THE INVENTION According to this invention, the SiC element mounting power semiconductor module which ensured the pressure | voltage resistant characteristic of the SiC element edge part can be provided.
以下、本発明の実施例を図面に基づき説明する。 Embodiments of the present invention will be described below with reference to the drawings.
(第一の実施形態)
本発明に係るSiC素子搭載パワー半導体モジュール100の模式断面を図1に示す。本発明が対象とするSiC素子搭載パワー半導体モジュールは、SiC素子がスイッチング素子として搭載されていても良いし、フリーホイールダイオード素子として搭載されていても良いし、両方の素子として搭載されていても良い。
(First embodiment)
FIG. 1 shows a schematic cross section of an SiC element-mounted power semiconductor module 100 according to the present invention. The SiC element-mounted power semiconductor module targeted by the present invention may be mounted with a SiC element as a switching element, a free wheel diode element, or both elements. good.
図1では、IGBTにSi素子を用い、ダイオードにSiC素子を用いたものを例に説明する。本実施形態に係るパワー半導体モジュール100は、放熱ベース11、セラミックス回路基板6、SiC素子(ダイオード)1A、Si素子(IGBT)1B、外部出力端子9A、9B、及びモジュールケース10を有している。セラミックス回路基板6は、一方の面に、SiC素子1A、Si素子1Bと接続される配線パターン6A1及び外部出力端子9Bが接続される6A2が設けられ、他方の面に、放熱ベース11と接続される金属パターン6Cを有している。金属パターン6Cと放熱ベース11とは、はんだもしくは金属ペーストを焼結した接合層5Bを介して接合される。一方、配線パターン6A1とSiC素子1A及びSi素子1Bは、はんだもしくは金属ペーストを焼結した接合層5Aを介して接合される。また、正極側と接続される外部出力端子9A(9)は、配線パターン6A1(6A)と直接超音波接合で接合されており、負極側と接続される外部出力端子9B(9)は、配線パターン6A2(6A)と直接超音波接合で接合されている。なお、ここでは外部出力端子9と配線パターン6との接続は超音波接合としたが、他の接合方法を用いても良いのは言うまでもない。 In FIG. 1, an example in which a Si element is used for the IGBT and a SiC element is used for the diode will be described. A power semiconductor module 100 according to this embodiment includes a heat dissipation base 11, a ceramic circuit board 6, a SiC element (diode) 1A, a Si element (IGBT) 1B, external output terminals 9A and 9B, and a module case 10. . The ceramic circuit board 6 is provided with a wiring pattern 6A1 connected to the SiC element 1A and the Si element 1B and 6A2 connected to the external output terminal 9B on one surface, and connected to the heat dissipation base 11 on the other surface. A metal pattern 6C. The metal pattern 6C and the heat dissipation base 11 are bonded via a bonding layer 5B obtained by sintering solder or metal paste. On the other hand, the wiring pattern 6A1, the SiC element 1A, and the Si element 1B are bonded via a bonding layer 5A obtained by sintering solder or metal paste. Further, the external output terminal 9A (9) connected to the positive electrode side is directly joined to the wiring pattern 6A1 (6A) by ultrasonic bonding, and the external output terminal 9B (9) connected to the negative electrode side is connected to the wiring pattern 6A1 (6A). It is joined to the pattern 6A2 (6A) by direct ultrasonic joining. Here, the connection between the external output terminal 9 and the wiring pattern 6 is ultrasonic bonding, but it goes without saying that other bonding methods may be used.
この外部出力端子9A及び9Bは、モジュールケース10の外部に引き出されて他の機器と接続される。 The external output terminals 9A and 9B are drawn out of the module case 10 and connected to other devices.
SiC素子1A及びSi素子1Bにおける配線パターン6A1側と反対側の面は、ボンディングワイヤ4を介して、外部出力端子9Bが接続される配線パターン6A2に接続されている。なお、SiC素子1Aの詳細構造については、下記で詳細に説明する。 The surface opposite to the wiring pattern 6A1 side of the SiC element 1A and the Si element 1B is connected via a bonding wire 4 to a wiring pattern 6A2 to which the external output terminal 9B is connected. The detailed structure of SiC element 1A will be described in detail below.
モジュールケース10は、放熱ベース11に固定されており、内部がシリコーンゲル3で満たされている。 The module case 10 is fixed to the heat dissipation base 11, and the inside is filled with the silicone gel 3.
図2は図1のSiC素子搭載部110を拡大したものである。SiC素子1Aの表面には樹脂材2が塗布されており、SiC素子1Aの端部の樹脂材2の厚さが厚くなった構造をしている。この構造が本発明の一つの特徴となっている。 FIG. 2 is an enlarged view of the SiC element mounting portion 110 of FIG. Resin material 2 is applied to the surface of SiC element 1A, and the thickness of resin material 2 at the end of SiC element 1A is increased. This structure is one of the features of the present invention.
図2のSiC素子端部120のより詳細な構造を図3に示す。まず、SiC素子1Aの具体的な構造から説明する。SiC素子1Aは、接合層5Aと接続されるカソード電極7C、アノード電極7A、電極7B、及びp領域やn領域を有するSiC層25を有している。SiC層25は、カソード電極7Cと接しているnリッチ(n+)領域20、当該nリッチ(n+)領域20と接しており当該nリッチ(n+)領域よりもエレクトロン濃度の薄いn領域21、当該n領域21内であってSiC素子1Aの表面に設けられたp領域からなる電界緩和領域30、及び電極7Bが接している領域に設けられているnリッチ(n+)領域23から構成される。このnリッチ(n+)領域23は、チャネルストッパの役割を果たしており、当該nリッチ(n+)領域23がSiC素子1Aの端部にあるため、nリッチ(n+)領域23よりも外部への電界の漏れを抑制できる。 A more detailed structure of the SiC element end portion 120 of FIG. 2 is shown in FIG. First, the specific structure of the SiC element 1A will be described. The SiC element 1A includes a cathode electrode 7C, an anode electrode 7A, an electrode 7B connected to the bonding layer 5A, and an SiC layer 25 having a p region and an n region. The SiC layer 25 is in contact with the n-rich (n + ) region 20 that is in contact with the cathode electrode 7C, and the n region that is in contact with the n-rich (n + ) region 20 and has a lower electron concentration than the n-rich (n + ) region. 21, an electric field relaxation region 30 formed of a p region provided on the surface of the SiC element 1A in the n region 21 and an n-rich (n + ) region 23 provided in a region in contact with the electrode 7B. Composed. The n-rich (n + ) region 23 serves as a channel stopper, and since the n-rich (n + ) region 23 is located at the end of the SiC element 1A, the n-rich (n + ) region 23 is more external than the n-rich (n + ) region 23. The leakage of the electric field to the
本発明に係るSiC素子1Aの表面部には、上述したように素子周辺の電界緩和領域30(p領域で構成されるもので、ガードリングと呼ぶ)が設けられている。なお、本実施形態のように電界緩和領域(ガードリング)30の濃度を、アノード電極7A側からSiC素子1Aの素子端部に向かって、最もホールの濃度が濃い第一のp領域、当該第一のp領域よりもホールの濃度が低い第二のp領域、当該第二のp領域よりもさらにホールの濃度が低い第三のp領域の順に並べると、半導体素子を作る工程数は増加するが、電界集中を緩和する効果が高まり、シリコーンゲル3の分極を抑制できるので効果的である。 On the surface portion of SiC element 1A according to the present invention, as described above, electric field relaxation region 30 (consisting of a p region and called a guard ring) around the element is provided. Note that, as in the present embodiment, the concentration of the electric field relaxation region (guard ring) 30 is set to the first p region having the highest hole concentration from the anode electrode 7A side toward the element end of the SiC element 1A. When the second p region having a hole concentration lower than that of one p region and the third p region having a hole concentration lower than that of the second p region are arranged in this order, the number of steps for manufacturing a semiconductor element increases. However, the effect of relaxing the electric field concentration is enhanced and the polarization of the silicone gel 3 can be suppressed, which is effective.
この電界緩和領域30で最も電界が集中するのは第一のp領域30Aと第二のp領域30Bの界面、及び第二のp領域30Bと第三のp領域30Cの界面である。したがって、素子の大型化を防ぎつつ、十分に素子の耐圧を確保するためには、例えば3.3kV耐圧のSiCダイオードである場合には、アノード電極7Aの端部から電界緩和領域30のSiC素子端部側(つまり、第三のp領域30Cの素子側端部)までの距離Lをアノード電極7Aの端部よりも外側であって、アノード電極7Aの端部から1000μm以下とするのが好ましい。アノード電極7Aの端部からの距離を1000μm以下とする理由は、電界集中を防ぐと言う意味では効果的だが、素子自体が大型化してしまうためである。一方で、Lをアノード電極7Aの端部以上とするのは、アノード電極7Aの端部よりも素子中心部に第三のp領域30Cの端部が寄ってしまうと、電界集中を十分に防ぐことができなくなるからである。またより好ましくは、Lを200μm〜500μmとすると、電界集中を防ぎつつ小型化できるという意味でより好ましい。絶縁破壊電界300kV/cm(Siと同程度まで低下と仮定)、耐圧3.3kVから計算すると3.3/300=110μmとなり、信頼性の観点からその2倍程度(200μm程度)は必要となるからである。なお、下記で述べる樹脂や樹脂厚を用いると、200μm以下として小型化したとしても、十分に電界集中による分極を防ぐことが可能となり、小型化と高耐圧性を両立することが可能となる。 The electric field is most concentrated in the electric field relaxation region 30 at the interface between the first p region 30A and the second p region 30B, and the interface between the second p region 30B and the third p region 30C. Therefore, in order to sufficiently secure the breakdown voltage of the element while preventing an increase in the size of the element, for example, when the SiC diode has a breakdown voltage of 3.3 kV, the SiC element in the electric field relaxation region 30 from the end of the anode electrode 7A. The distance L to the end portion side (that is, the element side end portion of the third p region 30C) is preferably outside the end portion of the anode electrode 7A and 1000 μm or less from the end portion of the anode electrode 7A. . The reason why the distance from the end of the anode electrode 7A is set to 1000 μm or less is effective in terms of preventing electric field concentration, but the element itself is enlarged. On the other hand, the reason why L is set to be equal to or greater than the end of the anode electrode 7A is that the electric field concentration is sufficiently prevented when the end of the third p region 30C is closer to the element center than the end of the anode 7A. Because it becomes impossible. More preferably, L is set to 200 μm to 500 μm in the sense that the size can be reduced while preventing electric field concentration. The dielectric breakdown electric field is 300 kV / cm (assumed to be reduced to the same level as Si) and the breakdown voltage is 3.3 kV, which is 3.3 / 300 = 110 μm. From the viewpoint of reliability, about twice that (about 200 μm) is necessary. Because. If the resin and resin thickness described below are used, even if the size is reduced to 200 μm or less, polarization due to electric field concentration can be sufficiently prevented, and both size reduction and high pressure resistance can be achieved.
続いて、電界緩和領域30上の構成について説明する。電界緩和領域30及びチャネルストッパ7B上にSiO2無機層8が配置されている。これはプラズマCVD法等による堆積手法で形成可能であるが、本手法に限定されず他の手法で形成してもよい。SiC素子では素子周辺の電界緩和領域に発生する電界強度がSi素子に比べ非常に大きくなってしまうので、特性変動を避けるため、高温処理が必要でエネルギー準位を作り易いシリコン窒化膜ではなく、高純度膜を形成可能なシリコン酸化膜(SiO2膜)を使っている。また、SiO2の誘電率は、4.1となっており、シリコーンゲルの2.7という誘電率に近いものとなっている。各種構成材料の誘電率差が大きいと界面に電荷が蓄積し易くなり、特性変動の原因になる。そのため、無機層8としてシリコーンゲルの誘電率に近いSiO2を用いると、SiC素子1A表面からシリコーンゲル3に至るまでの経路で誘電率の差を小さいものとできるため、特性変動を抑制することが可能となり、分極を抑制でき高耐圧のパワー半導体モジュールを提供できる。 Next, the configuration on the electric field relaxation region 30 will be described. The SiO 2 inorganic layer 8 is disposed on the electric field relaxation region 30 and the channel stopper 7B. This can be formed by a deposition technique such as plasma CVD, but is not limited to this technique and may be formed by another technique. In the SiC element, the electric field intensity generated in the electric field relaxation region around the element becomes very large as compared with the Si element. Therefore, in order to avoid characteristic variation, it is not a silicon nitride film that requires high temperature processing and easily creates an energy level. A silicon oxide film (SiO 2 film) capable of forming a high purity film is used. The dielectric constant of SiO 2 is 4.1, which is close to the dielectric constant of 2.7 of silicone gel. If the difference in dielectric constant between the various constituent materials is large, charges are likely to accumulate at the interface, which causes characteristic fluctuations. Therefore, if SiO 2 close to the dielectric constant of the silicone gel is used as the inorganic layer 8, the difference in dielectric constant can be made small in the path from the surface of the SiC element 1 A to the silicone gel 3. Therefore, polarization can be suppressed and a high breakdown voltage power semiconductor module can be provided.
さらに、無機層8の上には順に、第一の樹脂層2A、第二の樹脂層2B、シリコーンゲル3が配置される。SiO2を使うことで、これら材料の誘電率を狭い範囲に設定することが可能で、さらに、SiO2≧第一及び第二の樹脂層≧シリコーンゲルとなるように樹脂材2A及び2Bを用いると、さらにSiO2からシリコーンゲル3に至るまでの誘電率の変化を急激なものではなく、段階的に緩やかに変化させることができるため、より電荷の蓄積による影響を抑えることが可能になる。具体的な材料としては下記で述べるが、例えば第一の樹脂層2Aにポリイミド(誘電率2.9)を用い、第二の樹脂層2Bにポリエーテルアミド(3.2)を用いた場合には、SiO2無機層8と第一の樹脂層2Aとの誘電率の差が1.2、第一の樹脂層2Aと第二の樹脂層2Bとの誘電率の差が0.3、第二の樹脂層2Bとシリコーンゲル3の誘電率の差が0.5となるため、非常に誘電率の変化が小さく、電荷の蓄積による影響を抑えることが可能になる。 Furthermore, on the inorganic layer 8, the 1st resin layer 2A, the 2nd resin layer 2B, and the silicone gel 3 are arrange | positioned in order. By using SiO 2 , it is possible to set the dielectric constant of these materials in a narrow range, and furthermore, resin materials 2A and 2B are used so that SiO 2 ≧ first and second resin layers ≧ silicone gel. In addition, since the change in dielectric constant from SiO 2 to the silicone gel 3 can be changed gradually in a stepwise manner, the influence of charge accumulation can be further suppressed. Specific materials are described below. For example, when polyimide (dielectric constant 2.9) is used for the first resin layer 2A and polyether amide (3.2) is used for the second resin layer 2B. The difference in dielectric constant between the SiO 2 inorganic layer 8 and the first resin layer 2A is 1.2, the difference in dielectric constant between the first resin layer 2A and the second resin layer 2B is 0.3, Since the difference in dielectric constant between the second resin layer 2B and the silicone gel 3 is 0.5, the change in the dielectric constant is very small, and it is possible to suppress the influence due to the accumulation of charges.
また、第二の樹脂層2Bの厚さを厚くすると、ゲル中の最大電界を低減することができる。図5は、ゲル中に発生する最大電界を解析的に見積もったものである。SiC素子を単純にシリコーンゲル封止した場合には(図5の横軸0μmに相当)、ゲル中にゲル自体の絶縁破壊強度の5倍程度の電界が発生するが、第二の樹脂層2Bを設けると劇的に最大電界の抑制が可能となり、第二の樹脂層2Bの厚さを50μm以上にするとゲル自体の絶縁破壊強度と同等まで最大電界を抑制することができる。一方で、第二の樹脂層2Bの厚さを500μm以上とすると、樹脂自体にクラックが発生しやすくなり、却って素子耐圧性を損なうこととなる。したがって、SiC素子1Aの上に設けられる第二の樹脂層2Bの厚さは50μm〜500μmとなることが好ましい。より具体的には、電界緩和領域30内であって、特に電界の集中する第二のp領域30Bと第三のp領域30Cの界面上部での第二の樹脂層2Bの厚さWを50μm〜500μmとすると絶縁性能にも優れ、かつ小型なパワー半導体装置を提供することが可能となる。 Further, when the thickness of the second resin layer 2B is increased, the maximum electric field in the gel can be reduced. FIG. 5 is an analytical estimate of the maximum electric field generated in the gel. When the SiC element is simply sealed with silicone gel (corresponding to 0 μm in FIG. 5), an electric field of about 5 times the dielectric breakdown strength of the gel itself is generated in the gel, but the second resin layer 2B When the thickness of the second resin layer 2B is 50 μm or more, the maximum electric field can be suppressed to the same level as the dielectric breakdown strength of the gel itself. On the other hand, if the thickness of the second resin layer 2B is 500 μm or more, cracks are likely to occur in the resin itself, and the device pressure resistance is impaired. Therefore, the thickness of the second resin layer 2B provided on the SiC element 1A is preferably 50 μm to 500 μm. More specifically, the thickness W of the second resin layer 2B in the electric field relaxation region 30 and particularly in the upper part of the interface between the second p region 30B and the third p region 30C where the electric field is concentrated is 50 μm. When the thickness is ˜500 μm, it is possible to provide a power semiconductor device that is excellent in insulation performance and is small.
続いて、SiO2無機層8の上の第一の樹脂層2Aについて説明する。第一の樹脂層2Aは高耐熱性を有することが必要なため、ポリイミド樹脂が適当である。スピンコート等で塗布後、加熱硬化、リソグラフィーでパターン化して形成する。膜厚は、1μm以下になるとピンホールが発生し易くなって特性が安定せず、一方20μm以上に厚くなると膜応力が大きくなり剥離し易くなるため、1〜20μmの膜厚になるよう形成することが必要である。 Next, the first resin layer 2A on the SiO 2 inorganic layer 8 will be described. Since the first resin layer 2A needs to have high heat resistance, a polyimide resin is suitable. After coating by spin coating or the like, it is formed by patterning by heat curing and lithography. When the film thickness is 1 μm or less, pinholes are easily generated and the characteristics are not stable. On the other hand, when the film thickness is 20 μm or more, the film stress increases and the film is easily peeled off. It is necessary.
上記のようにしてSiC素子を作製したが、以降の工程は図2を使って説明する。SiC素子1Aを、セラミックス回路基板の金属パターン6A1の所定の位置にはんだを含む各種金属接合材料で接合して接合層5Aを形成する。SiC素子1A上面にワイヤーボンディング4を行った後、ディスペンサー等を用いてSiC素子1A上面全体が濡れるように絶縁性樹脂ワニス(上述した第二の樹脂層2Bを構成する樹脂)を滴下する。絶縁性樹脂としては、高耐圧かつ耐熱性樹脂である次の樹脂から選択して使う必要がある。具体的には、ポリアミドイミド樹脂、ポリエーテルアミドイミド樹脂、ポリエーテルアミド樹脂などである。それから加熱処理を行い、SiC素子1A上面に第二の樹脂層2Bを形成する。絶縁性樹脂ワニスの表面張力と濡れ性のため、形成される皮膜は図2の2Bに示すように素子周辺部の電界緩和領域が厚い形状になる。絶縁性樹脂の厚さは、滴下する絶縁性樹脂ワニスの量や濃度で調整することができる。さらに、絶縁性樹脂ワニスをSiC素子1A上面を越えて外側にも塗布してしまうと絶縁性樹脂厚さの制御が困難になるため、SiC素子上面に絶縁性樹脂ワニスを留めることが必要である。 Although the SiC element was manufactured as described above, the subsequent steps will be described with reference to FIG. SiC element 1A is bonded to a predetermined position of metal pattern 6A1 of the ceramic circuit board with various metal bonding materials including solder to form bonding layer 5A. After wire bonding 4 is performed on the upper surface of the SiC element 1A, an insulating resin varnish (resin constituting the second resin layer 2B described above) is dropped using a dispenser or the like so that the entire upper surface of the SiC element 1A is wet. As the insulating resin, it is necessary to select from the following resins that are high pressure resistant and heat resistant resins. Specific examples include polyamide imide resins, polyether amide imide resins, and polyether amide resins. Then, heat treatment is performed to form second resin layer 2B on the upper surface of SiC element 1A. Due to the surface tension and wettability of the insulating resin varnish, the formed film has a thick electric field relaxation region around the element as shown in 2B of FIG. The thickness of the insulating resin can be adjusted by the amount and concentration of the insulating resin varnish to be dropped. Furthermore, if the insulating resin varnish is applied to the outside beyond the upper surface of the SiC element 1A, it becomes difficult to control the thickness of the insulating resin, and therefore it is necessary to keep the insulating resin varnish on the upper surface of the SiC element. .
この後の工程は図1を用いて説明する。素子等部品を搭載したセラミックス回路基板6を放熱ベース11上にはんだ等で接合し、モジュールケース10接着、シリコーンゲル3注入・硬化等の所定のプロセスを経てパワー半導体モジュール100が完成する。 The subsequent steps will be described with reference to FIG. The ceramic circuit board 6 on which components such as elements are mounted is joined to the heat dissipation base 11 with solder or the like, and the power semiconductor module 100 is completed through a predetermined process such as adhesion of the module case 10 and injection / curing of the silicone gel 3.
このように、本実施例によれば、SiC素子上面周辺部の電界緩和領域に絶縁性樹脂の厚い皮膜形成が可能になるため、シリコーンゲル中に発生する最大電界は低減し、耐圧特性の安定したSiC素子搭載パワー半導体モジュールを実現することができる。また、本実施形態では、第一の樹脂層2Aと第二の樹脂層2Bの誘電率の大小関係については言及しなかったが、第二の樹脂層2Bの誘電率が第一の樹脂層2Aの誘電率よりも小さいと電界分布が拡がり、耐圧特性の確保により有利な構成となり、よりシリコーンゲル中に発生する最大電界を低減することができる。 As described above, according to this embodiment, since a thick film of insulating resin can be formed in the electric field relaxation region around the upper surface of the SiC element, the maximum electric field generated in the silicone gel is reduced, and the withstand voltage characteristic is stabilized. An SiC element-mounted power semiconductor module can be realized. In the present embodiment, the magnitude relationship between the dielectric constants of the first resin layer 2A and the second resin layer 2B is not mentioned, but the dielectric constant of the second resin layer 2B is the first resin layer 2A. If the dielectric constant is smaller than the above, the electric field distribution is widened, and it is advantageous in securing the withstand voltage characteristics, and the maximum electric field generated in the silicone gel can be further reduced.
(第二の実施形態)
本発明の第二の実施形態に係るSiC素子部の模式断面を図4に示す。第一の実施形態と異なるのは、第一の実施形態のSiC素子部110の代わりに、第二の樹脂2BをSiC素子上面周辺部の電界緩和領域30を含む周辺部のみに配置したSiC素子部210を設けた点である。
(Second embodiment)
FIG. 4 shows a schematic cross section of the SiC element portion according to the second embodiment of the present invention. The difference from the first embodiment is that the SiC element in which the second resin 2B is disposed only in the peripheral portion including the electric field relaxation region 30 in the peripheral portion on the upper surface of the SiC element, instead of the SiC element portion 110 of the first embodiment. The point is that the portion 210 is provided.
SiC素子部210は、最低限の領域に樹脂材225を有した構造をしている。シリコーンゲル3中に最大電界が発生するのは素子上面周辺部の電界緩和領域30であるため、最低限この領域に絶縁性樹脂皮膜を形成すれば、耐圧特性確保の目的を実現できるからである。 The SiC element part 210 has a structure having a resin material 225 in a minimum area. The reason why the maximum electric field is generated in the silicone gel 3 is the electric field relaxation region 30 at the periphery of the upper surface of the element. Therefore, if the insulating resin film is formed at least in this region, the purpose of ensuring the breakdown voltage characteristic can be realized. .
SiC素子端部220の詳細な図を図6に示す。樹脂材225は、第一の実施形態でも用いられた第一の樹脂層2Aと、最低限の領域に設けられた第二の樹脂層225Bをからなる。ここで、言う最小限の領域とは、電界緩和層30における最もSiC素子1A中心部に近い領域であり、具体的には、第一のp領域のSiC素子1Aの中心側の端部226である。 A detailed view of the SiC element end 220 is shown in FIG. The resin material 225 includes a first resin layer 2A used in the first embodiment and a second resin layer 225B provided in a minimum area. Here, the minimum region is a region in the electric field relaxation layer 30 that is closest to the center of the SiC element 1A. Specifically, at the end 226 on the center side of the SiC element 1A in the first p region. is there.
続いて、本実施形態に係るSiC素子端部220の形成方法である。SiC素子周辺部のみの絶縁性樹脂皮膜形成は、流れ性の低い絶縁性樹脂ペースト(本実施形態の第二の樹脂層225Bとなる材料)を使い、ディスペンサー等で塗布して行う。但し、この工程はSiC素子1A上のワイヤーボンディング4を接合する前に行う。絶縁性樹脂ペーストとしては、前記絶縁性樹脂ワニスの高濃度品や高粘度シリコン樹脂を使うことができる。塗布後、加熱処理を行い、SiC素子上面周辺部に第二の樹脂2Bを形成する。以降の工程は実施例1と同様である。 Then, it is the formation method of the SiC element edge part 220 which concerns on this embodiment. The insulating resin film only on the periphery of the SiC element is formed by applying an insulating resin paste having low flowability (a material that becomes the second resin layer 225B of the present embodiment) with a dispenser or the like. However, this process is performed before bonding the wire bonding 4 on the SiC element 1A. As the insulating resin paste, a high-concentration product of the insulating resin varnish or a high-viscosity silicon resin can be used. After the application, heat treatment is performed to form the second resin 2B around the upper surface of the SiC element. The subsequent steps are the same as in the first embodiment.
このように、本実施形態によれば、シリコーンゲル中に発生する最大電界は低減し、耐圧特性の安定したSiC素子搭載パワー半導体モジュールを実現し、さらにSiC素子上面周辺部の電界緩和領域を含む周辺部のみに絶縁性樹脂皮膜を形成するため、樹脂使用量を最小限に抑えることが可能になる。 As described above, according to the present embodiment, the maximum electric field generated in the silicone gel is reduced to realize a SiC element-mounted power semiconductor module having stable breakdown voltage characteristics, and further includes an electric field relaxation region around the upper surface of the SiC element. Since the insulating resin film is formed only on the peripheral portion, the amount of resin used can be minimized.
(第三の実施形態)
本発明の第二の実施形態に係るSiC素子端部230の模式断面を図7に示す。第一の実施形態と異なるのは、電界緩和層の構造である。本実施形態では、電界緩和領域60を構成する第一のp領域60A、第二のp領域60B、第三のp領域60Cのホール濃度に差を設けず、互いに接しないように配置してある。このように構成することによって、段階的にp濃度の差をつけた領域を複数回に分けて設ける必要が無く、簡易にSiC素子1Aを作成することができる。なお、本実施形態を用いる場合、距離Lとは、アノード電極7Aから第三のp領域60Cの素子外周部側端部236との距離を意味し、幅Wは第二のp領域60Bと第三のp領域60Cとの間の領域の中間点237を意味する。
(Third embodiment)
FIG. 7 shows a schematic cross section of the SiC element end portion 230 according to the second embodiment of the present invention. The difference from the first embodiment is the structure of the electric field relaxation layer. In the present embodiment, the first p region 60A, the second p region 60B, and the third p region 60C constituting the electric field relaxation region 60 are arranged so as not to contact each other without making a difference in hole concentration. . By configuring in this way, it is not necessary to provide a region with a difference in p concentration in stages, and the SiC element 1A can be easily created. When this embodiment is used, the distance L means the distance from the anode electrode 7A to the element outer peripheral side end 236 of the third p region 60C, and the width W is the second p region 60B and the second p region 60B. This means the middle point 237 of the region between the third p region 60C.
以上、上述したように、本発明を用いることによって、シリコーンゲル中に発生する最大電界を低減し、耐圧特性の安定したSiC素子搭載パワー半導体モジュールを提供することが可能となる。 As described above, by using the present invention, it is possible to provide an SiC element-mounted power semiconductor module in which the maximum electric field generated in the silicone gel is reduced and the breakdown voltage characteristics are stable.
1A SiC素子
1B Si素子
2A 第一の樹脂層
2B 第二の樹脂層
3 シリコーンゲル
4 ワイヤーボンディング
5 接合層
6 セラミックス回路基板
6A1、6A2 配線パターン
6B セラミックス絶縁板
6C 金属パターン
1A SiC element 1B Si element 2A First resin layer 2B Second resin layer 3 Silicone gel 4 Wire bonding 5 Bonding layer 6 Ceramic circuit boards 6A1, 6A2 Wiring pattern 6B Ceramic insulating plate 6C Metal pattern
Claims (7)
前記半導体素子を封止するシリコーンゲルと、を有する半導体装置において、
前記電界緩和領域とシリコーンゲルとの間には、SiO2から成る無機層と、当該無機層の上部に形成された樹脂層とを有し、
前記樹脂層の誘電率は、前記無機層の誘電率以下であり、且つシリコーンゲルの誘電率以上であり、
前記樹脂層は、前記無機物と直接接触する第一の樹脂層と、当該第一の樹脂層の上に形成された第二の樹脂層からなり、
前記第二の樹脂層の厚みは前記第一の樹脂層の厚みよりも厚いことを特徴とする半導体装置。 A semiconductor element made of SiC having an electric field relaxation region around the upper surface of the element;
In a semiconductor device having a silicone gel for sealing the semiconductor element,
Between the electric field relaxation region and the silicone gel, an inorganic layer made of SiO 2 and a resin layer formed on the inorganic layer,
The dielectric constant of the resin layer is less than or equal to the dielectric constant of the inorganic layer state, and are and more the dielectric constant of silicone gel,
The resin layer comprises a first resin layer that is in direct contact with the inorganic material, and a second resin layer formed on the first resin layer,
The semiconductor device according to claim 1, wherein the second resin layer has a thickness greater than that of the first resin layer .
前記第二の樹脂層の厚さは50μm以上500μm以下であることを特徴とする半導体装置。 The semiconductor device according to claim 1 ,
A thickness of the second resin layer is not less than 50 μm and not more than 500 μm.
前記第二の樹脂層はポリアミドイミド樹脂、ポリエーテルアミドイミド樹脂、ポリエーテルアミド樹脂から選ばれる一種あるいは複数種類で構成されていることを特徴とする半導体装置。 The semiconductor device according to claim 1 or 2 ,
The semiconductor device, wherein the second resin layer is composed of one kind or plural kinds selected from a polyamideimide resin, a polyetheramideimide resin, and a polyetheramide resin.
前記第一の樹脂層の厚さは1μm以上20μm以下であることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 3 ,
The semiconductor device according to claim 1, wherein the first resin layer has a thickness of 1 μm to 20 μm.
前記第一の樹脂層はポリイミド樹脂であることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 4,
The semiconductor device, wherein the first resin layer is a polyimide resin.
前記第二の樹脂層は、前記第一の樹脂層の誘電率よりも小さいことを特徴とする半導体装置。 The semiconductor device according to claim 1 or 2 ,
The semiconductor device, wherein the second resin layer has a dielectric constant smaller than that of the first resin layer.
前記電界緩和領域は濃度の異なる複数のp領域で構成されることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 6,
The semiconductor device, wherein the electric field relaxation region is composed of a plurality of p regions having different concentrations.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012056618A JP5600698B2 (en) | 2012-03-14 | 2012-03-14 | Power semiconductor module with SiC element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012056618A JP5600698B2 (en) | 2012-03-14 | 2012-03-14 | Power semiconductor module with SiC element |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013191716A JP2013191716A (en) | 2013-09-26 |
JP5600698B2 true JP5600698B2 (en) | 2014-10-01 |
Family
ID=49391681
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012056618A Active JP5600698B2 (en) | 2012-03-14 | 2012-03-14 | Power semiconductor module with SiC element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5600698B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10355090B2 (en) | 2016-07-15 | 2019-07-16 | Fuji Electric Co., Ltd. | Silicon carbide semiconductor device |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015092866A1 (en) | 2013-12-17 | 2015-06-25 | 三菱電機株式会社 | Power semiconductor module |
US20150255362A1 (en) * | 2014-03-07 | 2015-09-10 | Infineon Technologies Ag | Semiconductor Device with a Passivation Layer and Method for Producing Thereof |
JP6335331B2 (en) * | 2014-12-24 | 2018-05-30 | 株式会社日立製作所 | Semiconductor device and power conversion device using the same |
DE112014007221B4 (en) | 2014-12-26 | 2023-10-19 | Hitachi Power Semiconductor Device, Ltd. | Semiconductor device, method for producing the same and semiconductor module |
JP2018056144A (en) * | 2015-01-07 | 2018-04-05 | 株式会社日立製作所 | Power semiconductor module device and manufacturing method thereof |
WO2016166808A1 (en) | 2015-04-14 | 2016-10-20 | 三菱電機株式会社 | Semiconductor device |
JP6627359B2 (en) * | 2015-09-17 | 2020-01-08 | 富士電機株式会社 | Semiconductor device and method of manufacturing semiconductor device |
JP6457663B2 (en) * | 2016-01-05 | 2019-01-23 | 株式会社日立製作所 | Semiconductor device |
JP6711001B2 (en) * | 2016-02-17 | 2020-06-17 | 富士電機株式会社 | Semiconductor device and manufacturing method |
JP2019091731A (en) * | 2016-03-10 | 2019-06-13 | 株式会社日立製作所 | POWER SEMICONDUCTOR MODULE, SiC SEMICONDUCTOR ELEMENT MOUNTED ON THE SAME, AND METHOD OF MANUFACTURING THE SiC SEMICONDUCTOR ELEMENT |
WO2017199698A1 (en) * | 2016-05-17 | 2017-11-23 | 三菱電機株式会社 | Semiconductor device and method for manufacturing same |
JP6647151B2 (en) * | 2016-06-15 | 2020-02-14 | 株式会社 日立パワーデバイス | Semiconductor device, method of manufacturing the same, semiconductor module and power converter |
EP3279935B1 (en) * | 2016-08-02 | 2019-01-02 | ABB Schweiz AG | Power semiconductor module |
JP2018060928A (en) | 2016-10-06 | 2018-04-12 | 株式会社日立製作所 | Power module and power conversion apparatus |
JP6726112B2 (en) * | 2017-01-19 | 2020-07-22 | 株式会社 日立パワーデバイス | Semiconductor device and power converter |
US11631653B2 (en) | 2017-02-03 | 2023-04-18 | Mitsubishi Electric Corporation | Ultrasonic bonding apparatus, ultrasonic bonding inspection method and ultrasonically-bonded portion fabrication method |
JP7173157B2 (en) * | 2018-10-23 | 2022-11-16 | 三菱電機株式会社 | Semiconductor device manufacturing method, semiconductor device, power conversion device, and moving body |
US11538769B2 (en) * | 2018-12-14 | 2022-12-27 | General Electric Company | High voltage semiconductor devices having improved electric field suppression |
EP3951841A1 (en) * | 2020-08-07 | 2022-02-09 | Hitachi Energy Switzerland AG | Power semiconductor devices with edge termination and method of manufacturing the same |
JP7157783B2 (en) * | 2020-09-07 | 2022-10-20 | 富士電機株式会社 | Semiconductor module manufacturing method and semiconductor module |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56167333A (en) * | 1980-05-26 | 1981-12-23 | Fujitsu Ltd | Semiconductor device |
JPH01185925A (en) * | 1988-01-21 | 1989-07-25 | Hitachi Ltd | Semiconductor device |
JPH08204066A (en) * | 1995-01-20 | 1996-08-09 | Fuji Electric Co Ltd | Semiconductor device |
JP3332819B2 (en) * | 1997-08-25 | 2002-10-07 | 株式会社日立製作所 | Method for manufacturing high withstand voltage semiconductor device |
JP3708057B2 (en) * | 2001-07-17 | 2005-10-19 | 株式会社東芝 | High voltage semiconductor device |
JP3960837B2 (en) * | 2002-03-22 | 2007-08-15 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
JP5477681B2 (en) * | 2008-07-29 | 2014-04-23 | 三菱電機株式会社 | Semiconductor device |
JP5601849B2 (en) * | 2010-02-09 | 2014-10-08 | 三菱電機株式会社 | Method for manufacturing silicon carbide semiconductor device |
JP2012156153A (en) * | 2011-01-21 | 2012-08-16 | Kansai Electric Power Co Inc:The | Semiconductor device |
-
2012
- 2012-03-14 JP JP2012056618A patent/JP5600698B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10355090B2 (en) | 2016-07-15 | 2019-07-16 | Fuji Electric Co., Ltd. | Silicon carbide semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2013191716A (en) | 2013-09-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5600698B2 (en) | Power semiconductor module with SiC element | |
US8450828B2 (en) | Semiconductor device | |
JP6251810B2 (en) | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND POWER CONVERSION DEVICE | |
JP2007335858A (en) | Power semiconductor module having terminal elements electrically insulated from each other | |
US20200051717A1 (en) | Current sensing resistor | |
US9418954B2 (en) | Integrated circuit chip assembled on an interposer | |
US9466542B2 (en) | Semiconductor device | |
CN110914973A (en) | Capacitor with a capacitor element | |
JP4967701B2 (en) | Power semiconductor device | |
US7405448B2 (en) | Semiconductor device having a resistance for equalizing the current distribution | |
US20190126374A1 (en) | Power semiconductor module | |
JP2017143185A (en) | Semiconductor device and manufacturing method of the same | |
JP5826443B1 (en) | Semiconductor device and manufacturing method thereof | |
WO2016111127A1 (en) | Power semiconductor module device and method for manufacturing same | |
US9153516B2 (en) | Voidlessly encapsulated semiconductor die package | |
JP2014120728A (en) | Semiconductor device and manufacturing method therefor | |
JP5683777B2 (en) | Switching assembly for high voltage aircraft ignition system and switching assembly | |
US20060125053A1 (en) | Zener diode and methods for fabricating and packaging same | |
JP2007035913A (en) | Semiconductor device | |
JP2005026434A (en) | Semiconductor device | |
US11626361B2 (en) | Power semiconductor module | |
WO2023136078A1 (en) | Semiconductor device | |
JP7004233B2 (en) | Semiconductor device | |
JP2007067317A (en) | Mounting structure of semiconductor device, and mounting method of the semiconductor device | |
US9698092B2 (en) | Electronic device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20130829 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20131122 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140521 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140527 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140701 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140722 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140818 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5600698 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |