JP5585733B2 - Radiation detector and manufacturing method thereof - Google Patents

Radiation detector and manufacturing method thereof Download PDF

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Publication number
JP5585733B2
JP5585733B2 JP2013525546A JP2013525546A JP5585733B2 JP 5585733 B2 JP5585733 B2 JP 5585733B2 JP 2013525546 A JP2013525546 A JP 2013525546A JP 2013525546 A JP2013525546 A JP 2013525546A JP 5585733 B2 JP5585733 B2 JP 5585733B2
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electrode
bump
radiation detector
semiconductor layer
pixel
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JPWO2013014846A1 (en
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弘之 岸原
晃一 田邊
敏 徳田
利典 吉牟田
正知 貝野
聖菜 吉松
敏幸 佐藤
章二 桑原
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Shimadzu Corp
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Shimadzu Corp
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Description

本発明は、Ｘ線、γ線、光等を含む放射線を検出する機能を有し、医用および異物検査等の産業用に使用される放射線検出器とその製造方法に関する。   The present invention relates to a radiation detector having a function of detecting radiation including X-rays, γ-rays, light, etc., and used for industrial purposes such as medical and foreign matter inspection, and a method for manufacturing the same.

従来の放射線検出器１０１は、図８に示すように、対向基板１０２とアクティブマトリクス基板１０３とを備えている。対向基板１０２は、入射した放射線（例えばＸ線）に感応して電荷（キャリア）を生成する半導体層１０６と、半導体層１０６の上部に設けられたバイアス電圧印加用の共通電極１０４と、を備えている。半導体層１０６には、共通電極１０４側に電子注入阻止層１０５、また共通電極１０４の反対側に正孔注入阻止層１０７が設けられている。また、正孔注入阻止層１０７のアクティブマトリクス基板１０３側には、画素ごとに分離して形成された対向電極１０８が設けられている。   A conventional radiation detector 101 includes a counter substrate 102 and an active matrix substrate 103 as shown in FIG. The counter substrate 102 includes a semiconductor layer 106 that generates charges (carriers) in response to incident radiation (for example, X-rays), and a common electrode 104 for applying a bias voltage provided on the semiconductor layer 106. ing. The semiconductor layer 106 is provided with an electron injection blocking layer 105 on the common electrode 104 side and a hole injection blocking layer 107 on the opposite side of the common electrode 104. A counter electrode 108 formed separately for each pixel is provided on the active matrix substrate 103 side of the hole injection blocking layer 107.

一方、アクティブマトリクス基板１０３は、生成された電荷を蓄積するコンデンサ１１１と、コンデンサ１１１に蓄積された電荷を読み出すためにスイッチとして作用する薄膜トランジスタ（以下適宜、「ＴＦＴ」と略す）１１２等を備えている。コンデンサ１１１は、画素電極１１４と絶縁膜１１５とグランド線１１６とを備えており、ＴＦＴ１１２は、画素電極１１４、絶縁膜１１５，データ線１１７、ゲートチャネル１１８およびゲート線１１９を備えている。コンデンサ１１１およびＴＦＴ１１２は、絶縁基板１１３上に形成される。なお、符号１２０は絶縁膜を示す。   On the other hand, the active matrix substrate 103 includes a capacitor 111 that accumulates the generated charges, a thin film transistor (hereinafter, abbreviated as “TFT”) 112 that functions as a switch for reading out the charges accumulated in the capacitor 111, and the like. Yes. The capacitor 111 includes a pixel electrode 114, an insulating film 115, and a ground line 116. The TFT 112 includes a pixel electrode 114, an insulating film 115, a data line 117, a gate channel 118, and a gate line 119. The capacitor 111 and the TFT 112 are formed on the insulating substrate 113. Reference numeral 120 denotes an insulating film.

対向基板１０２とアクティブマトリクス基板１０３は、個別に形成され、形成後に貼り合わせられる。対向基板１０２とアクティブマトリクス基板１０３とを貼り合わせるために、アクティブマトリクス基板１０３の画素電極１１４上には、スクリーン印刷によりバンプ電極１３２が形成される。そして、対向基板１０２とアクティブマトリクス基板１０３は、対向基板１０２の対向電極１０８と、アクティブマトリクス基板１０３の画素電極１１４上に形成されたバンプ電極１３２とが接合されることにより貼り合わせられる。しかしながら、このような従来の放射線検出器１０１は、対向基板１０２とアクティブマトリクス基板１０３とを貼り合わせる際に、対向電極１０８とバンプ電極１３２とを位置合わせする必要があった。   The counter substrate 102 and the active matrix substrate 103 are formed separately and are bonded together after formation. In order to bond the counter substrate 102 and the active matrix substrate 103 together, bump electrodes 132 are formed on the pixel electrodes 114 of the active matrix substrate 103 by screen printing. The counter substrate 102 and the active matrix substrate 103 are bonded together by bonding the counter electrode 108 of the counter substrate 102 and the bump electrode 132 formed on the pixel electrode 114 of the active matrix substrate 103. However, such a conventional radiation detector 101 needs to align the counter electrode 108 and the bump electrode 132 when the counter substrate 102 and the active matrix substrate 103 are bonded together.

そこで、図９に示す放射線検出器２０１では、図８に示す放射線検出器１０１の対向電極１０８が設けられていない構成となっている。これにより、対向基板１０２とアクティブマトリクス基板１０３とを貼り合わせる際に、バンプ電極１３２の位置合わせする必要がないようになっている（例えば特許文献１および２参照）。なお、放射線検出器２０１において、放射線検出器１０１と同じ構成のものについては、放射線検出器１０１と同じ符号を付している。   Therefore, the radiation detector 201 shown in FIG. 9 has a configuration in which the counter electrode 108 of the radiation detector 101 shown in FIG. 8 is not provided. This eliminates the need to align the bump electrodes 132 when the counter substrate 102 and the active matrix substrate 103 are bonded to each other (see, for example, Patent Documents 1 and 2). In the radiation detector 201, the same components as those of the radiation detector 101 are denoted by the same reference numerals as those of the radiation detector 101.

特開２００８−１７１８３３号公報JP 2008-171833 A 特開２００７−２８０９７７号公報JP 2007-280977 A

しかしながら、このような構成を有する従来の放射線検出器２０１の場合には、次のような問題がある。すなわち、図９に示す放射線検出器２０１は、図８に示す放射線検出器１０１のように対向電極１０８を設けていないので、半導体層１０６で生成された電荷を効率よく収集するためにバンプ電極１３２の径を大きくすることが望まれる。図９に示すように、バンプ電極１３２の直上で生成された電荷は、バンプ電極１３２で収集されてコンデンサ１１１に蓄積される。しかしながら、バンプ電極１３２とバンプ電極１３２との間で生成された電荷（符号ａ）は、どちらのバンプ電極１３２に収集されるかは定かでない。これにより、画素間で感度のばらつきが生じることになる。バンプ電極１３２は、図１０（ａ）に示すように、円形に形成されている。   However, the conventional radiation detector 201 having such a configuration has the following problems. That is, since the radiation detector 201 shown in FIG. 9 is not provided with the counter electrode 108 unlike the radiation detector 101 shown in FIG. 8, the bump electrode 132 is collected in order to efficiently collect the charges generated in the semiconductor layer 106. It is desirable to increase the diameter. As shown in FIG. 9, the charge generated immediately above the bump electrode 132 is collected by the bump electrode 132 and accumulated in the capacitor 111. However, it is not clear to which bump electrode 132 the electric charge (symbol a) generated between the bump electrode 132 and the bump electrode 132 is collected. As a result, variations in sensitivity occur between pixels. The bump electrode 132 is formed in a circular shape as shown in FIG.

このように、半導体層１０６で生成された電荷を効率よく収集するためにバンプ電極１３２の径を大きくすることが望まれる。しかしながら、画素電極１１４の面積以上の径のバンプ電極１３２を形成すると、隣接する画素電極１１４、あるいは隣接するバンプ電極１３２と接触する可能性がある。そのため、バンプ電極１３２の径の大きさには制限がある。また、スクリーン印刷によるバンプ電極１３２の形成においては、たとえ印刷マスクのパターン孔が画素電極１１４に沿って四角形に構成してもバンプ電極１３２の先端側は、円形となってしまう（図１０（ｂ））。すなわち、スクリーン印刷によるバンプ電極１３２は、その画素電極１１４側で四角形であっても、先端に向かうにつれて円形に形成されてしまう（図１０（ｃ））。そのため、バンプ電極１３２と半導体層１０６側との接触面積を大きくすることは難しい。   As described above, it is desirable to increase the diameter of the bump electrode 132 in order to efficiently collect the charges generated in the semiconductor layer 106. However, when the bump electrode 132 having a diameter larger than the area of the pixel electrode 114 is formed, there is a possibility that the adjacent pixel electrode 114 or the adjacent bump electrode 132 is brought into contact. Therefore, the size of the diameter of the bump electrode 132 is limited. Further, in the formation of the bump electrode 132 by screen printing, even if the pattern hole of the print mask is formed in a square shape along the pixel electrode 114, the tip side of the bump electrode 132 becomes circular (FIG. 10B). )). That is, even if the bump electrode 132 by screen printing is a rectangle on the pixel electrode 114 side, the bump electrode 132 is formed in a circle toward the tip (FIG. 10C). Therefore, it is difficult to increase the contact area between the bump electrode 132 and the semiconductor layer 106 side.

本発明は、このような事情に鑑みてなされたものであって、生成された電荷を効率良く収集し、画素間で感度ばらつきを抑えた放射線検出器およびその製造方法を提供することを目的とする。   The present invention has been made in view of such circumstances, and an object of the present invention is to provide a radiation detector that efficiently collects generated charges and suppresses sensitivity variations between pixels, and a method for manufacturing the same. To do.

本発明は、このような目的を達成するために、次のような構成をとる。すなわち、本発明に係る放射線検出器は、入射した放射線に感応して電荷を生成する、画素ごとに分離して形成される対向電極が設けられていない半導体層を有する対向基板と、前記電荷を収集する画素電極がマトリクス状に配置されたアクティブマトリクス基板と、前記半導体層と前記各画素電極とを接合するバンプ電極とを備え、前記バンプ電極は、前記各画素電極上に複数形成されていることを特徴とするものである。 In order to achieve such an object, the present invention has the following configuration. That is, the radiation detector according to the present invention generates a charge in response to incident radiation, and includes a counter substrate having a semiconductor layer without a counter electrode formed separately for each pixel, and the charge. An active matrix substrate in which pixel electrodes to be collected are arranged in a matrix, and a bump electrode that joins the semiconductor layer and each pixel electrode, and a plurality of the bump electrodes are formed on each pixel electrode It is characterized by this.

本発明に係る放射線検出器によれば、対向基板は、入射した放射線に感応して電荷を生成する、画素ごとに分離して形成される対向電極が設けられていない半導体層を有し、アクティブマトリクス基板は、前記電荷を収集する画素電極がマトリクス状に配置されている。バンプ電極は、各画素電極上に複数形成されて半導体層と各画素電極とを接合する。 According to the radiation detector of the present invention, the counter substrate includes a semiconductor layer that is not provided with a counter electrode that is formed separately for each pixel and generates charges in response to incident radiation. The matrix substrate has pixel electrodes for collecting the charges arranged in a matrix. A plurality of bump electrodes are formed on each pixel electrode to join the semiconductor layer and each pixel electrode.

すなわち、画素電極には、バンプ電極が複数形成される。対向基板とアクティブマトリクス基板とを貼り合わせする際、すなわち、対向基板の半導体層とアクティブマトリクス基板の画素電極に形成された複数のバンプ電極とを接合する際に、画素電極に複数のバンプ電極が潰れて結合し、擬似的に１つの大きなバンプ電極となる。そのため、半導体層とバンプ電極との接触面積を大きくすることができる。また、接触面積が大きくなることで画素間の隙間が減少する。したがって、半導体層で生成された電荷を１画素ごとに効率よく収集することができ、画素間の感度ばらつきを低減させることができる。   That is, a plurality of bump electrodes are formed on the pixel electrode. When bonding the counter substrate and the active matrix substrate, that is, when bonding the semiconductor layer of the counter substrate and the plurality of bump electrodes formed on the pixel electrode of the active matrix substrate, the plurality of bump electrodes are formed on the pixel electrode. They are crushed and combined to form one large bump electrode. Therefore, the contact area between the semiconductor layer and the bump electrode can be increased. Further, the gap between the pixels is reduced by increasing the contact area. Therefore, charges generated in the semiconductor layer can be efficiently collected for each pixel, and variations in sensitivity between pixels can be reduced.

また、本発明に係る放射線検出器において、前記画素電極は、四角形で形成され、前記バンプ電極は、前記各画素電極上に四角形に配置していることが好ましい。すなわち、四角形の画素電極に複数のバンプ電極が四角形に配置しているので、バンプ電極を画素電極の角部まで配置させることができる。そのため、半導体層とバンプ電極との接触面積を大きくすることができる。また、接触面積が大きくなることで画素間の隙間が減少する。   In the radiation detector according to the present invention, it is preferable that the pixel electrode is formed in a square shape, and the bump electrode is arranged in a square shape on each pixel electrode. That is, since the plurality of bump electrodes are arranged in a square shape on the square pixel electrode, the bump electrodes can be arranged up to the corners of the pixel electrode. Therefore, the contact area between the semiconductor layer and the bump electrode can be increased. Further, the gap between the pixels is reduced by increasing the contact area.

また、本発明に係る放射線検出器において、前記バンプ電極の一例は、前記各画素電極上に格子状に配置していることである。これにより、画素間の隙間がなく接触面積を大きくする構成を容易にすることができる。また、縦横列でバンプ電極を均等に配置することができる。   In the radiation detector according to the present invention, an example of the bump electrode is that the bump electrodes are arranged in a grid pattern on the pixel electrodes. Thereby, the structure which does not have the clearance gap between pixels and enlarges a contact area can be made easy. Further, the bump electrodes can be evenly arranged in rows and columns.

また、本発明に係る放射線検出器において、前記バンプ電極の一例は、前記各画素電極上に千鳥配列で配置していることである。これにより、画素間の隙間がなく接触面積を大きくする構成を容易にすることができる。また、複数のバンプ電極間の隙間を減少することができる。   In the radiation detector according to the present invention, an example of the bump electrode is a staggered arrangement on each pixel electrode. Thereby, the structure which does not have the clearance gap between pixels and enlarges a contact area can be made easy. Further, the gap between the plurality of bump electrodes can be reduced.

また、本発明に係る放射線検出器において、前記半導体層は、ＣｄＴｅまたはＣｄＺｎＴｅであることが好ましい。これにより、半導体層として例えば、ａ−Ｓｅ（アモルファスセレン）で構成されるものと比べて放射線に対する感度を向上させることができる。そのため、より低線量での撮影をすることができる。   In the radiation detector according to the present invention, the semiconductor layer is preferably CdTe or CdZnTe. Thereby, the sensitivity with respect to a radiation can be improved compared with what is comprised as a semiconductor layer, for example by a-Se (amorphous selenium). Therefore, it is possible to take an image with a lower dose.

また、本発明に係る放射線検出器の製造方法は、入射した放射線に感応して電荷を生成する、画素ごとに分離して形成される対向電極が設けられていない半導体層を有する対向基板を作成する工程と、前記電荷を蓄積するコンデンサとコンデンサに蓄積された電荷を読み出すためのスイッチング素子との組が格子状に複数組配置されるアクティブマトリクス基板を作成する工程と、前記アクティブマトリクス基板に形成された複数の前記コンデンサの画素電極ごとに複数個のバンプ電極をスクリーン印刷により四角形に配置して形成する工程と、前記対向基板の半導体層と前記アクティブマトリクス基板の前記画素電極に形成された前記複数個のバンプ電極とを接合する工程と、を備えることを特徴とするものである。

In addition, the manufacturing method of the radiation detector according to the present invention creates a counter substrate having a semiconductor layer which is not provided with a counter electrode formed separately for each pixel, which generates charges in response to incident radiation. Forming an active matrix substrate in which a plurality of sets of a capacitor for accumulating the charge and a switching element for reading out the electric charge accumulated in the capacitor are arranged in a lattice pattern, and forming the active matrix substrate on the active matrix substrate Forming a plurality of bump electrodes for each pixel electrode of the plurality of capacitors arranged in a square by screen printing, and forming the semiconductor layer of the counter substrate and the pixel electrode of the active matrix substrate And a step of bonding a plurality of bump electrodes.

本発明に係る放射線検出器の製造方法によれば、アクティブマトリクス基板に形成された複数のコンデンサの画素電極ごとに複数個のバンプ電極をスクリーン印刷により四角形に配置して形成する。すなわち、画素電極には、スクリーン印刷により複数個のバンプ電極が四角形に配置して形成される。対向基板とアクティブマトリクス基板とを貼り合わせする際、すなわち、対向基板の半導体層とアクティブマトリクス基板の画素電極に形成された複数個のバンプ電極とを接合する際に、画素電極に四角形に配置された複数のバンプ電極が潰れて結合し、擬似的に１つの大きなバンプ電極となる。そのため、半導体層とバンプ電極との接触面積を大きくすることができる。また、接触面積が大きくなることで画素間の隙間が減少する。したがって、半導体層で生成された電荷を１画素ごとに効率よく収集することができ、画素間の感度ばらつきを低減させることができる。   According to the method for manufacturing a radiation detector according to the present invention, a plurality of bump electrodes are formed in a square shape by screen printing for each pixel electrode of a plurality of capacitors formed on an active matrix substrate. That is, a plurality of bump electrodes are formed in a square shape on the pixel electrode by screen printing. When the counter substrate and the active matrix substrate are bonded together, that is, when the semiconductor layer of the counter substrate and a plurality of bump electrodes formed on the pixel electrode of the active matrix substrate are bonded, the pixel electrodes are arranged in a square shape. The plurality of bump electrodes are crushed and combined to form one large bump electrode. Therefore, the contact area between the semiconductor layer and the bump electrode can be increased. Further, the gap between the pixels is reduced by increasing the contact area. Therefore, charges generated in the semiconductor layer can be efficiently collected for each pixel, and variations in sensitivity between pixels can be reduced.

本発明に係る放射線検出器によれば、画素電極には、バンプ電極が複数形成される。対向基板とアクティブマトリクス基板とを貼り合わせする際、すなわち、対向基板の半導体層とアクティブマトリクス基板の画素電極に形成された複数のバンプ電極とを接合する際に、画素電極に複数のバンプ電極が潰れて結合し、擬似的に１つの大きなバンプ電極となる。そのため、半導体層とバンプ電極との接触面積を大きくすることができる。また、接触面積が大きくなることで画素間の隙間が減少する。したがって、半導体層で生成された電荷を１画素ごとに効率よく収集することができ、画素間の感度ばらつきを低減させることができる。   According to the radiation detector of the present invention, a plurality of bump electrodes are formed on the pixel electrode. When bonding the counter substrate and the active matrix substrate, that is, when bonding the semiconductor layer of the counter substrate and the plurality of bump electrodes formed on the pixel electrode of the active matrix substrate, the plurality of bump electrodes are formed on the pixel electrode. They are crushed and combined to form one large bump electrode. Therefore, the contact area between the semiconductor layer and the bump electrode can be increased. Further, the gap between the pixels is reduced by increasing the contact area. Therefore, charges generated in the semiconductor layer can be efficiently collected for each pixel, and variations in sensitivity between pixels can be reduced.

本発明に係る放射線検出器の製造方法によれば、画素電極には、スクリーン印刷により複数個のバンプ電極が四角形に配置して形成される。対向基板とアクティブマトリクス基板とを貼り合わせする際、すなわち、対向基板の半導体層とアクティブマトリクス基板の画素電極に形成された複数個のバンプ電極とを接合する際に、画素電極に四角形に配置された複数のバンプ電極が潰れて結合し、擬似的に１つの大きなバンプ電極となる。そのため、半導体層とバンプ電極との接触面積を大きくすることができる。また、接触面積が大きくなることで画素間の隙間が減少する。したがって、半導体層で生成された電荷を１画素ごとに効率よく収集することができ、画素間の感度ばらつきを低減させることができる。   According to the method for manufacturing a radiation detector according to the present invention, a plurality of bump electrodes are formed in a square shape on a pixel electrode by screen printing. When the counter substrate and the active matrix substrate are bonded together, that is, when the semiconductor layer of the counter substrate and a plurality of bump electrodes formed on the pixel electrode of the active matrix substrate are bonded, the pixel electrodes are arranged in a square shape. The plurality of bump electrodes are crushed and combined to form one large bump electrode. Therefore, the contact area between the semiconductor layer and the bump electrode can be increased. Further, the gap between the pixels is reduced by increasing the contact area. Therefore, charges generated in the semiconductor layer can be efficiently collected for each pixel, and variations in sensitivity between pixels can be reduced.

実施例に係るＸ線検出器の構成を示す縦断面図である。It is a longitudinal cross-sectional view which shows the structure of the X-ray detector which concerns on an Example. 実施例に係るＸ線検出器の構成を示すブロック図である。It is a block diagram which shows the structure of the X-ray detector which concerns on an Example. 実施例に係るＸ線検出器の製造方法を示すフローチャートである。It is a flowchart which shows the manufacturing method of the X-ray detector which concerns on an Example. （ａ）はスクリーン印刷で形成された複数（３×３個）のバンプ電極を示す図であり、（ｂ）は接合後における複数のバンプ電極が潰れた状態を示す図である。(A) is a figure which shows the several (3x3) bump electrode formed by screen printing, (b) is a figure which shows the state by which the several bump electrode after joining was crushed. （ａ）〜（ｃ）は、スクリーン印刷の説明に供する図である。(A)-(c) is a figure where it uses for description of screen printing. （ａ）は変形例に係る２×２個で形成されたバンプ電極を示す図であり、（ｂ）は変形例に係る４×４個で形成されたバンプ電極が千鳥配列で配置している図であり、（ｃ）は変形例に係る画素電極からはみ出して配置したバンプ電極の一例を示す図である。(A) is a figure which shows the bump electrode formed by 2x2 which concerns on a modification, (b) is the bump electrode formed by 4x4 which concerns on a modification, and has arrange | positioned by the staggered arrangement | sequence. It is a figure, (c) is a figure which shows an example of the bump electrode arrange | positioned and protruded from the pixel electrode which concerns on a modification. 変形例に係るバンプ電極が形成される電極を示す図である。It is a figure which shows the electrode in which the bump electrode which concerns on a modification is formed. 従来の放射線検出器の構成を示す縦断面図である。It is a longitudinal cross-sectional view which shows the structure of the conventional radiation detector. 図８と異なる従来の放射線検出器の構成を示す縦断面図である。It is a longitudinal cross-sectional view which shows the structure of the conventional radiation detector different from FIG. （ａ）は従来のスクリーン印刷で形成されたバンプ電極を示す図であり、（ｂ）および（ｃ）は、画素電極に沿って印刷マスクのパターン孔を四角形にした場合に形成されたバンプ電極の形状を示す図である。(A) is a figure which shows the bump electrode formed by the conventional screen printing, (b) and (c) are the bump electrodes formed when the pattern hole of the printing mask was made into a square along a pixel electrode. FIG.

以下、図面を参照して本発明の実施例を説明する。図１は、実施例に係るＸ線検出器の構成を示す縦断面図であり、図２は、実施例に係るＸ線検出器の構成を示すブロック図である。また、本実施例では、放射線検出器の一例として、Ｘ線を検出するＸ線検出器（ＦＰＤ；フラットパネル型Ｘ線検出器）について説明する。   Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a longitudinal sectional view showing the configuration of the X-ray detector according to the embodiment, and FIG. 2 is a block diagram showing the configuration of the X-ray detector according to the embodiment. In this embodiment, an X-ray detector (FPD; flat panel X-ray detector) that detects X-rays will be described as an example of a radiation detector.

図１を参照する。Ｘ線検出器１は、入射したＸ線を電荷に変換する対向基板２と、変換された電荷を蓄積するとともに、蓄積された電荷を読み出すアクティブマトリクス基板３とを備えている。   Please refer to FIG. The X-ray detector 1 includes a counter substrate 2 that converts incident X-rays into electric charges, and an active matrix substrate 3 that accumulates the converted electric charges and reads out the accumulated electric charges.

対向基板２は、Ｘ線入射方向（符号ｘ）から順番に、バイアス電圧印加用の共通電極４と、この共通電極４の下面に形成され、後述する半導体層６への電荷（電子）の注入を阻止する電子注入阻止層５と、入射したＸ線に感応して電荷（電子−正孔対キャリア）を生成する半導体層６と、半導体層６への電荷（正孔）の注入を阻止する正孔注入阻止層７とが積層形成された構成となっている。   The counter substrate 2 is formed on the common electrode 4 for applying the bias voltage and the lower surface of the common electrode 4 in order from the X-ray incident direction (symbol x), and charges (electrons) are injected into the semiconductor layer 6 described later. An electron injection blocking layer 5 for blocking the charge, a semiconductor layer 6 that generates charges (electron-hole pair carriers) in response to incident X-rays, and a charge (hole) injection to the semiconductor layer 6 is blocked. The hole injection blocking layer 7 is laminated.

一方、アクティブマトリクス基板３は、生成された電荷を蓄積するコンデンサ１１と、コンデンサ１１に蓄積された電荷を読み出すためにスイッチング素子として機能する薄膜トランジスタ（ＴＦＴ）１２などを備えている。コンデンサ１１とＴＦＴ１２等は、絶縁基板１３上に形成される。コンデンサ１１は、画素電極１４と絶縁膜１５とグランド線１６とで構成されている。グランド線１６は、アースされたり、所定電圧が印加されていたりする。ＴＦＴ１２は、画素電極１４および絶縁膜１５、データ線１７、ゲートチャネル１８、ゲート線１９で構成されている。なお、絶縁膜２０は保護膜として形成される。なお、ＴＦＴ１２は、本発明におけるスイッチング素子に相当する。   On the other hand, the active matrix substrate 3 includes a capacitor 11 that accumulates the generated charges, a thin film transistor (TFT) 12 that functions as a switching element to read out the charges accumulated in the capacitor 11, and the like. The capacitor 11, the TFT 12, etc. are formed on the insulating substrate 13. The capacitor 11 includes a pixel electrode 14, an insulating film 15, and a ground line 16. The ground line 16 is grounded or a predetermined voltage is applied. The TFT 12 includes a pixel electrode 14, an insulating film 15, a data line 17, a gate channel 18, and a gate line 19. The insulating film 20 is formed as a protective film. The TFT 12 corresponds to a switching element in the present invention.

対向基板２とアクティブマトリクス基板３は、正孔注入阻止層７を介して半導体層６と、画素電極１４上のバンプ電極群３１とが接合されている。バンプ電極群３１は、複数個（例えは３×３個）のバンプ電極３２で構成される。バンプ電極群３１については、Ｘ線検出器１の製造方法において説明する。   In the counter substrate 2 and the active matrix substrate 3, the semiconductor layer 6 and the bump electrode group 31 on the pixel electrode 14 are bonded via the hole injection blocking layer 7. The bump electrode group 31 includes a plurality of (for example, 3 × 3) bump electrodes 32. The bump electrode group 31 will be described in the manufacturing method of the X-ray detector 1.

図１中の符号ＤＵは、Ｘ線検出素子を示しており、Ｘ線検出素子ＤＵでの検出が１画素に相当する。Ｘ線検出素子ＤＵは、２次元マトリクス状に配置され、図２に示すように３×３個で構成されている。なお、実際には、Ｘ線検出素子ＤＵは、例えば１５００×１５００個程度（２３０×２３０ｍｍ程度）で構成される。アクティブマトリクス基板３には、コンデンサ１１とＴＦＴ１２との組が格子状に複数組（３×３組）配置されている。   A symbol DU in FIG. 1 indicates an X-ray detection element, and detection by the X-ray detection element DU corresponds to one pixel. The X-ray detection elements DU are arranged in a two-dimensional matrix, and are composed of 3 × 3 as shown in FIG. Actually, the X-ray detection element DU is configured with, for example, about 1500 × 1500 (about 230 × 230 mm). On the active matrix substrate 3, a plurality of sets (3 × 3 sets) of capacitors 11 and TFTs 12 are arranged in a lattice pattern.

図２において、ゲート線１９は、行（Ｘ）方向のＸ線検出素子ＤＵで共通に構成されており、データ線１７は、列（Ｙ）方向のＸ線検出素子ＤＵで共通に構成されている。また、ゲート線１９は、ゲート駆動部４１と接続されており、データ線１７は、順番に電荷電圧変換アンプ４２、マルチプレクサ４３に接続されている。ゲート駆動部４１、電荷電圧変換アンプ４２およびマルチプレクサ４３は、駆動制御部４４で制御されるようになっており、例えば図示しない外部装置からの信号で駆動させるようになっている。   In FIG. 2, the gate line 19 is configured in common with the X-ray detection element DU in the row (X) direction, and the data line 17 is configured in common with the X-ray detection element DU in the column (Y) direction. Yes. The gate line 19 is connected to the gate drive unit 41, and the data line 17 is connected to the charge-voltage conversion amplifier 42 and the multiplexer 43 in order. The gate drive unit 41, the charge / voltage conversion amplifier 42, and the multiplexer 43 are controlled by a drive control unit 44, and are driven by signals from an external device (not shown), for example.

次に、実施例におけるＸ線検出器１の製造方法について図３のフローチャートに沿って説明する。   Next, a method for manufacturing the X-ray detector 1 in the embodiment will be described with reference to the flowchart of FIG.

〔ステップＳ０１〕対向基板の作成
図１を参照する。共通電極４は、例えば、グラファイトやＩＴＯ（酸化インジウムスズ）、Ａｕ（金）、Ｐｔ（白金）などの導電材料から構成される。共通電極４がＩＴＯ、Ａｕ、Ｐｔなどの場合は、ガラスやセラミック（Ａｌ２Ｏ３、ＡｌＮ）で構成された図示しない支持基板上に蒸着法やスパッタリング等で形成する。共通電極４がグラファイトの場合は、導電性のあるグラファイトの支持基板がその状態で共通電極４として機能する。[Step S01] Creation of counter substrate Referring to FIG. The common electrode 4 is made of a conductive material such as graphite, ITO (indium tin oxide), Au (gold), or Pt (platinum). When the common electrode 4 is made of ITO, Au, Pt or the like, it is formed by vapor deposition or sputtering on a support substrate (not shown) made of glass or ceramic (Al 2 O 3 , AlN). When the common electrode 4 is graphite, a conductive graphite support substrate functions as the common electrode 4 in that state.

共通電極４上（図１では下側）に電子注入阻止層５を形成する。電子注入阻止層５は、ＺｎＴｅ、またはＳｂ２Ｓ３等のｐ型半導体で構成され、共通電極４上に昇華法、蒸着もしくはスパッタリング、化学析出法、または電析法等によって形成される。An electron injection blocking layer 5 is formed on the common electrode 4 (lower side in FIG. 1). The electron injection blocking layer 5 is made of a p-type semiconductor such as ZnTe or Sb 2 S 3 and is formed on the common electrode 4 by a sublimation method, vapor deposition or sputtering, a chemical deposition method, an electrodeposition method, or the like.

電子注入阻止層５上（図１では下側）に半導体層６を形成する。半導体層６は、ＣｄＴｅ（テルル化カドミウム）またはＣｄＺｎＴｅ（テルル化カドミウム亜鉛）の化合物半導体で構成される。半導体層６は、近接昇華法で６００μｍ程度に形成し、４００μｍ程度に表面を研磨して形成される。なお、近接昇華法では、高温（７００℃程度）に加熱するので、半導体層６は、例えば、グラファイト、あるいはセラミック基板上のＩＴＯ層などの耐熱材料に形成される。なお、近接昇華法では、高温に加熱して半導体層６を形成するので、対向基板２とアクティブマトリクス基板３が個別に形成される。また、半導体層６の成膜は、近接昇華法の他に、ＭＯＣＶＤ（Metal Organic Chemical Vapor Deposition）法や、ペースト印刷・焼成法等が用いてもよい。また、半導体層６は、ＰｂＩ２（ヨウ化鉛）やａ−Ｓｅ（アモルファスセレン）で構成されていてもよい。A semiconductor layer 6 is formed on the electron injection blocking layer 5 (lower side in FIG. 1). The semiconductor layer 6 is made of a compound semiconductor of CdTe (cadmium telluride) or CdZnTe (cadmium zinc telluride). The semiconductor layer 6 is formed to have a thickness of about 600 μm by the proximity sublimation method and the surface is polished to about 400 μm. In the proximity sublimation method, the semiconductor layer 6 is formed on a heat-resistant material such as graphite or an ITO layer on a ceramic substrate because it is heated to a high temperature (about 700 ° C.). In the proximity sublimation method, since the semiconductor layer 6 is formed by heating to a high temperature, the counter substrate 2 and the active matrix substrate 3 are formed separately. In addition to the proximity sublimation method, the semiconductor layer 6 may be formed by MOCVD (Metal Organic Chemical Vapor Deposition) method, paste printing / firing method, or the like. The semiconductor layer 6 may be made of PbI 2 (lead iodide) or a-Se (amorphous selenium).

半導体層６上（図１では下側）に正孔注入阻止層７を形成する。正孔注入阻止層７は、ＣｄＳ（硫化カドミウム）、ＺｎＳ（硫化亜鉛）、ＺｎＯ（酸化亜鉛）、またはＳｂ２Ｓ３（硫化アンチモン）等のｎ型半導体で構成され、昇華法、蒸着法、スパッタリング、化学析出法、または電析法等で形成される。なお、必要に応じて、正孔注入阻止層７と電子注入阻止層５と配置を交換して形成した構成としてもよいし、また、電子注入阻止層５および正孔注入阻止層７のいずれか一方あるいは両方を形成しない構成としてもよい。A hole injection blocking layer 7 is formed on the semiconductor layer 6 (on the lower side in FIG. 1). The hole injection blocking layer 7 is made of an n-type semiconductor such as CdS (cadmium sulfide), ZnS (zinc sulfide), ZnO (zinc oxide), or Sb 2 S 3 (antimony sulfide). It is formed by sputtering, chemical precipitation, or electrodeposition. In addition, if necessary, the hole injection blocking layer 7 and the electron injection blocking layer 5 may be formed by exchanging the arrangement, or any one of the electron injection blocking layer 5 and the hole injection blocking layer 7 may be used. One or both may not be formed.

〔ステップＳ０２〕アクティブマトリクス基板の作成
ガラス等で構成される絶縁基板１３上にグランド線１６とゲート線１９とを形成し、絶縁膜１５を形成する。グランド線１６およびゲート線１９は、Ｔａ（タンタル）、Ａｌ（アルミニウム）、Ｍｏ（モリブレン）等の金属膜で構成される。これらの金属膜は、蒸着法またはスパッタリング等で形成される。絶縁膜１５は、ＳｉＮｘやＳｉＯｘで構成され、蒸着法等で形成される。また、絶縁膜１５は、無機膜の他にアクリルやポリイミド等で構成してもよい。[Step S02] Creation of Active Matrix Substrate A ground line 16 and a gate line 19 are formed on an insulating substrate 13 made of glass or the like, and an insulating film 15 is formed. The ground line 16 and the gate line 19 are made of a metal film such as Ta (tantalum), Al (aluminum), or Mo (molybrene). These metal films are formed by vapor deposition or sputtering. The insulating film 15 is made of SiNx or SiOx and is formed by a vapor deposition method or the like. The insulating film 15 may be made of acrylic, polyimide, or the like in addition to the inorganic film.

ＴＦＴ１２を形成するためにゲートチャネル１８を絶縁膜１５上に形成する。ゲートチャネル１８は、ａ−Ｓｉ（アモルファスシリコン）やｐ−Ｓｉ（ポリシリコン）を蒸着法で形成し、不純物を拡散させて例えばｎ＋層としたもので構成される。   A gate channel 18 is formed on the insulating film 15 to form the TFT 12. The gate channel 18 is configured by forming a-Si (amorphous silicon) or p-Si (polysilicon) by a vapor deposition method and diffusing impurities to form, for example, an n + layer.

コンデンサ１１およびＴＦＴ１２を作成するために画素電極１４とデータ線１７とを絶縁膜１５等上に形成し、また、絶縁膜２０を形成する。画素電極１４およびデータ線１７は、Ｔａ、Ａｌ、Ｔｉ（チタン）等の金属膜で構成される。これらの金属膜は、蒸着法またはスパッタリング等で形成される。絶縁膜２０は、絶縁膜１５と同様に形成されるが、バンプ電極３２を形成する画素電極１４上には、絶縁膜２０を形成しないようにする。なお、ＴＦＴ１２は、ボトムゲート構造であるが、トップゲート構造にしてもよい。   In order to form the capacitor 11 and the TFT 12, the pixel electrode 14 and the data line 17 are formed on the insulating film 15 and the like, and the insulating film 20 is formed. The pixel electrode 14 and the data line 17 are made of a metal film such as Ta, Al, Ti (titanium). These metal films are formed by vapor deposition or sputtering. The insulating film 20 is formed in the same manner as the insulating film 15, but the insulating film 20 is not formed on the pixel electrode 14 on which the bump electrode 32 is formed. The TFT 12 has a bottom gate structure, but may have a top gate structure.

〔ステップＳ０３〕バンプ電極の形成
ステップＳ０２で形成されたアクティブマトリクス基板３上にバンプ電極３２を形成する。バンプ電極３２は、導電性ペーストをスクリーン印刷することで形成される。スクリーン印刷は、大面積のパターン形成を簡単・低コストで作成でき、また、大面積にわたって等ピッチでバンプ電極３２を配置することを簡単に行うことができる。[Step S03] Formation of Bump Electrodes Bump electrodes 32 are formed on the active matrix substrate 3 formed in Step S02. The bump electrode 32 is formed by screen printing a conductive paste. Screen printing can create a large area pattern easily and at low cost, and can easily arrange the bump electrodes 32 at a constant pitch over a large area.

バンプ電極３２は、導電性ペーストで構成され、例えば、ゴムを主成分とした母材に、カーボンを主成分とした導電性材料と、常温で放置することにより有機物質が徐々に揮発して硬化する、あるいは空気中の水分と縮合反応して硬化するバインダー樹脂とを配合したもので構成される。この導電性ペーストに含まれる導電性材料については、導電性を有していれば、適宜材料を選択しても良い。また、例えば、母材の主成分をゴムと例示したが、その他の高分子材料でもよい。バインダー樹脂についても、必ずしも樹脂に限定されず、接着性および硬化性を有する素材の混合物であってもよい。   The bump electrode 32 is made of a conductive paste. For example, an organic substance is gradually volatilized and cured by leaving a conductive material mainly composed of carbon and a conductive material mainly composed of carbon on a base material mainly composed of rubber. Or a blend of a binder resin that cures by condensation with moisture in the air. About the electroconductive material contained in this electroconductive paste, as long as it has electroconductivity, you may select a material suitably. For example, the main component of the base material is exemplified as rubber, but other polymer materials may be used. Also about binder resin, it is not necessarily limited to resin, The mixture of the raw material which has adhesiveness and sclerosis | hardenability may be sufficient.

また、導電性ペーストには、例えば、バインダー樹脂のように常温で放置することにより有機物質が徐々に揮発して硬化する、あるいは空気中の水分と縮合反応して硬化する素材が含まれていることが望ましいが、温度変化（１００℃程度まで）を与えることにより硬化する物質が含まれていてもよい。   In addition, the conductive paste includes, for example, a material such as a binder resin that is cured by allowing the organic substance to volatilize gradually when left at room temperature, or to cure by condensation with moisture in the air. Desirably, a substance that cures when a temperature change (up to about 100 ° C.) is applied may be included.

図４（ａ）を参照する。アクティブマトリクス基板３に形成された複数のコンデンサ１１の画素電極１４ごとに複数個（３×３個）のバンプ電極３２をスクリーン印刷により四角形に配置して形成する。バンプ電極３２は、画素電極１４の四角形の形状に合わせて形成されている。バンプ電極３２は、複数個のバンプ電極３２が隙間なく並んで形成してもよいし、対向基板２との貼り合わせ時にバンプ電極３２が潰されることを考慮してバンプ電極３２間に隙間があるように形成してもよい。   Reference is made to FIG. For each pixel electrode 14 of the plurality of capacitors 11 formed on the active matrix substrate 3, a plurality (3 × 3) of bump electrodes 32 are formed in a square shape by screen printing. The bump electrode 32 is formed in accordance with the square shape of the pixel electrode 14. The bump electrodes 32 may be formed by arranging a plurality of bump electrodes 32 side by side without any gap, and there is a gap between the bump electrodes 32 in consideration of the fact that the bump electrode 32 is crushed when bonded to the counter substrate 2. You may form as follows.

次に、図５（ａ）〜図５（ｃ）を参照して、スクリーン印刷によるバンプ電極３２の形成について説明する。図５（ａ）に示すように、ステップＳ０２で作成されたアクティブマトリクス基板３に対向してメタルマスク５１を配置する。メタルマスク５１は、金属薄板で構成され、バンプ電極３２を形成する部分にパターン孔（開口）５２が設けられている。メタルマスク５１の配置後、図５（ｂ）および図５（ｃ）に示すように、メタルマスク５１上の一端に導電性ペースト５３を載置する。載置された導電性ペースト５３をスキージ５４でアクティブマトリクス基板３側に押し付けながらメタルマスク５１の他端に移動させる。これにより、パターン孔５２に導電性ペースト５３が入り込み、パターン孔５２に入り込んだ導電性ペースト５３によりバンプ電極３２が画素電極１４に形成される。また、メタルマスク５１に代えて、ステンレス線などで構成されたメッシュにバンプ電極３２を形成しない部分をマスクしたメッシュ状の印刷マスクを用いてもよい。   Next, the formation of the bump electrodes 32 by screen printing will be described with reference to FIGS. As shown in FIG. 5A, a metal mask 51 is disposed so as to face the active matrix substrate 3 created in step S02. The metal mask 51 is formed of a thin metal plate, and a pattern hole (opening) 52 is provided in a portion where the bump electrode 32 is formed. After the arrangement of the metal mask 51, a conductive paste 53 is placed on one end of the metal mask 51 as shown in FIGS. 5 (b) and 5 (c). The placed conductive paste 53 is moved to the other end of the metal mask 51 while being pressed against the active matrix substrate 3 side by the squeegee 54. As a result, the conductive paste 53 enters the pattern hole 52, and the bump electrode 32 is formed on the pixel electrode 14 by the conductive paste 53 that has entered the pattern hole 52. Further, instead of the metal mask 51, a mesh-shaped printing mask in which a portion where the bump electrode 32 is not formed may be used on a mesh made of stainless steel wire or the like.

〔ステップＳ０４〕対向基板とアクティブマトリクス基板との貼り合わせ（接合）
対向基板２における正孔注入阻止層７を介して半導体層６と、アクティブマトリクス基板３の画素電極１４上における複数個のバンプ電極３２とを接合する。これにより、対向基板２とアクティブマトリクス基板３とが貼り合われる。接合は、予め設定された所定の圧力を加えながら、常温放置、あるいは必要に応じて加熱することにより行われる。このとき、図４（ａ）のように形成されたバンプ電極３２は、図４（ｂ）に示すように潰れて結合し、擬似的に１つの大きなバンプ電極（バンプ電極群）３１になる。[Step S04] Bonding (bonding) the counter substrate and the active matrix substrate
The semiconductor layer 6 and a plurality of bump electrodes 32 on the pixel electrodes 14 of the active matrix substrate 3 are bonded via the hole injection blocking layer 7 in the counter substrate 2. Thereby, the counter substrate 2 and the active matrix substrate 3 are bonded together. Joining is performed by leaving at room temperature or applying heat as necessary while applying a predetermined pressure set in advance. At this time, the bump electrode 32 formed as shown in FIG. 4A is crushed and joined as shown in FIG. 4B to become one large bump electrode (bump electrode group) 31.

このような工程によりＸ線検出器１が作成される。なお、この他に、ゲート駆動部４１、電荷電圧変換アンプ４２、マルチプレクサ４３、および駆動制御部４４等が設けられる。   The X-ray detector 1 is created by such a process. In addition, a gate drive unit 41, a charge / voltage conversion amplifier 42, a multiplexer 43, a drive control unit 44, and the like are provided.

次に、図１および図２を参照して、Ｘ線検出器１の動作の説明をする。Ｘ線管から被検体に向けてＸ線が照射され（Ｘ線管と被検体は共に図示しない）、被検体を透過したＸ線はＸ線検出器１に入射する。半導体層６にＸ線が入射すると、光導電効果により半導体層６で電荷が生成する。このとき、コンデンサ１１と、電子注入阻止層５を介した半導体層６とは、バンプ電極群３１により直列に接続された構成となっている。そのため、共通電極４にバイアス電圧（Ｖｈ）を印加しておくと、半導体層６内で生成された電荷が移動する。そして、生成された電荷は、バンプ電極群３１（画素電極１４）で収集されてコンデンサ１１に蓄積される。バンプ電極群３１は、図１０（ａ）のように円形に形成されておらず、画素電極１４の四角形状に沿って形成（すなわち角部まで形成）されているので、１画素ごとに接触面積が大きくなり、また、画素間の隙間も減少する。これにより、半導体層６で生成された電荷を１画素ごとに効率よく収集される。   Next, the operation of the X-ray detector 1 will be described with reference to FIGS. 1 and 2. X-rays are irradiated from the X-ray tube toward the subject (both the X-ray tube and the subject are not shown), and the X-rays transmitted through the subject enter the X-ray detector 1. When X-rays enter the semiconductor layer 6, charges are generated in the semiconductor layer 6 due to the photoconductive effect. At this time, the capacitor 11 and the semiconductor layer 6 via the electron injection blocking layer 5 are connected in series by the bump electrode group 31. Therefore, if a bias voltage (Vh) is applied to the common electrode 4, the charge generated in the semiconductor layer 6 moves. The generated charges are collected by the bump electrode group 31 (pixel electrode 14) and accumulated in the capacitor 11. The bump electrode group 31 is not formed in a circular shape as shown in FIG. 10A, but is formed along the quadrangular shape of the pixel electrode 14 (that is, formed up to the corner). Increases, and the gaps between pixels also decrease. As a result, charges generated in the semiconductor layer 6 are efficiently collected for each pixel.

コンデンサ１１に蓄積された電荷は、ＴＦＴ１２によりコンデンサ１１から読み出される。ゲート駆動部４１は、例えば図２の上側のゲート線１９から１行ずつ順番に電圧を印加して信号を送信することで、ＴＦＴ１２を接続（ＯＮ）の状態にし、コンデンサ１１に蓄積された電荷をデータ線１７から読み出しを行う。電荷電圧変換アンプ４２は、データ線１７を通じて取り出された電荷を電圧に変換して電圧信号として出力する。マルチプレクサ４３は、複数の電圧信号から１つの電圧信号を選択して出力する。このようにして出力された電圧信号に基づいてＸ線画像が取得される。   The electric charge accumulated in the capacitor 11 is read from the capacitor 11 by the TFT 12. For example, the gate drive unit 41 applies a voltage sequentially from the upper gate line 19 in FIG. 2 one by one to transmit a signal, thereby turning the TFT 12 into a connection (ON) state, and the charge accumulated in the capacitor 11. Is read from the data line 17. The charge-voltage conversion amplifier 42 converts the charge taken out through the data line 17 into a voltage and outputs it as a voltage signal. The multiplexer 43 selects and outputs one voltage signal from the plurality of voltage signals. An X-ray image is acquired based on the voltage signal output in this way.

本実施例に係るＸ線検出器１によれば、画素電極１４には、スクリーン印刷により複数個のバンプ電極３２が四角形に配置して形成される。対向基板２とアクティブマトリクス基板３とを貼り合わせする際、すなわち、対向基板２の半導体層６とアクティブマトリクス基板３の画素電極１４に形成された複数個のバンプ電極３２とを接合する際に、画素電極１４に四角形に配置された複数のバンプ電極３２が潰れて結合し、擬似的に１つの大きなバンプ電極（バンプ電極群）３１となる。そのため、半導体層６とバンプ電極（バンプ電極群）３１との接触面積を大きくすることができる。また、接触面積が大きくなることで画素間の隙間が減少する。したがって、半導体層６で生成された電荷を１画素ごとに効率よく収集することができ、画素間の感度ばらつきを低減させることができる。   According to the X-ray detector 1 according to the present embodiment, the pixel electrode 14 is formed with a plurality of bump electrodes 32 arranged in a square by screen printing. When the counter substrate 2 and the active matrix substrate 3 are bonded together, that is, when the semiconductor layer 6 of the counter substrate 2 and the plurality of bump electrodes 32 formed on the pixel electrodes 14 of the active matrix substrate 3 are bonded. A plurality of bump electrodes 32 arranged in a square shape on the pixel electrode 14 are crushed and combined to form one large bump electrode (bump electrode group) 31 in a pseudo manner. Therefore, the contact area between the semiconductor layer 6 and the bump electrode (bump electrode group) 31 can be increased. Further, the gap between the pixels is reduced by increasing the contact area. Therefore, charges generated in the semiconductor layer 6 can be efficiently collected for each pixel, and sensitivity variations between pixels can be reduced.

また、半導体層６として、ＣｄＴｅまたはＣｄＺｎＴｅで構成すると、例えば、ａ−Ｓｅで構成されるものと比べてＸ線に対する感度を向上させることができる。そのため、より低線量での撮影をすることができる。   Further, when the semiconductor layer 6 is composed of CdTe or CdZnTe, for example, sensitivity to X-rays can be improved as compared with that composed of a-Se. Therefore, it is possible to take an image with a lower dose.

本発明は、上記実施形態に限られることはなく、下記のように変形実施することができる。   The present invention is not limited to the above embodiment, and can be modified as follows.

（１）上述した実施例では、図４（ａ）では、バンプ電極３２は、画素電極１４ごとに３×３個で構成したが、図６（ａ）に示すように、２×２個でもよく、また４×４個や、４×３個、その他の個数で構成されてもよい。   (1) In the above-described embodiment, 3 × 3 bump electrodes 32 are formed for each pixel electrode 14 in FIG. 4A. However, as shown in FIG. Alternatively, it may be composed of 4 × 4, 4 × 3, or other numbers.

（２）上述した実施例では、複数のバンプ電極３２は、格子状（２次元マトリクス状）に配置している。これにより、画素間の隙間がなく接触面積を大きくする構成を容易にすることができ、また、縦横列でバンプ電極を均等に配置することができる。しかしながら、例えば、図６（ｂ）に示すように、複数のバンプ電極３２は、位置をずらして配置された２列のバンプ電極３２が交互に形成される、千鳥配列に配置していてもよい。これにより、画素間の隙間がなく接触面積を大きくする構成を容易にすることができ、また、複数個のバンプ電極間の隙間を減少することができる。また、バンプ電極３２は、画素電極１４の四角形状に沿って形成されていれば、厳密に四角形に配置されていなくてもよく（図６（ｂ））、規則的に並んでいなくてもよい。   (2) In the above-described embodiment, the plurality of bump electrodes 32 are arranged in a lattice shape (two-dimensional matrix shape). As a result, a configuration in which there is no gap between pixels and the contact area is increased can be facilitated, and bump electrodes can be evenly arranged in rows and columns. However, for example, as shown in FIG. 6B, the plurality of bump electrodes 32 may be arranged in a staggered arrangement in which two rows of bump electrodes 32 arranged at different positions are alternately formed. . Accordingly, it is possible to facilitate a configuration in which there is no gap between pixels and the contact area is increased, and it is possible to reduce gaps between a plurality of bump electrodes. Further, the bump electrodes 32 do not have to be strictly arranged in a quadrilateral shape as long as they are formed along the quadrangular shape of the pixel electrode 14 (FIG. 6B), and may not be arranged regularly. Good.

（３）上述した実施例では、バンプ電極３２は、画素電極１４内に形成されていたが、はみ出して形成してもよい。例えば、画素電極１４の一部が欠けて形成されている場合は、図６（ｃ）に示すように、画素電極１４からはみ出して構成してもよい。なお、図６（ｃ）に示す画素電極１４は四角形に含まれるものとする。   (3) In the above-described embodiment, the bump electrode 32 is formed in the pixel electrode 14, but may be formed so as to protrude. For example, in the case where a part of the pixel electrode 14 is not formed, the pixel electrode 14 may protrude from the pixel electrode 14 as shown in FIG. It is assumed that the pixel electrode 14 shown in FIG.

（４）上述した実施例では、図１に示すように、バンプ電極３２は、コンデンサ１１の電極の１つである画素電極１４上に形成されていたが、画素電極１４上に限定されない。例えば、図７に示すように、画素電極１４に接続された、画素電極１４上の画素（Ｘ線検出素子ＤＵ）ごとに形成された電極１４ａにバンプ電極３２を形成してもよい。なお、符号１４ｂは、画素電極１４と電極１４ａとを接続させる配線を示し、符号１４ｃは絶縁膜を示す。すなわち、画素電極１４は、電極１４ａを含むものとする。   (4) In the above-described embodiment, as shown in FIG. 1, the bump electrode 32 is formed on the pixel electrode 14 that is one of the electrodes of the capacitor 11, but is not limited to the pixel electrode 14. For example, as shown in FIG. 7, the bump electrode 32 may be formed on the electrode 14 a formed for each pixel (X-ray detection element DU) on the pixel electrode 14 connected to the pixel electrode 14. Reference numeral 14b indicates a wiring for connecting the pixel electrode 14 and the electrode 14a, and reference numeral 14c indicates an insulating film. That is, the pixel electrode 14 includes the electrode 14a.

（５）本実施例は、図８に示す対向電極１０８が設けられていない対向基板２と、アクティブマトリクス基板３とを貼り合わせた構成であれば、適用することができる。   (5) This embodiment can be applied as long as the counter substrate 2 not provided with the counter electrode 108 shown in FIG. 8 is bonded to the active matrix substrate 3.

１ … Ｘ線検出器
２ … 対向基板
３ … アクティブマトリクス基板
６ … 半導体層
１１ … コンデンサ
１２ … 薄膜トランジスタ（ＴＦＴ）
１４ … 画素電極
１８ … ゲートチャネル
３１ … バンプ電極群
３２ … バンプ電極
５３ … 導電性ペーストDESCRIPTION OF SYMBOLS 1 ... X-ray detector 2 ... Opposite substrate 3 ... Active matrix substrate 6 ... Semiconductor layer 11 ... Capacitor 12 ... Thin-film transistor (TFT)
DESCRIPTION OF SYMBOLS 14 ... Pixel electrode 18 ... Gate channel 31 ... Bump electrode group 32 ... Bump electrode 53 ... Conductive paste

Claims (6)

入射した放射線に感応して電荷を生成する、画素ごとに分離して形成される対向電極が設けられていない半導体層を有する対向基板と、
前記電荷を収集する画素電極がマトリクス状に配置されたアクティブマトリクス基板と、
前記半導体層と前記各画素電極とを接合するバンプ電極とを備え、
前記バンプ電極は、前記各画素電極上に複数形成されていることを特徴とする放射線検出器。 A counter substrate having a semiconductor layer that is not provided with a counter electrode formed separately for each pixel that generates charges in response to incident radiation;
An active matrix substrate in which pixel electrodes for collecting the charges are arranged in a matrix;
A bump electrode that joins the semiconductor layer and the pixel electrodes;
A radiation detector, wherein a plurality of the bump electrodes are formed on each pixel electrode. 請求項１に記載の放射線検出器において、
前記画素電極は、四角形で形成され、
前記バンプ電極は、前記各画素電極上に四角形に配置していることを特徴とする放射線検出器。The radiation detector according to claim 1.
The pixel electrode is formed in a quadrangle,
The radiation detector according to claim 1, wherein the bump electrodes are arranged in a square shape on each pixel electrode. 請求項１または２に記載の放射線検出器において、
前記バンプ電極は、前記各画素電極上に格子状に配置していることを特徴とする放射線検出器。The radiation detector according to claim 1 or 2,
The radiation detector according to claim 1, wherein the bump electrodes are arranged in a grid pattern on the pixel electrodes. 請求項１または２に記載の放射線検出器において、
前記バンプ電極は、前記各画素電極上に千鳥配列で配置していることを特徴とする放射線検出器。The radiation detector according to claim 1 or 2,
The radiation detector according to claim 1, wherein the bump electrodes are arranged in a staggered arrangement on the pixel electrodes. 請求項１から４のいずれかに記載の放射線検出器において、
前記半導体層は、ＣｄＴｅまたはＣｄＺｎＴｅであることを特徴とする放射線検出器。The radiation detector according to any one of claims 1 to 4,
The radiation detector according to claim 1, wherein the semiconductor layer is CdTe or CdZnTe. 入射した放射線に感応して電荷を生成する、画素ごとに分離して形成される対向電極が設けられていない半導体層を有する対向基板を作成する工程と、
前記電荷を蓄積するコンデンサとコンデンサに蓄積された電荷を読み出すためのスイッチング素子との組が格子状に複数組配置されるアクティブマトリクス基板を作成する工程と、
前記アクティブマトリクス基板に形成された複数の前記コンデンサの画素電極ごとに複数個のバンプ電極をスクリーン印刷により四角形に配置して形成する工程と、
前記対向基板の半導体層と前記アクティブマトリクス基板の前記画素電極に形成された前記複数個のバンプ電極とを接合する工程と、
を備えることを特徴とする放射線検出器の製造方法。 Creating a counter substrate having a semiconductor layer that is not provided with a counter electrode formed separately for each pixel that generates charges in response to incident radiation; and
Creating an active matrix substrate in which a plurality of sets of capacitors for storing the charge and switching elements for reading out the charge stored in the capacitor are arranged in a lattice pattern;
A step of forming a plurality of bump electrodes for each pixel electrode of the plurality of capacitors formed on the active matrix substrate by arranging them in a square by screen printing;
Bonding the semiconductor layer of the counter substrate and the plurality of bump electrodes formed on the pixel electrode of the active matrix substrate;
A method for manufacturing a radiation detector.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009295841A (en) * 2008-06-06 2009-12-17 Fujitsu Ltd Imaging device
JP2010192815A (en) * 2009-02-20 2010-09-02 Fujitsu Ltd Image sensor
JP2011089964A (en) * 2009-10-26 2011-05-06 Ishida Co Ltd Article inspection device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4835838B2 (en) * 2006-04-03 2011-12-14 株式会社島津製作所 Manufacturing method of two-dimensional image detector

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009295841A (en) * 2008-06-06 2009-12-17 Fujitsu Ltd Imaging device
JP2010192815A (en) * 2009-02-20 2010-09-02 Fujitsu Ltd Image sensor
JP2011089964A (en) * 2009-10-26 2011-05-06 Ishida Co Ltd Article inspection device

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