JP5563668B2 - フロントエンド回路 - Google Patents
フロントエンド回路 Download PDFInfo
- Publication number
- JP5563668B2 JP5563668B2 JP2012541326A JP2012541326A JP5563668B2 JP 5563668 B2 JP5563668 B2 JP 5563668B2 JP 2012541326 A JP2012541326 A JP 2012541326A JP 2012541326 A JP2012541326 A JP 2012541326A JP 5563668 B2 JP5563668 B2 JP 5563668B2
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- JP
- Japan
- Prior art keywords
- signal
- duplexer
- power amplification
- output
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
- H03F3/602—Combinations of several amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B1/0483—Transmitters with multiple parallel paths
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/111—Indexing scheme relating to amplifiers the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/429—Two or more amplifiers or one amplifier with filters for different frequency bands are coupled in parallel at the input or output
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/543—A transmission line being used as coupling element between two amplifying stages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F2203/7209—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched from a first band to a second band
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F2203/7239—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers and shunting lines by one or more switch(es)
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B2001/0408—Circuits with power amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Amplifiers (AREA)
- Microwave Amplifiers (AREA)
- Transmitters (AREA)
Description
異なる図面に現れる、同一のデザイン及び機能の構成要素は、同一の参照符号を付すことで特定している。
ANT 共通アンテナ
BP1 第1の迂回路
BP2 第2の迂回路
DIP 周波数選択器
DIPPA 電力増幅回路
DR ドライバー
FEM フロントエンド回路
GND 基準電位
HBDUP 第2のデュプレクサー
LBDUP 第1のデュプレクサー
PA1、PA2 電力増幅段
PA3、PA4 電力増幅器
PIN 入力端
POUT1、POUT2、POUT3 出力端
R 抵抗器
S_1 第1の信号
S_2 第2の信号
S_A1 第1の増幅された信号
S_A2 第2の増幅された信号
S_DR ドライバー信号
S_R 受信信号経路
TL1、TL2、TL3 伝送線路素子
TLU 伝送線路ユニット
TXRX トランシーバー
Claims (7)
- 入力端及び出力端を有し、その入力端における所定の送信信号に依存する前置増幅されたドライバー信号(S_DR)をその出力端に供給するよう適用可能なドライバー段(DR)、
入力端(PIN)及び少なくとも2個の出力端(POUT1、POUT2)を有し、前記入力端(PIN)を介して前記ドライバー段(DR)の前記出力端に電気的に結合されていて、前記ドライバー信号(S_DR)から少なくとも第1の信号(S_1)及び第2の信号(S_2)を分離するように動作し、前記第1の信号(S_1)は第1の所定の周波数帯に対応付けられており、前記第2の信号(S_2)は第2の所定の周波数帯に対応付けられている周波数選択器(DIP)、
それぞれが入力端及び出力端を有する、少なくとも第1の電力増幅枝路及び第2の電力増幅枝路、を備え、
前記第1の電力増幅枝路の前記入力端は周波数選択器(DIP)の前記第1の出力端(POUT1)に電気的に結合されており、前記第2の電力増幅枝路の前記入力端は周波数選択器(DIP)の前記第2の出力端(POUT2)に電気的に結合されており、前記第1の電力増幅枝路が、前記第1の信号(S_1)に依存する第1の増幅された信号(S_A1)をその出力端に供給し、第2の電力増幅枝路が、前記第2の信号(S_2)に依存する第2の増幅された信号(S_A2)をその出力端に供給するよう動作し、
前記ドライバー段及び前記周波数選択器は、進行波増幅器で構成されている、
無線通信装置のための電力増幅回路(DIPPA)と、
少なくとも第1のデュプレクサー(LBDUP)及び第2のデュプレクサー(HBDUP)と、
共通アンテナ(ANT)と、を備え、
前記第1のデュプレクサー(LBDUP)及び前記第2のデュプレクサー(HBDUP)はそれぞれ、入力端及び出力端を備え、前記第1のデュプレクサー(LBDUP)の前記入力端は前記第1の電力増幅枝路の前記出力端に電気的に結合され、前記第2のデュプレクサー(HBDUP)の前記入力端は前記第2の電力増幅枝路の前記出力端に電気的に結合され、前記第1のデュプレクサー(LBDUP)及び前記第2のデュプレクサー(HBDUP)はそれぞれ、その入力端からその出力端へと信号を通し、
前記共通アンテナ(ANT)は、前記第1のデュプレクサー(LBDUP)の前記出力端及び前記第2のデュプレクサー(HBDUP)の前記出力端に電気的に結合される、
無線通信装置のためのフロントエンド回路(FEM)であって、
前記進行波増幅器で構成された前記周波数選択器は、電力増幅器と、複数の第1の種類の伝送線路素子と、複数の第2の種類の伝送線路素子と、を備え、
前記複数の第1の種類の伝送線路素子は、信号の周波数に従属するその信号の位相をシフトするように動作可能に構成されており、
前記複数の第2の種類の伝送線路素子は、それぞれ、信号の周波数に従属するその信号の勾配及び位相をあらかじめ定めるよう動作可能に構成されており、
前記複数の第1の種類の伝送線路素子および前記複数の第2の種類の伝送線路素子は、信号の伝達方向がその信号の周波数に依存するものとなるように構成されている、
フロントエンド回路(FEM)。 - 前記ドライバー段(DR)は、供給された所定の送信信号を広帯域で前置増幅するよう適用可能な少なくとも1個の広帯域増幅器を備え、前記広帯域は、少なくとも前記第1及び前記第2の所定の周波数帯を包含する、
請求項1に記載のフロントエンド回路(FEM)。 - 前記周波数選択器(DIP)は、前記ドライバー信号(S_DR)及び/又は前記第1の信号(S_1)及び/又は前記第2の信号(S_2)を増幅するよう適用可能な少なくとも1個の電力増幅器(PA3、PA4)を備える、
請求項1又は2に記載のフロントエンド回路(FEM)。 - 前記第1及び/又は前記第2の電力増幅枝路はそれぞれ、少なくとも1個の狭帯域増幅器を備える、
請求項1〜3のいずれか1項に記載のフロントエンド回路(FEM)。 - 少なくとも第1の迂回路(BP1)及び第2の迂回路(BP2)を備え、
前記第1の迂回路(BP1)は前記第1の電力増幅枝路に対応付けられており、
前記第2の迂回路(BP2)は前記第2の電力増幅枝路に対応付けられており、
特定の前記迂回路(BP1、BP2)は、特定の前記電力増幅枝路の前記入力端及び前記出力端をバイパスするよう動作する、
請求項1〜4のいずれか1項に記載のフロントエンド回路(FEM)。 - 前記ドライバー段(DR)及び前記周波数選択器(DIP)、又は、
前記周波数選択器(DIP)及び前記第1の電力増幅枝路及び前記第2の電力増幅枝路、又は、
前記ドライバー段(DR)及び前記周波数選択器(DIP)及び前記第1の電力増幅枝路及び前記第2の電力増幅枝路は、単一のチップに集積されている、
請求項1〜5のいずれか1項に記載のフロントエンド回路(FEM)。 - 少なくとも第1の入力端と第2の入力端と単一の出力端とを有するアンテナマルチプレクサー(ADIP)を備えており、前記アンテナマルチプレクサー(ADIP)の前記出力端は前記共通アンテナ(ANT)に電気的に結合され、前記アンテナマルチプレクサー(ADIP)の前記第1の入力端は前記第1のデュプレクサー(LBDUP)の前記出力端に電気的に結合され、前記アンテナマルチプレクサー(ADIP)の前記第2の入力端は前記第2のデュプレクサー(HBDUP)の前記出力端に電気的に結合され、前記アンテナマルチプレクサー(ADIP)は、前記第1のデュプレクサー(LBDUP)及び前記第2のデュプレクサー(HBDUP)が出力する前記信号を結合して、これを送信方向において、前記共通アンテナ(ANT)に供給するよう動作する、
請求項1〜6のいずれか1項に記載のフロントエンド回路(FEM)。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP2009/066355 WO2011066861A1 (en) | 2009-12-03 | 2009-12-03 | Power amplifier circuit and front end circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013512634A JP2013512634A (ja) | 2013-04-11 |
JP5563668B2 true JP5563668B2 (ja) | 2014-07-30 |
Family
ID=42313152
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012541326A Expired - Fee Related JP5563668B2 (ja) | 2009-12-03 | 2009-12-03 | フロントエンド回路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8912847B2 (ja) |
JP (1) | JP5563668B2 (ja) |
DE (1) | DE112009005411B4 (ja) |
WO (1) | WO2011066861A1 (ja) |
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2009
- 2009-12-03 DE DE112009005411.0T patent/DE112009005411B4/de active Active
- 2009-12-03 US US13/513,239 patent/US8912847B2/en not_active Expired - Fee Related
- 2009-12-03 WO PCT/EP2009/066355 patent/WO2011066861A1/en active Application Filing
- 2009-12-03 JP JP2012541326A patent/JP5563668B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE112009005411T5 (de) | 2012-12-20 |
DE112009005411B4 (de) | 2018-10-18 |
US20120235735A1 (en) | 2012-09-20 |
JP2013512634A (ja) | 2013-04-11 |
US8912847B2 (en) | 2014-12-16 |
WO2011066861A1 (en) | 2011-06-09 |
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