JP5561245B2 - Semiconductor substrate evaluation method - Google Patents
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Description
本発明は、半導体基板の評価方法に関し、特にリーク電流測定による半導体基板の評価方法に関する。 The present invention relates to a method for evaluating a semiconductor substrate, and more particularly to a method for evaluating a semiconductor substrate by measuring leakage current.
メモリ、ＣＣＤのような固体撮像素子等の半導体装置の微細化、高性能化に伴い、それらの製品歩留まりを向上させるために、材料としてのシリコンウェーハにも高品質化が要求され、これに対応した各種シリコンウェーハが開発されている。特に、製品特性に直接影響を与えると推測されるウェーハ表層部の結晶性は重要であり、その改善策として、（１）不活性ガス又は水素を含む雰囲気中での高温熱処理、（２）引き上げ条件の改善によるグローイン（Ｇｒｏｗｎ−ｉｎ）欠陥の低減、（３）ウェーハ上にエピタキシャル成長させる等の方法が開発されている。 With the miniaturization and high performance of semiconductor devices such as solid-state imaging devices such as memory and CCD, in order to improve the yield of those products, the quality of silicon wafers as materials is also required, and this is supported. Various silicon wafers have been developed. In particular, the crystallinity of the wafer surface layer, which is presumed to have a direct effect on the product characteristics, is important. As measures for improvement, (1) high-temperature heat treatment in an atmosphere containing inert gas or hydrogen, (2) pulling up Methods such as reduction of grown-in defects by improving conditions and (3) epitaxial growth on a wafer have been developed.
従来のシリコンウェーハ表面品質の電気的特性評価法としては、酸化膜耐圧（ＧＯＩ：Ｇａｔｅ Ｏｘｉｄｅ Ｉｎｔｅｇｒｉｔｙ）評価が用いられてきた（特許文献１参照）。
これは、まずシリコンウェーハ表面に熱酸化によりゲート酸化膜を形成し、この上に電極を形成する。そして、絶縁体であるシリコン酸化膜に電気的ストレスを印加し、この絶縁度合いによりシリコンウェーハの表面品質を評価するものである。すなわち、もとのシリコンウェーハ表面に欠陥や金属不純物が存在すると、これが熱酸化によりシリコン酸化膜に取り込まれたり、表面形状に応じた酸化膜が形成され、不均一な絶縁体になる等により、絶縁性が低下することから、シリコンウェーハの表面品質を評価できるものである。
As a conventional method for evaluating the electrical characteristics of the surface quality of a silicon wafer, an oxide film breakdown voltage (GOI) evaluation has been used (see Patent Document 1).
First, a gate oxide film is formed on a silicon wafer surface by thermal oxidation, and an electrode is formed thereon. Then, an electrical stress is applied to the silicon oxide film as an insulator, and the surface quality of the silicon wafer is evaluated based on the degree of insulation. That is, if there are defects or metal impurities on the original silicon wafer surface, this is taken into the silicon oxide film by thermal oxidation, an oxide film according to the surface shape is formed, and it becomes a non-uniform insulator, etc. Since the insulation is lowered, the surface quality of the silicon wafer can be evaluated.
このような酸化膜耐圧評価は、実デバイスにおいては、ＭＯＳＦＥＴのゲート酸化膜信頼性を示し、これの改善に向けていろいろなウェーハ開発が行われている。しかしながら、ＧＯＩ評価で問題がなくても、デバイス歩留まりが低下するということは当然ありえるわけであるが、特に近年、デバイスの高集積化に伴い、このような事象が数多くなってきている。 Such oxide film withstand voltage evaluation shows the reliability of MOSFET gate oxide film in actual devices, and various wafer developments have been made to improve this. However, even if there is no problem in the GOI evaluation, it is naturally possible that the device yield is lowered, but in recent years, in particular, with the high integration of devices, such a phenomenon has been increasing.
このような半導体基板の評価方法としては、リーク電流測定があるが（特許文献２参照）、とりわけ固体撮像素子においては、その原理から考えて、例えば暗電流を低減して感度向上を考えた場合、ウェーハ起因のリーク電流を低減する必要性がある。
しかしながら、リーク電流測定を精度良く、かつ安定した簡便な構造で行うことはできず、実デバイスに近い構造を作製して評価する等、日数・費用をかけて行うことが必要であった。また、このようにして測定したにも関わらず、リーク源の特定には、他の物理解析を組み合わせる必要があり、シリコンウェーハ等の半導体基板の改善に結び付けるには多大な努力が必要とされてきた。
As a method for evaluating such a semiconductor substrate, there is a leakage current measurement (see Patent Document 2). In particular, in the case of a solid-state imaging device, in consideration of the principle, for example, when a dark current is reduced to improve sensitivity. There is a need to reduce the leakage current caused by the wafer.
However, leak current measurement cannot be performed with high accuracy and a stable and simple structure, and it has been necessary to perform a number of days and costs such as making and evaluating a structure close to an actual device. In spite of the measurement, it is necessary to combine other physical analysis to identify the leak source, and much effort has been required to improve the semiconductor substrate such as a silicon wafer. It was.
本発明は上記問題点に鑑みてなされたもので、その目的は、ＣＣＤ、ＣＭＯＳセンサ等の高歩留まりが要求される製品に使用される高品質ウェーハのリーク電流の測定において、リーク源である欠陥種を簡易な方法で正確に特定することができる半導体基板の評価方法を提供することである。 The present invention has been made in view of the above problems, and its object is to provide a defect that is a leak source in the measurement of the leakage current of a high-quality wafer used in a product that requires a high yield, such as a CCD or CMOS sensor. An object of the present invention is to provide a method for evaluating a semiconductor substrate in which the species can be accurately identified by a simple method.
上記目的を達成するために、本発明では、半導体基板をリーク電流により評価する方法であって、評価対象である半導体基板にＰＮ接合を形成し、該ＰＮ接合が形成された半導体基板の基板温度を変化させながらリーク電流を測定し、この測定結果をプロットすることによって得られる前記リーク電流の温度特性から、前記評価対象である半導体基板に含まれる欠陥種を特定することを特徴とする半導体基板の評価方法を提供する。 In order to achieve the above object, the present invention is a method for evaluating a semiconductor substrate by a leakage current, wherein a PN junction is formed on a semiconductor substrate to be evaluated, and the substrate temperature of the semiconductor substrate on which the PN junction is formed. A semiconductor substrate characterized in that a defect type included in the semiconductor substrate to be evaluated is specified from a temperature characteristic of the leakage current obtained by measuring a leakage current while changing the value and plotting the measurement result Provides an evaluation method.
このような本発明の評価方法であれば、リーク電流測定により、他の物理解析等を用いることなく、当該リーク原因となっている欠陥種を特定することができる。従って、簡易な方法で、半導体基板を精度良く評価することができるため、半導体基板の品質向上に大きく貢献することができる。 With such an evaluation method of the present invention, the defect type that causes the leak can be identified by measuring the leak current without using other physical analysis or the like. Therefore, the semiconductor substrate can be accurately evaluated by a simple method, which can greatly contribute to the improvement of the quality of the semiconductor substrate.
このとき、前記欠陥種を特定する方法として、既知の欠陥を含む半導体基板のリーク電流の温度特性を調べることで、前記既知の欠陥を含む半導体基板に含まれている欠陥種にそれぞれ応じたリーク電流の温度特性データのデータベースを予め作成し、該データベースに登録したリーク電流の温度特性データと前記評価対象である半導体基板のリーク電流の温度特性データとを照らし合わせることによって、前記評価対象である半導体基板に含まれる欠陥種を特定することが好ましい。 At this time, as a method for specifying the defect type, the leakage characteristics corresponding to the defect type included in the semiconductor substrate including the known defect are determined by examining the temperature characteristics of the leakage current of the semiconductor substrate including the known defect. A current temperature characteristic data database is created in advance, and the leakage current temperature characteristic data registered in the database is compared with the leakage current temperature characteristic data of the semiconductor substrate to be evaluated. It is preferable to specify the defect type contained in the semiconductor substrate.
このように評価することで、より高精度で欠陥種の特定を効率的に行うことができる。 By evaluating in this way, it is possible to efficiently identify the defect type with higher accuracy.
このとき、前記欠陥種を、金属汚染による欠陥及び前記半導体基板の加工中に導入される欠陥の少なくともいずれか一方とすることが好ましい。 At this time, it is preferable that the defect type is at least one of a defect caused by metal contamination and a defect introduced during processing of the semiconductor substrate.
このような欠陥種であれば、特にリーク電流の温度特性の欠陥による特異点が明確に生じるため、より確実に欠陥種の特定を行うことができ、さらに、これらの欠陥の種類を特定することで半導体基板の品質の向上に貢献できる。 With such defect types, a singular point due to defects in the temperature characteristics of the leakage current is clearly generated, so that the defect types can be identified more reliably, and further, the types of these defects must be specified. Can contribute to improving the quality of semiconductor substrates.
またこのとき、前記半導体基板を、シリコンウェーハとすることができる。 At this time, the semiconductor substrate can be a silicon wafer.
このように、本発明の評価方法においては、評価する半導体基板としてシリコンウェーハとすることができる。 Thus, in the evaluation method of the present invention, a silicon wafer can be used as the semiconductor substrate to be evaluated.
以上のように、本発明によれば、例えばＣＣＤ、ＣＭＯＳセンサ等の高歩留まりが要求される製品に使用される半導体基板のリーク源の欠陥種を、簡便かつ高精度に評価することが可能になり、これにより、高品質な半導体基板を提供することができる。 As described above, according to the present invention, it is possible to easily and accurately evaluate a defect type of a leak source of a semiconductor substrate used for a product requiring a high yield such as a CCD or a CMOS sensor. Thus, a high-quality semiconductor substrate can be provided.
従来、リーク電流測定そのものは実施されていたが、このリーク源についてはその他の評価法から考察する方法しかなく、リーク源の特定まで評価するためには、測定のコストの悪化や評価の長時間化が生じていた。 Conventionally, leakage current measurement itself has been carried out, but there is only a method of considering this leakage source from other evaluation methods. In order to evaluate the leakage source, the cost of measurement is deteriorated and the evaluation time is long. Has occurred.
これに対して、本発明者が鋭意研究を重ねた結果、半導体基板のリーク電流の温度特性評価を行うという簡易な方法で、半導体基板のリーク源となる欠陥種まで特定することができることを見出し、本発明を完成させた。 On the other hand, as a result of intensive studies by the present inventors, it has been found that it is possible to identify a defect type that becomes a leak source of a semiconductor substrate by a simple method of performing a temperature characteristic evaluation of the leakage current of the semiconductor substrate. The present invention has been completed.
以下、本発明の実施形態について図を参照して説明するが、本発明はこれに限定されるものではない。
図１は、本発明の半導体基板の評価方法の実施形態の一例を示すフロー図である。
Hereinafter, although an embodiment of the present invention is described with reference to figures, the present invention is not limited to this.
FIG. 1 is a flowchart showing an example of an embodiment of a semiconductor substrate evaluation method of the present invention.
まず図１（ａ）に示すように、評価対象である半導体基板を準備する。
本発明で評価できる半導体基板としては特には限定されないが、例えばシリコンウェーハとすることができる。
First, as shown in FIG. 1A, a semiconductor substrate to be evaluated is prepared.
Although it does not specifically limit as a semiconductor substrate which can be evaluated by this invention, For example, it can be set as a silicon wafer.
次に図１（ｂ）に示すように、準備した半導体基板にＰＮ接合（接合構造）を作製する。作製する接合構造は、どのような構造でも特に限定されないが、構造起因のリーク電流（基板成分）をできるだけ低減するように作製することが好ましい。 Next, as shown in FIG. 1B, a PN junction (junction structure) is formed on the prepared semiconductor substrate. There is no particular limitation on the bonding structure to be manufactured, but it is preferable to manufacture the bonding structure so as to reduce leakage current (substrate component) due to the structure as much as possible.
作製方法としては、例えばＰｙｒｏ酸化（パイロジェニック酸化）等の熱酸化やＣＶＤ酸化等により基板表面に酸化膜を形成し、その一部をエッチング除去し、基板と異なる導電型のドーパントをイオン注入、ガラスデポ、塗布拡散等により拡散させてＰＮ接合を作製することができる。 As a manufacturing method, for example, an oxide film is formed on the substrate surface by thermal oxidation such as Pyro oxidation (pyrogenic oxidation) or CVD oxidation, a part of the oxide film is removed by etching, and a dopant having a conductivity type different from that of the substrate is ion-implanted. A PN junction can be produced by diffusing by glass deposition, coating diffusion, or the like.
そして図１（ｃ）−（ｅ）に示すように、ＰＮ接合が形成された半導体基板の基板温度を変化させながらリーク電流を測定する。すなわち、図１（ｃ）に示すように、まず基板温度を室温にした状態で、接合部に逆バイアスを印加してリーク電流測定を行う。そして、図１（ｄ）に示すように、基板温度を室温から例えば１０℃上昇させて、図１（ｅ）に示すように、当該昇温後の基板温度でリーク電流測定を行う。
さらに、昇温、リーク電流測定を繰り返して、基板温度を低温から高温側へスキャンしながらリーク電流値を測定し、図１（ｆ）に示すように、基板温度とリーク電流のプロットを作成して、リーク電流の温度特性を得ることができる。
Then, as shown in FIGS. 1C to 1E, the leakage current is measured while changing the substrate temperature of the semiconductor substrate on which the PN junction is formed. That is, as shown in FIG. 1C, first, a leakage current measurement is performed by applying a reverse bias to the junction with the substrate temperature at room temperature. Then, as shown in FIG. 1D, the substrate temperature is raised from room temperature, for example, by 10 ° C., and as shown in FIG. 1E, the leakage current is measured at the substrate temperature after the temperature rise.
Furthermore, repeat the temperature rise and leak current measurement to measure the leak current value while scanning the substrate temperature from the low temperature side to the high temperature side, and create a plot of the substrate temperature and the leak current as shown in FIG. Thus, the temperature characteristics of the leakage current can be obtained.
この測定の際には、１箇所のデータではなく、複数箇所のデータを取得することが好ましい。
これは、１箇所の測定では、基板上の不良箇所を必ずしも検出できるわけではないためである。欠陥密度が小さいと、それだけ多数の測定が必要になり、具体的な測定箇所の数は、評価対象の半導体基板に依存するため、最適数を適時設定することが好ましい。
In this measurement, it is preferable to acquire data at a plurality of locations instead of data at one location.
This is because it is not always possible to detect a defective portion on the substrate by measurement at one location. If the defect density is small, a large number of measurements are required, and the number of specific measurement points depends on the semiconductor substrate to be evaluated. Therefore, it is preferable to set the optimum number in a timely manner.
そして、図１（ｇ）に示すように、上記のように作成したプロットから、データベースとの照合によりリーク源の欠陥種を特定することができる。
この際、例えば、既知の欠陥を含む半導体基板のリーク電流の温度特性を調べることで、前記既知の欠陥を含む半導体基板に含まれている欠陥種にそれぞれ応じたリーク電流の温度特性データのデータベースを予め作成し、該データベースに登録したリーク電流の温度特性データと評価対象である半導体基板のリーク電流の温度特性データとを照らし合わせることによって、評価対象である半導体基板に含まれる欠陥種を特定することが好ましい。
このように既知の欠陥を含む半導体基板の温度特性を予め調べておくことで、実際の評価の際に得られたプロットにおいて、予め作成した温度特性のデータベースと同様の傾向（同様の特異点）が認められば、当該既知の欠陥を含む半導体基板であることを確実に特定することができる。
Then, as shown in FIG. 1G, the defect type of the leak source can be identified from the plot created as described above by collating with the database.
At this time, for example, by examining the temperature characteristics of the leakage current of the semiconductor substrate including a known defect, a database of temperature characteristics data of the leakage current corresponding to each defect type included in the semiconductor substrate including the known defect The defect type included in the evaluation target semiconductor substrate is identified by comparing the temperature characteristic data of the leakage current registered in the database with the temperature characteristic data of the leakage current of the evaluation target semiconductor substrate. It is preferable to do.
By examining the temperature characteristics of a semiconductor substrate including known defects in advance in this way, the same tendency as that of a database of temperature characteristics created in advance in the plots obtained during actual evaluation (similar singularities) If it is recognized, it can be surely specified that the semiconductor substrate includes the known defect.
以下、さらに詳細に本発明の評価方法において欠陥種を特定する方法を説明する。
本発明においてリーク電流を測定した結果、欠陥種類に応じて、特定の温度帯で、リーク電流の温度特性に特異点が観察される。すなわち、急激にリーク電流が増加し、また減少するというものである。これ以外にも、傾きの異なるリーク電流などが観察される。この温度依存性からは活性化エネルギーを算出することが可能であり、プロットの傾きがこれに相当する。このことから、傾きが変化するということは、活性化エネルギーが変化することであり、特異な温度依存をもつということは、欠陥の特性を示している。シリコンに作製された接合であれば、高温側では拡散成分といわれるリーク電流（基板からの拡散電流）が支配的であり、この際温度特性から得られる傾き、すなわち、リーク電流を縦軸に、温度の逆数を横軸にとってプロットした結果からは、シリコンのバンドギャップに相当する、１．１ｅＶの傾きが観察される。また、低温側では、発生成分といわれるリーク電流（空乏層内の発生電流）が支配的であり、バンドギャップの半分、すなわち０．５５ｅＶの傾きに理論的にはなる（図２の式（１）、（２）、グラフ、及び、非特許文献１参照）。
Hereinafter, a method for identifying the defect type in the evaluation method of the present invention will be described in more detail.
As a result of measuring the leakage current in the present invention, a singular point is observed in the temperature characteristics of the leakage current in a specific temperature zone according to the type of defect. That is, the leakage current increases and decreases abruptly. In addition to this, leakage currents having different slopes are observed. The activation energy can be calculated from this temperature dependence, and the slope of the plot corresponds to this. From this, changing the slope means changing the activation energy, and having a specific temperature dependence indicates a defect characteristic. If the junction is made of silicon, the leakage current (diffusion current from the substrate), which is called a diffusion component, is dominant on the high temperature side, and the slope obtained from the temperature characteristics, that is, the leakage current on the vertical axis, From the result of plotting the reciprocal of temperature on the horizontal axis, a slope of 1.1 eV corresponding to the band gap of silicon is observed. On the low temperature side, a leak current (generated current in the depletion layer), which is called a generated component, is dominant, and theoretically becomes a half band gap, that is, a slope of 0.55 eV (the expression (1 in FIG. 2) ), (2), graph, and non-patent document 1).
図２の式（１）（２）から分かるように、シリコンのバンドギャップのエネルギー差が式に含まれており、このバンド端に起因するものであれば、これらの式に相当する電流で説明できる。一方、例えば金属汚染による欠陥や半導体基板の加工中に導入される欠陥のようなシリコンのバンドギャップ内に準位を作るものであれば、このエネルギー差は異なったものになる。
すなわち、例えば金属汚染による欠陥や半導体基板の加工中に導入される欠陥が無い半導体基板のリーク電流の温度特性をプロットすると、図２のグラフのように、高温側では傾き１．１ｅＶに近く、低温側では０．５５ｅＶの傾きに近いプロットが得られる。一方、上記欠陥を有する基板のリーク電流の温度特性をプロットすると、それぞれの欠陥種によって異なる特異点が生じ、この特異点の位置（温度）等により欠陥種を特定することができる。
As can be seen from the equations (1) and (2) in FIG. 2, the energy difference of the band gap of silicon is included in the equation, and if it is caused by this band edge, it will be described with the current corresponding to these equations. it can. On the other hand, this energy difference is different if a level is created in the silicon band gap, such as a defect caused by metal contamination or a defect introduced during processing of a semiconductor substrate.
That is, for example, when plotting the temperature characteristics of the leakage current of a semiconductor substrate free from defects due to metal contamination or defects introduced during the processing of the semiconductor substrate, as shown in the graph of FIG. On the low temperature side, a plot close to a slope of 0.55 eV is obtained. On the other hand, when the temperature characteristics of the leakage current of the substrate having the defect is plotted, a singular point that differs depending on each defect type is generated, and the defect type can be specified by the position (temperature) of the singular point.
尚、本発明において特定することができる「半導体基板の加工中に導入される欠陥」とは、単結晶育成後の基板形状への加工工程において熱応力や機械的応力等によって導入される欠陥を意味する。酸素析出物、ＯＳＦ、ＣＯＰ等の単結晶製造時に導入されるＧｒｏｗｎ−ｉｎ欠陥に比べ、半導体基板の加工中に導入される転位等の欠陥や、金属汚染による欠陥は、リーク電流の温度特性において、顕著に特異点が生じるため、本発明によって、リーク源となっている欠陥種を特に正確に特定することができる。また、金属汚染による欠陥の場合、金属の種類によりエネルギー準位が異なるので、本発明であれば、汚染された金属の種類までをも推定できる。 The “defect introduced during processing of a semiconductor substrate” that can be specified in the present invention refers to a defect introduced by thermal stress, mechanical stress, or the like in the processing step to the substrate shape after single crystal growth. means. Compared to Grown-in defects introduced during the manufacture of single crystals such as oxygen precipitates, OSF, and COP, defects such as dislocations introduced during processing of semiconductor substrates and defects due to metal contamination are related to the temperature characteristics of leakage current. Since a singular point is remarkably generated, the present invention makes it possible to specify the defect type that is a leak source particularly accurately. In the case of a defect due to metal contamination, the energy level varies depending on the type of metal. Therefore, according to the present invention, even the type of contaminated metal can be estimated.
以上のような本発明の半導体基板の評価方法であれば、リーク電流の原因となる欠陥種を特定することが精度良くできるため、ウェーハの高性能化などに有効となる。さらに、本発明の方法はリーク電流測定の際に行うことができるため、簡易な方法で実施でき、生産性等の悪化はほとんどない。また、具体的には、汚染種が特定されることで、汚染除去の対象が明確になったり、半導体基板の加工中に導入される欠陥であることが分かれば、工程を改善して、この欠陥を低減することを効果的に行うことができる。 With the semiconductor substrate evaluation method of the present invention as described above, it is possible to specify the defect type causing the leak current with high accuracy, which is effective for improving the performance of the wafer. Furthermore, since the method of the present invention can be performed at the time of measuring the leakage current, it can be carried out by a simple method and there is almost no deterioration in productivity. Specifically, if the contamination species is identified and the object of decontamination becomes clear or it is known that the defect is introduced during the processing of the semiconductor substrate, the process is improved. Defects can be effectively reduced.
以下、実施例を示して本発明をより具体的に説明するが、本発明は下記の実施例に限定されるものではない。 Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited to the following examples.
（実施例１）
抵抗率１０Ω・ｃｍのボロンドープ直径２００ｍｍシリコンウェーハを材料として、まず、このウェーハに、Ｐｙｒｏ雰囲気１０００℃、９０分の熱処理で、厚さ２００ｎｍの酸化膜を形成した。この後、レジストを塗布し、フォトリソを行った。今回はネガレジストを選択した。このレジスト付きウェーハをバッファードＨＦ溶液にて酸化膜をエッチングし、硫酸過酸化水素混合液にてレジストを除去後、ＲＣＡ洗浄を実施した。このウェーハに、加速電圧５５ＫｅＶ、ドーズ量２×１０１２ａｔｏｍｓ／ｃｍ２でボロンをイオン注入し、１０００℃、窒素雰囲気下で回復アニール後、リンガラスを塗布拡散し、リンを表面より拡散することで、ＰＮ接合を形成した。
Example 1
Using a boron-doped diameter 200 mm silicon wafer having a resistivity of 10 Ω · cm as a material, an oxide film having a thickness of 200 nm was first formed on the wafer by heat treatment at 1000 ° C. for 90 minutes in a Pyro atmosphere. Thereafter, a resist was applied and photolithography was performed. This time I chose negative resist. The resist-coated wafer was etched with an oxide film with a buffered HF solution, and the resist was removed with a sulfuric acid hydrogen peroxide mixed solution, followed by RCA cleaning. Boron ions are implanted into this wafer at an acceleration voltage of 55 KeV and a dose of 2 × 10 12 atoms / cm 2 , and after recovery annealing in a nitrogen atmosphere at 1000 ° C., phosphorus glass is applied and diffused, and phosphorus is diffused from the surface. Thus, a PN junction was formed.
図１（ｃ）−（ｆ）に示す本発明の方法により、ＰＮ接合を形成したウェーハのリーク電流の温度特性測定を行った結果を図３に示す。このリーク電流測定は、上記素子作製済みウェーハを、温度調整が可能なプローバのチャック上にマウントし、昇温しながら、その都度、各温度でのリーク電流値を測定した。なおリーク電流は、逆バイアスを印加したときの電流値とした。測定温度範囲は、室温（３０℃）から１００℃の範囲として、室温から温度を上げながら１０℃刻みでリーク電流を測定した。
図３に示すように、得られた温度特性では、高温側では拡散電流が支配的な場合に観察される１．１ｅＶの傾き、低温側では発生電流が支配的な場合に観察される０．５５ｅＶの傾きを示すリーク電流となっており、特異な点は見られず、理論どおりのプロットである。これより、リーク源となるような欠陥が実施例１の半導体基板表面付近には存在しないことが分かる。
FIG. 3 shows the result of measuring the temperature characteristics of the leakage current of the wafer on which the PN junction is formed by the method of the present invention shown in FIGS. In this leakage current measurement, the device-fabricated wafer was mounted on a chuck of a prober capable of adjusting the temperature, and each time the temperature was raised, the leakage current value at each temperature was measured. The leakage current was a current value when a reverse bias was applied. The measurement temperature range was from room temperature (30 ° C.) to 100 ° C., and the leakage current was measured in increments of 10 ° C. while raising the temperature from room temperature.
As shown in FIG. 3, in the obtained temperature characteristics, a slope of 1.1 eV observed when the diffusion current is dominant on the high temperature side, and 0. 0 which is observed when the generated current is dominant on the low temperature side. The leak current shows a slope of 55 eV, no peculiar point is seen, and the plot is as expected. From this, it can be seen that there is no defect that can be a leak source near the surface of the semiconductor substrate of the first embodiment.
（実施例２）
まず、金属汚染による欠陥の影響を求めた。
抵抗率１０Ω・ｃｍのボロンドープ直径２００ｍｍシリコンウェーハを材料として、まず、このウェーハに、Ｐｙｒｏ雰囲気１０００℃、９０分の熱処理で、厚さ２００ｎｍの酸化膜を形成した。この酸化膜形成前のウェーハには、タングステン等の高融点金属が１×１０９ａｔｏｍｓ／ｃｍ２存在していることを、他の分析により確認した。
この後、レジストを塗布し、フォトリソを行った。今回はネガレジストを選択した。このレジスト付きウェーハをバッファードＨＦ溶液にて酸化膜をエッチングし、硫酸過酸化水素混合液にてレジストを除去後、ＲＣＡ洗浄を実施した。その後、このウェーハに、加速電圧５５ＫｅＶ、ドーズ量２×１０１２ａｔｏｍｓ／ｃｍ２でボロンをイオン注入し、１０００℃、窒素雰囲気下で回復アニール後、リンガラスを塗布拡散し、リンを表面より拡散することで、ＰＮ接合を形成した。
(Example 2)
First, the effect of defects due to metal contamination was determined.
Using a boron-doped diameter 200 mm silicon wafer having a resistivity of 10 Ω · cm as a material, an oxide film having a thickness of 200 nm was first formed on the wafer by heat treatment at 1000 ° C. for 90 minutes in a Pyro atmosphere. It was confirmed by other analysis that refractory metal such as tungsten was present at 1 × 10 9 atoms / cm 2 on the wafer before the oxide film was formed.
Thereafter, a resist was applied and photolithography was performed. This time I chose negative resist. The resist-coated wafer was etched with an oxide film with a buffered HF solution, and the resist was removed with a sulfuric acid hydrogen peroxide mixed solution, followed by RCA cleaning. Thereafter, boron is ion-implanted into this wafer at an acceleration voltage of 55 KeV and a dose amount of 2 × 10 12 atoms / cm 2 , and after recovery annealing in a nitrogen atmosphere at 1000 ° C., phosphorus glass is applied and diffused, and phosphorus is diffused from the surface. As a result, a PN junction was formed.
実施例１と同様に、ＰＮ接合を形成したウェーハのリーク電流を測定した。温度特性測定の結果を図４に示す。
図４から分かるように、高温側では拡散電流が支配的な場合に観察される１．１ｅＶの傾きのリーク電流となっているが、低温側では発生電流が支配的な場合に観察される０．５５ｅＶの傾きに対して、６０℃（１０００／Ｔ＝３．０）付近で急激なリーク電流の変化が見られる。この特異点は、金属汚染による欠陥に関係するものであることがわかる。なお、金属汚染による欠陥の場合、６０℃付近で急激なリークが現れる理由については不明である。
As in Example 1, the leakage current of the wafer on which the PN junction was formed was measured. The result of the temperature characteristic measurement is shown in FIG.
As can be seen from FIG. 4, the leak current has a slope of 1.1 eV observed when the diffusion current is dominant on the high temperature side, but is 0 when the generated current is dominant on the low temperature side. With respect to the slope of .55 eV, a sudden change in the leakage current is observed at around 60 ° C. (1000 / T = 3.0). This singularity is found to be related to defects due to metal contamination. In the case of defects due to metal contamination, the reason why a rapid leak appears around 60 ° C. is unknown.
（実施例３）
次に、ウェーハの加工中に導入される欠陥の影響を求めた。
抵抗率１０Ω・ｃｍのボロンドープ、直径２００ｍｍシリコンウェーハを材料として、このウェーハに、Ｐｙｒｏ雰囲気１０００℃、９０分の熱処理で、厚さ２００ｎｍの酸化膜を形成した。この酸化膜形成前のウェーハには、転位が高密度で発生していることを他の分析により確認した。
この後、レジストを塗布し、フォトリソを行った。今回はネガレジストを選択した。このレジスト付きウェーハを、バッファードＨＦ溶液にて酸化膜をエッチングし、硫酸過酸化水素混合液にてレジストを除去後、ＲＣＡ洗浄を実施した。このウェーハに、加速電圧５５ＫｅＶ、ドーズ量２×１０１２ａｔｏｍｓ／ｃｍ２でボロンをイオン注入し、１０００℃、窒素雰囲気下で回復アニール後、リンガラスを塗布拡散し、リンを表面より拡散することで、ＰＮ接合を形成した。
(Example 3)
Next, the influence of defects introduced during wafer processing was determined.
Using a boron-doped, 200 mm diameter silicon wafer having a resistivity of 10 Ω · cm as a material, an oxide film having a thickness of 200 nm was formed on this wafer by heat treatment at 1000 ° C. for 90 minutes in a Pyro atmosphere. It was confirmed by other analyzes that dislocations were generated at a high density in the wafer before the oxide film was formed.
Thereafter, a resist was applied and photolithography was performed. This time I chose negative resist. The oxide-coated wafer was etched with a buffered HF solution, and the resist was removed with a sulfuric acid / hydrogen peroxide mixture, followed by RCA cleaning. Boron ions are implanted into this wafer at an acceleration voltage of 55 KeV and a dose of 2 × 10 12 atoms / cm 2 , and after recovery annealing in a nitrogen atmosphere at 1000 ° C., phosphorus glass is applied and diffused, and phosphorus is diffused from the surface. Thus, a PN junction was formed.
実施例１と同様に、ＰＮ接合を形成したウェーハのリーク電流を測定した。温度特性測定の結果を図５に示す。
図５から分かるように、高温側の拡散電流が支配的に観察される１．１ｅＶの傾き、及び低温側の発生電流が支配的な場合に観察される０．５５ｅＶの傾きのいずれの傾きに対しても、急激なリーク電流の変化が見られている。これは転位に関係するものであることがわかる。なお、加工中に導入された欠陥の場合、このように高温側及び低温側の広範囲にわたり急激なリークが現れる理由については不明である。
As in Example 1, the leakage current of the wafer on which the PN junction was formed was measured. The result of the temperature characteristic measurement is shown in FIG.
As can be seen from FIG. 5, the slope of 1.1 eV where the diffusion current on the high temperature side is dominantly observed and the slope of 0.55 eV observed when the generated current on the low temperature side is dominant are shown. On the other hand, a sudden change in leakage current is observed. It can be seen that this is related to dislocations. In the case of defects introduced during processing, it is unclear why such a rapid leak appears over a wide range on the high temperature side and the low temperature side.
（実施例４）
次に、欠陥種が未知のウェーハのリーク源の欠陥種を以下のように特定した。
抵抗率１０Ω・ｃｍのボロンドープ直径２００ｍｍシリコンウェーハを材料として、このウェーハに、Ｐｙｒｏ雰囲気１０００℃、９０分の熱処理で、厚さ２００ｎｍの酸化膜を形成した。
この後、レジストを塗布し、フォトリソを行った。今回はネガレジストを選択した。このレジスト付きウェーハを、バッファードＨＦ溶液にて酸化膜をエッチングし、硫酸過酸化水素混合液にてレジストを除去後、ＲＣＡ洗浄を実施した。このウェーハに、加速電圧５５ＫｅＶ、ドーズ量２×１０１２ａｔｏｍｓ／ｃｍ２でボロンをイオン注入し、１０００℃、窒素雰囲気下で回復アニール後、リンガラスを塗布拡散し、リンを表面より拡散することで、ＰＮ接合を形成した。
(Example 4)
Next, the defect type of the leak source of the wafer whose defect type is unknown was specified as follows.
Using a boron-doped diameter 200 mm silicon wafer having a resistivity of 10 Ω · cm as a material, an oxide film having a thickness of 200 nm was formed on this wafer by a heat treatment at 1000 ° C. for 90 minutes in a Pyro atmosphere.
Thereafter, a resist was applied and photolithography was performed. This time I chose negative resist. The oxide-coated wafer was etched with a buffered HF solution, and the resist was removed with a sulfuric acid / hydrogen peroxide mixture, followed by RCA cleaning. Boron ions are implanted into this wafer at an acceleration voltage of 55 KeV and a dose of 2 × 10 12 atoms / cm 2 , and after recovery annealing in a nitrogen atmosphere at 1000 ° C., phosphorus glass is applied and diffused, and phosphorus is diffused from the surface. Thus, a PN junction was formed.
実施例１と同様に、ＰＮ接合を形成したウェーハのリーク電流を測定し、その温度特性を得た。
この場合、高温側及び低温側の広範囲にわたり急激なリークの変化が見られた。上記の結果から、この温度帯に特異点が生じた場合には、リークの原因としては、転位に関係するものであることが推定できる。従って、当該ウェーハのリーク源の欠陥種は、転位であることがわかった。
Similar to Example 1, the leakage current of the wafer on which the PN junction was formed was measured, and its temperature characteristics were obtained.
In this case, a sudden change in leakage was observed over a wide range on the high temperature side and the low temperature side. From the above results, when a singular point occurs in this temperature range, it can be estimated that the cause of the leak is related to dislocation. Therefore, it was found that the defect type of the leak source of the wafer is dislocation.
以上のように、実施例２，３のように、既知の欠陥を含む基板のリーク電流の温度特性を調べ、欠陥種による温度特性の違いをデータベースに登録しておくことで、実施例４のように、未知の欠陥を含む基板を評価する際に、登録データと照らし合わせて、容易かつ高精度にリーク源の欠陥種を特定することができる。 As described above, as in the second and third embodiments, the temperature characteristics of the leakage current of the substrate including known defects are examined, and the difference in temperature characteristics depending on the defect type is registered in the database. As described above, when a substrate including an unknown defect is evaluated, the defect type of the leak source can be identified easily and with high accuracy in comparison with the registered data.
なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は、例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。 The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
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| JPH1131725A (en) * | 1997-05-15 | 1999-02-02 | Komatsu Denshi Kinzoku Kk | Method for evaluating silicon wafer and silicon wafer |
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