JP5528000B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- JP5528000B2 JP5528000B2 JP2009092317A JP2009092317A JP5528000B2 JP 5528000 B2 JP5528000 B2 JP 5528000B2 JP 2009092317 A JP2009092317 A JP 2009092317A JP 2009092317 A JP2009092317 A JP 2009092317A JP 5528000 B2 JP5528000 B2 JP 5528000B2
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- H01L24/93—Batch processes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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Description
本発明は、ＤＲＡＭ、フラッシュメモリ等の半導体メモリに好適に用いられる半導体装置の製造方法に関する。特に集積回路（ＩＣ）が作製されたチップを複数積層してパッケージ化した、いわゆる３次元実装された半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device suitably used for a semiconductor memory such as a DRAM or a flash memory. In particular, the present invention relates to a method for manufacturing a so-called three-dimensionally mounted semiconductor device in which a plurality of chips on which an integrated circuit (IC) is manufactured are stacked and packaged.
ＣＭＯＳ回路が作製された半導体層を、ハンドル基板に転写して３次元実装されたＩＣを製造する方法は、非特許文献１に記載されている。一例を挙げるなら、シリコンウエハの表面に多孔質シリコンからなる分離層を形成し、その上に単結晶シリコンからなる半導体層をエピタキシャル成長させ、その半導体層のＣＭＯＳ回路を作製する。 Non-Patent Document 1 describes a method of manufacturing an IC in which a semiconductor layer on which a CMOS circuit is manufactured is transferred to a handle substrate and three-dimensionally mounted. For example, a separation layer made of porous silicon is formed on the surface of a silicon wafer, and a semiconductor layer made of single crystal silicon is epitaxially grown on the separation layer to produce a CMOS circuit of the semiconductor layer.
続いて、ＣＭＯＳ回路が作製された半導体層をハンドル基板に貼り合わせ、分離層において分離を行い、半導体層をハンドル基板に転写する。この工程を複数回繰り返すことにより、ＣＭＯＳ回路が作製された半導体層を複数、ハンドル基板上に、積層する。 Subsequently, the semiconductor layer on which the CMOS circuit is manufactured is bonded to the handle substrate, separation is performed in the separation layer, and the semiconductor layer is transferred to the handle substrate. By repeating this process a plurality of times, a plurality of semiconductor layers on which CMOS circuits are manufactured are stacked on the handle substrate.
特許文献１には、２回の分離工程を経て形成される半導体層を有する２つの基板を半導体層同士が接合するように貼り合わせて、最後に片方の基板を分離する、３次元実装された半導体装置を製造するプロセスが記載されている。 In Patent Document 1, two substrates having semiconductor layers formed through two separation steps are bonded together so that the semiconductor layers are bonded to each other, and finally one substrate is separated, and three-dimensional mounting is performed. A process for manufacturing a semiconductor device is described.
しかしながら、従来の分離工程を含む転写技術は、半導体装置の製造プロセスにおける、いわゆる前工程に採用されるものであり、歩留まりなどのコスト要因から十分に廉価な製造方法ではなかった。 However, the conventional transfer technique including the separation step is employed in a so-called previous step in the manufacturing process of the semiconductor device, and is not a sufficiently inexpensive manufacturing method due to cost factors such as yield.
本発明は、このような背景技術に鑑みてなされたものである。本発明の目的は、いわゆる後工程に分離プロセスを適用し、低コストで３次元実装された半導体装置の製造方法を提供するものである。 The present invention has been made in view of such background art. An object of the present invention is to provide a method of manufacturing a semiconductor device that is three-dimensionally mounted at a low cost by applying a separation process to a so-called post-process.
本発明の半導体装置の製造方法は、
第１の半導体基板１１の表面に複数の第１の集積回路１７を作製する工程と、
第２の半導体基板１に設けられた第１の分離層２の上に形成された第１の半導体層３に、貫通電極４を有する複数の第２の集積回路７を作製する工程と、
前記第１の半導体基板と前記第２の半導体基板とを、前記第１の集積回路の接合部１６と、前記第２の集積回路の、前記貫通電極に接続された第１の接合部６とを接合するように貼り合せ、第１の貼り合わせ構造体を得る工程と、
前記第１の分離層で前記第１の貼り合せ構造体から前記第２の半導体基板を分離することにより、前記複数の第２の集積回路が作製された第１の半導体層３を前記第１の半導体基板１１に移設する工程と、
前記貫通電極を露出させ、前記第１の接合部と対向する側で前記貫通電極に接続された第２の接合部８を形成する工程と、
第３の半導体基板２１に設けられた第２の分離層２２の上に形成された第２の半導体層２３に、複数の第３の集積回路２７を作製する工程と、
前記第１の半導体層３と前記第２の半導体層２３とを、前記第２の集積回路の前記第２の接合部と前記第３の集積回路の接合部２８とを接合するように貼り合せ、第２の貼り合わせ構造体を得る工程と、
前記第２の分離層で前記第２の貼り合せ構造体から前記第３の半導体基板を分離することにより、前記複数の第３の集積回路２７が作製された第２の半導体層２３を前記第１の半導体基板に移設する工程と、
前記複数の第２及び第３の集積回路が移設された前記第１の半導体基板をダイシングして、前記第１の集積回路と前記第２の集積回路と前記第３の集積回路とを有する積層チップを得る工程と、を含む半導体装置の製造方法である。
A method for manufacturing a semiconductor device of the present invention includes:
Producing a plurality of first integrated circuits 17 on the surface of the first semiconductor substrate 11;
Producing a plurality of second integrated circuits 7 having through electrodes 4 in the first semiconductor layer 3 formed on the first isolation layer 2 provided on the second semiconductor substrate 1;
The first semiconductor substrate and the second semiconductor substrate are joined to the junction 16 of the first integrated circuit, and the first junction 6 connected to the through electrode of the second integrated circuit. Bonding to join, and obtaining a first bonded structure,
By separating the second semiconductor substrate from the first bonded structure with the first separation layer, the first semiconductor layer 3 on which the plurality of second integrated circuits are fabricated is formed as the first semiconductor layer 3. Transferring to the semiconductor substrate 11;
Exposing the through electrode and forming a second bonding portion 8 connected to the through electrode on a side facing the first bonding portion;
Producing a plurality of third integrated circuits 27 on the second semiconductor layer 23 formed on the second isolation layer 22 provided on the third semiconductor substrate 21;
The first semiconductor layer 3 and the second semiconductor layer 23 are bonded together so as to join the second junction portion of the second integrated circuit and the junction portion 28 of the third integrated circuit. Obtaining a second bonded structure; and
By separating the third semiconductor substrate from the second bonded structure with the second separation layer, the second semiconductor layer 23 in which the plurality of third integrated circuits 27 are fabricated is replaced with the second semiconductor layer 23. Transferring to one semiconductor substrate;
A stack having the first integrated circuit, the second integrated circuit, and the third integrated circuit obtained by dicing the first semiconductor substrate on which the plurality of second and third integrated circuits are transferred. And a step of obtaining a chip.
本発明によれば、貫通電極や接合部等を形成した後、つまり、後工程に分離プロセスを適用することで、低コストで３次元実装された半導体装置を製造できる。 According to the present invention, a semiconductor device that is three-dimensionally mounted can be manufactured at a low cost after a through electrode, a junction, or the like is formed, that is, by applying a separation process to a subsequent process.
以下、図面を参照しつつ本発明をより詳細に説明する。なお、同一の構成要素には原則として同一の参照番号を付して、説明を省略する。 Hereinafter, the present invention will be described in more detail with reference to the drawings. In principle, the same components are denoted by the same reference numerals, and description thereof is omitted.
（実施形態１）
図１は、本発明の一実施形態による半導体装置の製造方法を説明するための模式的断面図である。
(Embodiment 1)
FIG. 1 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.
まず、第１の半導体基板１１としてバルクシリコンウエハ、エピタキシャルシリコンウエハのような半導体基板を用意する。そして、周知の製造プロセスにより第１の半導体基板１１の表面側に、複数の第１の集積回路１７を作製する。ここで云う、第１の集積回路とは、後にチップ（ダイ）となる一つの集積回路部分である。例えば、ＤＲＡＭやフラッシュメモリであれば、多数のメモリセルと、メモリセルを選択する選択回路、メモリセルから信号を読み出したり、メモリセルに信号を書き込むための信号処理回路等を含む。この工程では分離・転写工程は伴わないことが好ましい。 First, a semiconductor substrate such as a bulk silicon wafer or an epitaxial silicon wafer is prepared as the first semiconductor substrate 11. Then, a plurality of first integrated circuits 17 are manufactured on the surface side of the first semiconductor substrate 11 by a known manufacturing process. The first integrated circuit referred to here is one integrated circuit portion that will later become a chip (die). For example, a DRAM or flash memory includes a large number of memory cells, a selection circuit for selecting the memory cells, a signal processing circuit for reading signals from the memory cells, and writing signals to the memory cells, and the like. This step preferably does not involve a separation / transfer step.
図１（ａ）に示すように、バルクシリコンウエハのような第２の半導体基板１に設けられた多孔質シリコンのような分離層２上に単結晶シリコンのような半導体層３を形成したウエハを用意する。そこに、複数（ここでは３つを図示している）の第２の集積回路７を作製する。また、ＭＯＳトランジスタのような素子及び多数のＭＯＳトランジスタを接続する多層配線を形成した後、半導体層３にスルーホールやビアホールと呼ばれる貫通孔を形成する。その貫通孔の内壁表面に絶縁膜を形成して絶縁性内壁表面とし、貫通孔内に導電体を充填して、貫通電極４を形成する（スルーシリコンビア技術）。この時、エッチング時間を調整して、溝の深さＤｔを半導体層３の厚さｔ３よりも小さくする。Ｄｔ＜ｔ３、つまり、溝４内の導電層の底が分離層２に到達しない程度に浅く形成する。半導体層３の厚さｔ３は１．０μｍ以上２０μｍ以下、より好ましくは１．０μｍ以上１０μｍ以下の範囲から選択しうる。例えば、ＣＭＯＳ回路を作製する場合には、１．０μｍ以上、２．０μｍ以下であり、メモリ構造を作製する場合には、種々の記憶電荷を保持する容量によって異なるが、１．０μｍ以上、１０．０μｍ以下である。穴又は溝の深さＤｔは、半導体層３の厚さの半分以上であって、溝の下方に半導体層３の２０分の１以下厚さの残留部を残すことが好ましいものである。つまり、ｔ３／２≦Ｄｔ＜ｔ３／２０×１を満足するように設計するとよい。導電体としては、スズ（Ｓｎ）、ニッケル（Ｎｉ）、銅（Ｃｕ）、金（Ａｕ）及びアルミニウム（Ａｌ）のうちのいずれか一つ、またはこれらのうちの少なくとも一つ以上で作製された合金で形成すると良い。 As shown in FIG. 1A, a wafer in which a semiconductor layer 3 such as single crystal silicon is formed on an isolation layer 2 such as porous silicon provided on a second semiconductor substrate 1 such as a bulk silicon wafer. Prepare. A plurality of (here, three are shown) second integrated circuits 7 are produced. Further, after forming an element such as a MOS transistor and a multilayer wiring for connecting a large number of MOS transistors, a through hole called a through hole or a via hole is formed in the semiconductor layer 3. An insulating film is formed on the inner wall surface of the through hole to form an insulating inner wall surface, and a conductor is filled in the through hole to form the through electrode 4 (through silicon via technology). At this time, the etching time is adjusted to make the groove depth Dt smaller than the thickness t 3 of the semiconductor layer 3. Dt <t3, that is, shallow enough that the bottom of the conductive layer in the groove 4 does not reach the isolation layer 2. The thickness t3 of the semiconductor layer 3 can be selected from the range of 1.0 μm to 20 μm, more preferably 1.0 μm to 10 μm. For example, when a CMOS circuit is manufactured, the thickness is 1.0 μm or more and 2.0 μm or less, and when a memory structure is manufactured, it varies depending on a capacity for holding various storage charges, but is 1.0 μm or more, 10 μm or more. 0.0 μm or less. The depth Dt of the hole or groove is preferably half or more of the thickness of the semiconductor layer 3, and it is preferable to leave a residual portion having a thickness of 1/20 or less of the semiconductor layer 3 below the groove. That is, it is preferable to design so as to satisfy t3 / 2 ≦ Dt <t3 / 20 × 1. The conductor is made of any one of tin (Sn), nickel (Ni), copper (Cu), gold (Au), and aluminum (Al), or at least one of these. It is good to form with an alloy.
その後、はんだや金からなる接合部６（接合パッドとも言う。）を形成する。こうして、図１（ａ）に示す構造体が得られる。図では判りやすいように、貫通電極や接合部の位置を集積回路のチップの内側に描いているが、通常、貫通電極や接合部は、集積回路のチップの周辺部分に設けられる。この工程でも分離・転写工程は伴わないことが好ましい。 Thereafter, a joint 6 (also referred to as a joint pad) made of solder or gold is formed. Thus, the structure shown in FIG. 1A is obtained. For easy understanding, the position of the through electrode and the joint is drawn inside the chip of the integrated circuit, but the through electrode and the joint are usually provided in the peripheral portion of the chip of the integrated circuit. Even in this step, it is preferable that no separation / transfer step is involved.
本発明において貫通電極とは、各チップの集積回路の配線と接続されており、チップ同士を積層した場合は、配線と電気的に接続できる機能を有する。具体的には電源供給ライン、入出力ライン、クロック信号ライン、グランドラインになり得る。 In the present invention, the through electrode is connected to the wiring of the integrated circuit of each chip, and has a function of being electrically connected to the wiring when the chips are stacked. Specifically, it can be a power supply line, an input / output line, a clock signal line, or a ground line.
分離層２としては、多孔質体からなる分離層が好ましく用いられ、例えば、シリコンウエハの表面を陽極化成してえられる多孔質シリコン層などが用いられる。陽極化成を行う際には、Ｐ＋型又はＮ＋型の基板を用いるか、少なくとも陽極化成する領域がＰ＋型又はＮ＋型となるようにＰ型又はＮ型の不純物をドープしておくことが好ましい。本発明においては特にＰ＋型の基板を用いるか、少なくとも陽極化成する領域がＰ＋型となるようにＰ型の不純物をドープしておくことが好ましい。 As the separation layer 2, a separation layer made of a porous material is preferably used. For example, a porous silicon layer obtained by anodizing the surface of a silicon wafer is used. When anodizing is performed, a P + -type or N + -type substrate is used, or a P-type or N-type impurity is doped so that at least the region to be anodized becomes P + -type or N + -type. It is preferable. In the present invention, it is particularly preferable to use a P + type substrate or dope a P type impurity so that at least the region to be anodized becomes P + type.
また本発明においては、上記Ｐ＋型又はＮ＋型の領域抵抗率を調整して導電性を高め、必要に応じて多孔質層の一部を残存させて、チップ化した際に電磁波等のノイズに対するシールドとして機能させることもできる。 In the present invention, the P + type or N + type region resistivity is adjusted to increase the conductivity, and if necessary, a part of the porous layer is left to form a chip when a chip is formed. It can also function as a shield against noise.
また、図１（ｂ）に示すように、予め、第１の半導体基板１１を用意し、その表面に複数の第１の集積回路１７を作製する。ここでは、貫通電極１４が描かれているが、この第１の半導体基板１１を薄層化しない場合には、この貫通電極１４は必ずしも必要ではない。そして、集積回路１７の表面にはんだや金からなる接合部１６を形成する。こうして、ハンドル基板となる、第１の集積回路１７が形成された半導体基板からなる構造体が得られる。 Further, as shown in FIG. 1B, a first semiconductor substrate 11 is prepared in advance, and a plurality of first integrated circuits 17 are formed on the surface thereof. Here, the through electrode 14 is depicted, but the through electrode 14 is not necessarily required when the first semiconductor substrate 11 is not thinned. Then, a joint 16 made of solder or gold is formed on the surface of the integrated circuit 17. In this way, a structure made of a semiconductor substrate on which the first integrated circuit 17 is formed, which becomes a handle substrate, is obtained.
これに、図１（ｂ）に示すように、第２の半導体基板１と、第１の半導体基板１１とを、それぞれの接合部６，１６が形成された面同士を向かい合わせにする。そして、間に接着剤１８を介在させて、接合部の無い領域において、第１及び第２の半導体基板を接着する。この時、接合部同士も接合させ、電気的に短絡しておく。これにより、貼り合わせ構造体が得られる。 As shown in FIG. 1B, the second semiconductor substrate 1 and the first semiconductor substrate 11 are made to face each other on which the respective joint portions 6 and 16 are formed. Then, the first and second semiconductor substrates are bonded to each other in an area where there is no bonding portion with an adhesive 18 interposed therebetween. At this time, the joint portions are also joined and electrically short-circuited. Thereby, a bonded structure is obtained.
接着剤を用いる場合には、フリップリップボンディングした第１及び第２の半導体基板（貼り合わせ構造体）の周囲をディスペンサ等によりアクリル樹脂のような封止部材で一旦囲う。その封止部材の一部に開口を設けて硬化させておき、その開口から内部空間により粘性の低い接着剤を導入し、硬化させる。この接着剤の充填技術は液晶パネルの製造方法において用いられている、周知の液晶材料の充填する方法と同様である。或いは、いずれか一方の半導体基板の表面における接合部の設けられていない領域に、粒子状の接着剤（接着ビーズ）を分散配置しておき、他方の半導体基板をフリップチップボンディングする際に、同時に接着ビーズを変形させて硬化してもよい。これらの方法により介在させた接着剤は、後に分離層２において半導体層３を分離する際に、接合部のみの接着力に頼らず、２つの半導体基板の接着強度を増すために用いられる。 When an adhesive is used, the periphery of the first and second semiconductor substrates (bonded structures) subjected to flip lip bonding is once surrounded by a sealing member such as an acrylic resin by a dispenser or the like. An opening is provided in a part of the sealing member and cured, and an adhesive having a low viscosity is introduced into the internal space from the opening and cured. This adhesive filling technique is the same as the known liquid crystal material filling method used in the liquid crystal panel manufacturing method. Alternatively, particle adhesives (adhesive beads) are dispersedly arranged in a region where no bonding portion is provided on the surface of one of the semiconductor substrates, and when the other semiconductor substrate is flip-chip bonded, The adhesive beads may be deformed and cured. The adhesive interposed by these methods is used to increase the adhesive strength between the two semiconductor substrates without depending on the adhesive force of only the joint when the semiconductor layer 3 is separated later in the separation layer 2.
本発明において用いることができる好ましい接着剤としては、低粘度、低不純物、高耐候性、低脱ガス、低収縮性、１６０℃における耐熱性、高接着力、低熱膨張率、高熱伝導率、高体積抵抗率を満たす接着剤を選択することが好ましい。これらの条件を満たす接着剤としては、例えば、アクリル系、メタクリル系（アクリレート系）、エポキシ系（酸無水物硬化剤）、ポリイミド系、ポリイミドアミド系（ポロイミド＝ナイロン変性系）の接着剤を挙げることができる。そしてこれらの接着剤を接合表面（基板又はチップ表面）に塗布し、一定のタック性を残した状態で乾燥した後、所定の荷重をかけて、所定の温度で熱処理を行う。 Preferred adhesives that can be used in the present invention include low viscosity, low impurities, high weather resistance, low degassing, low shrinkage, heat resistance at 160 ° C., high adhesive strength, low thermal expansion coefficient, high thermal conductivity, high It is preferable to select an adhesive that satisfies the volume resistivity. Examples of adhesives that satisfy these conditions include acrylic, methacrylic (acrylate), epoxy (anhydride curing agents), polyimide, and polyimideamide (polyimide = nylon-modified) adhesives. be able to. Then, these adhesives are applied to the bonding surface (substrate or chip surface), dried with a certain tackiness left, and then subjected to heat treatment at a predetermined temperature under a predetermined load.
また、貼りあわせの接着剤と導通の両方を兼ねるものとして、厚さ方向に対しては電気的に短絡して、横方向に対しては隣接する接合パッド間を絶縁する異方性導電フィルムやペーストを用いてもよい。 In addition, as both an adhesive for bonding and conduction, an anisotropic conductive film that electrically shorts in the thickness direction and insulates between adjacent bonding pads in the lateral direction. A paste may be used.
また本発明においては、接着剤の代わりまたは接着剤に加えて、接着剤として機能するフィルム（ホットメルトシート）を用いて接着することも可能である。本発明においては例えば日立化成工業株式会社製のダイボンディングフィルム、ＦＨシリーズ、ＤＦシリーズ、ＨＳシリーズ、アンダーフィル用フィルム、ＵＦシリーズ等を使用することができる。 Moreover, in this invention, it is also possible to adhere | attach using the film (hot melt sheet) which functions as an adhesive agent instead of an adhesive agent or in addition to an adhesive agent. In the present invention, for example, a die bonding film manufactured by Hitachi Chemical Co., Ltd., FH series, DF series, HS series, underfill film, UF series and the like can be used.
続いて、図１の（ｃ）に示すような２つの半導体基板１，１１が接合された構造体の側面に研磨粒子を含まない高圧の水流を吹き付ける。そして、分離層２において、貼り合わせ構造体から第２の半導体基板１を分離する。換言すると、半導体層３を第２の半導体基板１から剥離する。こうして、図１（ｄ）に示すように、複数の集積回路が作製された半導体層３が、第２の半導体基板１から第１の半導体基板１１上に移設、転写される。 Subsequently, a high-pressure water stream containing no abrasive particles is sprayed on the side surface of the structure in which the two semiconductor substrates 1 and 11 are joined as shown in FIG. Then, in the separation layer 2, the second semiconductor substrate 1 is separated from the bonded structure. In other words, the semiconductor layer 3 is peeled from the second semiconductor substrate 1. In this way, as shown in FIG. 1D, the semiconductor layer 3 on which a plurality of integrated circuits are manufactured is transferred from the second semiconductor substrate 1 onto the first semiconductor substrate 11 and transferred.
分離方法は、上述したようないわゆるウオータージェット法に限らず、窒素等の高圧ガスを吹き付けるガスジェット法でもよく、要するに楔の作用をもつ流体を吹き付ければよい。或いは、金属などの固体からなる楔を２枚の半導体基板間に打ち込んで機械的に分離してもよい。図では２枚の半導体基板の側面が揃っているように描かれているが、実際には、半導体基板の面取り部（べべリング部）により２枚の半導体基板間には窪み（凹部）が形成されている。よって、この部分に楔を挿入することにより、２枚の半導体基板が互いに離れるような方向の力ベクトルを加えれば、両者は機械的強度の低い分離層２において分離される。勿論、始めに、固体の楔で貼り合わせ構造体の分離を開始し、次いで、流体の楔で貼り合わせ構造体を完全に分離してもよい。 The separation method is not limited to the so-called water jet method as described above, but may be a gas jet method in which a high-pressure gas such as nitrogen is blown. In short, a fluid having a wedge action may be blown. Alternatively, a wedge made of a solid such as a metal may be driven between two semiconductor substrates and mechanically separated. In the drawing, the side surfaces of the two semiconductor substrates are drawn so as to be aligned, but in reality, a recess (concave portion) is formed between the two semiconductor substrates by the chamfered portion (beveling portion) of the semiconductor substrate. Has been. Therefore, if a force vector is applied in such a direction that the two semiconductor substrates are separated from each other by inserting a wedge in this portion, the two are separated in the separation layer 2 having low mechanical strength. Of course, the separation of the bonded structure may be started first with a solid wedge, and then the bonded structure may be completely separated with a fluid wedge.
ここで、分離後の分離層２は、第１の半導体基板１１の半導体層側、又は第２の半導体基板側、或いは両者の側に残留し得る。特に、分離層として多孔質体の多孔度が異なる少なくとも２つの多孔質層の積層体を用いれば、多孔質層の界面に近い部分であって相対的に多孔度の高い多孔質層に亀裂が形成され、当該多孔質層の界面に沿って分離がなされる。 これにより、残留多孔質層の厚さは、集積回路が作製される半導体基板表面部分の全体に亘って均一な厚さとなる。（図１（ｄ）参照）
その後、必要に応じて残留する分離層２をエッチング等により除去し、半導体層３の裏面を露出させる。貫通電極４が露出するまで、半導体層３の裏面をエッチングし、貫通電極４を露出させた後、はんだや金などにより接合部８を形成する。
Here, the separated separation layer 2 can remain on the semiconductor layer side of the first semiconductor substrate 11, the second semiconductor substrate side, or both sides. In particular, if a laminate of at least two porous layers having different porosities is used as the separation layer, the porous layer having a relatively high porosity near the interface between the porous layers is cracked. Formed and separated along the interface of the porous layer. Thereby, the thickness of the residual porous layer is uniform over the entire surface of the semiconductor substrate on which the integrated circuit is manufactured. (See Fig. 1 (d))
Thereafter, the remaining separation layer 2 is removed by etching or the like as necessary, and the back surface of the semiconductor layer 3 is exposed. The back surface of the semiconductor layer 3 is etched until the through electrode 4 is exposed. After the through electrode 4 is exposed, the joint 8 is formed using solder, gold, or the like.
こうして、図１（ｅ）に示すように、２つの集積回路が積層された構造体が得られる。２層でよい場合には、この構造体をダイシングソーにより、隣接する集積回路間の領域（破線）に溝を形成して貼り合わせ構造体を切断し、各集積回路をチップ状に分離独立させるダイシングを行う。 In this way, a structure in which two integrated circuits are stacked is obtained as shown in FIG. When two layers are sufficient, this structure is formed in a region (broken line) between adjacent integrated circuits by a dicing saw, and the bonded structure is cut to separate each integrated circuit into chips. Dicing is performed.
こうして、少なくとも第１の集積回路と第２の集積回路とを有する積層チップ、即ち３次元実装された半導体装置が製造できる。 Thus, a laminated chip having at least a first integrated circuit and a second integrated circuit, that is, a three-dimensionally mounted semiconductor device can be manufactured.
（実施形態２）
本実施形態は、３層以上の集積回路が作製された半導体層または半導体基板を積層するものである。
(Embodiment 2)
In this embodiment, a semiconductor layer or a semiconductor substrate on which three or more layers of integrated circuits are manufactured is stacked.
まず、前述した実施形態１において得られる図１（ｅ）の構造体と同じ構造体３０を用意する。また、図１（ａ）の構造体と同じ構造体３１を用意する。 First, the same structure 30 as the structure of FIG.1 (e) obtained in Embodiment 1 mentioned above is prepared. In addition, the same structure 31 as the structure shown in FIG.
そして、これら構造体３０、３１を、接着剤を介して互いに貼り合わせ、更に、分離層２２において分離を行い、３層以上の集積回路が作製された半導体層を積層する。 Then, these structural bodies 30 and 31 are bonded to each other via an adhesive, and further separated in the separation layer 22 to stack a semiconductor layer in which three or more integrated circuits are manufactured.
半導体基板の貼り合わせ方法や分離方法は、前述した実施形態１と同様の方法を用いることができる。図２（ｂ）は、集積回路が作製された２つめの半導体層２３が、積層構造体３０上に転写された状態を示す。そして、必要に応じて、残留多孔質層２３を除去する。 As a method for bonding and separating semiconductor substrates, the same method as that of the first embodiment described above can be used. FIG. 2B shows a state in which the second semiconductor layer 23 in which the integrated circuit is manufactured is transferred onto the laminated structure 30. And the residual porous layer 23 is removed as needed.
その後、図２（ｃ）に示すように、実施形態１と同様に半導体層２３に形成された貫通電極２４を露出させて、はんだや金からなる接合部２８を形成する。 Thereafter, as shown in FIG. 2C, the through electrode 24 formed in the semiconductor layer 23 is exposed in the same manner as in the first embodiment, and the joint portion 28 made of solder or gold is formed.
更に、図２（ｃ）に示す構造体をダイシングソーにより、隣接する集積回路間の領域（破線）に溝を形成して貼り合わせ構造体を切断し、各集積回路をチップ状に分離独立させるダイシングを行う。 Further, the structure shown in FIG. 2C is formed in a region (broken line) between adjacent integrated circuits by using a dicing saw to cut the bonded structure so that the integrated circuits are separated into chips. Dicing is performed.
図３は、こうして得られた、少なくとも３つの集積回路が積層された積層チップ、即ち、３次元実装された半導体装置を示している。この後、金属やセラミックスなどからなる実装基板上にダイボンディングされ、パッケージ化される。図３は、縦方向を拡大して描いているが、実際には厚さ（図中縦方向の長さ）より、チップサイズ（図中横方向の長さ）の方がかなり大きい。 FIG. 3 shows a stacked chip obtained by stacking at least three integrated circuits, that is, a three-dimensionally mounted semiconductor device. Thereafter, it is die-bonded on a mounting substrate made of metal, ceramics, etc., and packaged. Although FIG. 3 is drawn by enlarging the vertical direction, the chip size (length in the horizontal direction in the figure) is actually considerably larger than the thickness (length in the vertical direction in the figure).
以上の実施形態において、第１の半導体基板１１や、各半導体層３、２３に作製される集積回路は、同一の回路でもよく、別の回路でもよい。同一の回路の場合には、集積回路としては、ＤＲＡＭのような記憶保持動作が必要な半導体メモリや、フラッシュメモリと称されるＥＥＰＲＯＭ、ＭＲＡＭ等の不揮発性半導体メモリが好ましく用いられる。積層数も、図示した３層に限らす、８層以上、より好ましくは１２層以上であり得る。 In the above embodiment, the integrated circuit manufactured in the first semiconductor substrate 11 and the semiconductor layers 3 and 23 may be the same circuit or different circuits. In the case of the same circuit, as the integrated circuit, a semiconductor memory such as a DRAM that requires a memory holding operation and a nonvolatile semiconductor memory such as an EEPROM or MRAM called a flash memory are preferably used. The number of stacked layers is also limited to the illustrated three layers, and may be 8 layers or more, more preferably 12 layers or more.
また、半導体基板１１を薄層化しない場合には、当該半導体基板１１に作製される集積回路のみを、他の集積回路とは異なる回路（例えば、ロジックＩＣ）とすることも好ましいものである。 In addition, when the semiconductor substrate 11 is not thinned, it is preferable that only an integrated circuit manufactured on the semiconductor substrate 11 is a circuit (for example, a logic IC) different from other integrated circuits.
（実施形態３）
本実施形態は、本発明の半導体装置の製造方法により得られた積層チップの一部拡大図である。
(Embodiment 3)
This embodiment is a partially enlarged view of a multilayer chip obtained by the method for manufacturing a semiconductor device of the present invention.
図４は、同一チップサイズの３つの集積回路が積層された部分の断面を示している。図４の下方には、不図示の同一チップサイズの集積回路チップがあり、それに図４に示す構造体が積層されたものが、本実施形態の積層チップである。 FIG. 4 shows a cross section of a portion where three integrated circuits having the same chip size are stacked. In the lower part of FIG. 4, there is an integrated circuit chip of the same chip size (not shown), and the stacked structure of FIG. 4 is the stacked chip of this embodiment.
半導体メモリなどの集積回路７が作製された半導体層３には、貫通電極４と接合部としてのはんだバンプ８が形成されている。その上には、同じ半導体メモリからなる集積回路２７が作製された半導体層２３が積層され、半導体層２３には、貫通電極２４と接合部としてのはんだバンプ２８が形成されている。 In the semiconductor layer 3 on which the integrated circuit 7 such as a semiconductor memory is manufactured, the through electrode 4 and a solder bump 8 as a joint portion are formed. On top of that, a semiconductor layer 23 on which an integrated circuit 27 made of the same semiconductor memory is fabricated is laminated, and a through-electrode 24 and solder bumps 28 as joints are formed on the semiconductor layer 23.
更にその上に、半導体メモリからなる集積回路３７が作製された半導体層３３が積層されている。ここで、一番上の半導体層３３においては、分離層３２を除去することなく、半導体層３３上に残している。 Furthermore, a semiconductor layer 33 on which an integrated circuit 37 made of a semiconductor memory is manufactured is laminated thereon. Here, the uppermost semiconductor layer 33 is left on the semiconductor layer 33 without removing the separation layer 32.
貫通電極３４は、下方の貫通電極２４、４上に積層されるように配置され、互いに導通をとるように短絡している。それぞれの半導体層３、２３、３３の部分では、貫通孔内壁が絶縁膜で形成されているので、各半導体層と貫通孔内部でショートすることはない。一方、最上部に位置する半導体層３３の表面に残留させた多孔質体からなる分離層３２は、高濃度のほう素を含むシリコンからなる低抵抗層である。そのため、分離層と貫通電極３４とを互いに短絡させ、分離層層３２を、電気シールド層として利用することにより、積層チップの誤動作や静電破壊等を防止することができる。貫通電極３４とそれに繋がる貫通電極４、２４は、各半導体層のＰ型ボディ部分を相互に電気的に短絡させるボディコンタクトである。このボディコンタクトは、ｐＭＯＳトランジスタのＮ型半導体ウエルが形成されるところのＰ型のボディ部分（分離された半導体層の共通部分）を、不図示の配線層を通じて電気的に互いに短絡させるとともに、接地される。この多孔質体からなる層３２に代えて、高濃度ドープのＰ＋半導体層又は金属層を設けることもできる。 The through electrode 34 is disposed so as to be stacked on the lower through electrodes 24 and 4 and is short-circuited so as to be electrically connected to each other. In each of the semiconductor layers 3, 23, and 33, the inner wall of the through hole is formed of an insulating film, so that there is no short circuit between each semiconductor layer and the through hole. On the other hand, the separation layer 32 made of a porous material remaining on the surface of the semiconductor layer 33 located at the uppermost part is a low resistance layer made of silicon containing a high concentration of boron. Therefore, by causing the separation layer and the through electrode 34 to be short-circuited with each other and using the separation layer layer 32 as an electric shield layer, it is possible to prevent malfunction of the multilayer chip, electrostatic breakdown, and the like. The through electrode 34 and the through electrodes 4 and 24 connected to the through electrode 34 are body contacts that electrically short-circuit the P-type body portions of the respective semiconductor layers. The body contact electrically shorts P-type body portions (common portions of separated semiconductor layers) where the N-type semiconductor well of the pMOS transistor is formed through a wiring layer (not shown) and Is done. Instead of the porous layer 32, a highly doped P + semiconductor layer or metal layer may be provided.
１ 第２の半導体基板
２ 分離層
３ 半導体層
６ 接合部
７ 第２の集積回路
１１ 第１の半導体基板
１６ 接合部
１７ 第１の集積回路
DESCRIPTION OF SYMBOLS 1 2nd semiconductor substrate 2 Separation layer 3 Semiconductor layer 6 Junction part 7 2nd integrated circuit 11 1st semiconductor substrate 16 Junction part 17 1st integrated circuit
Claims (2)
第２の半導体基板に設けられた第１の分離層の上に形成された第１の半導体層に、貫通電極を有する複数の第２の集積回路を作製する工程と、
前記第１の半導体基板と前記第２の半導体基板とを、前記第１の集積回路の接合部と、前記第２の集積回路の、前記貫通電極に接続された第１の接合部とを接合するように貼り合せ、第１の貼り合わせ構造体を得る工程と、
前記第１の分離層で前記第１の貼り合せ構造体から前記第２の半導体基板を分離することにより、前記複数の第２の集積回路が作製された第１の半導体層を前記第１の半導体基板に移設する工程と、
前記貫通電極を露出させ、前記第１の接合部と対向する側で前記貫通電極に接続された第２の接合部を形成する工程と、
第３の半導体基板に設けられた第２の分離層の上に形成された第２の半導体層に、複数の第３の集積回路を作製する工程と、
前記第１の半導体層と前記第２の半導体層とを、前記第２の集積回路の前記第２の接合部と前記第３の集積回路の接合部とを接合するように貼り合せ、第２の貼り合わせ構造体を得る工程と、
前記第２の分離層で前記第２の貼り合せ構造体から前記第３の半導体基板を分離することにより、前記複数の第３の集積回路が作製された第２の半導体層を前記第１の半導体基板に移設する工程と、
前記複数の第２及び第３の集積回路が移設された前記第１の半導体基板をダイシングして、前記第１の集積回路と前記第２の集積回路と前記第３の集積回路とを有する積層チップを得る工程と、を含む半導体装置の製造方法。 Producing a plurality of first integrated circuits on a surface of a first semiconductor substrate;
Producing a plurality of second integrated circuits having through electrodes in a first semiconductor layer formed on a first isolation layer provided on a second semiconductor substrate;
The first semiconductor substrate and the second semiconductor substrate are joined to the joint portion of the first integrated circuit and the first joint portion of the second integrated circuit connected to the through electrode. Bonding, and obtaining a first bonded structure;
By separating the second semiconductor substrate from the first bonded structure with the first separation layer, the first semiconductor layer in which the plurality of second integrated circuits are manufactured is changed to the first semiconductor layer. Transferring to a semiconductor substrate;
Exposing the through electrode and forming a second joint connected to the through electrode on a side facing the first joint;
Producing a plurality of third integrated circuits in a second semiconductor layer formed on a second isolation layer provided on a third semiconductor substrate;
The first semiconductor layer and the second semiconductor layer are bonded to each other so as to join the second junction of the second integrated circuit and the junction of the third integrated circuit, and a second Obtaining a bonded structure of
By separating the third semiconductor substrate from the second bonded structure by the second separation layer, the second semiconductor layer in which the plurality of third integrated circuits are manufactured is changed to the first semiconductor layer. Transferring to a semiconductor substrate;
A stack having the first integrated circuit, the second integrated circuit, and the third integrated circuit obtained by dicing the first semiconductor substrate on which the plurality of second and third integrated circuits are transferred. And a step of obtaining a chip.
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