JP5400279B2 - 半導体装置及びその製造方法並びに半導体製造装置 - Google Patents
半導体装置及びその製造方法並びに半導体製造装置 Download PDFInfo
- Publication number
- JP5400279B2 JP5400279B2 JP2007151619A JP2007151619A JP5400279B2 JP 5400279 B2 JP5400279 B2 JP 5400279B2 JP 2007151619 A JP2007151619 A JP 2007151619A JP 2007151619 A JP2007151619 A JP 2007151619A JP 5400279 B2 JP5400279 B2 JP 5400279B2
- Authority
- JP
- Japan
- Prior art keywords
- otp
- rom cell
- rom
- cell array
- program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/34—Source electrode or drain electrode programmed
Landscapes
- Semiconductor Memories (AREA)
- Weting (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
12 半導体チップ
14 回路部
20 ROM部
21 OTP−ROMセル配列
22 OTP−ROMセル
44 配線
55、56 薬液
80 プログラムヘッド
84 位置合わせ部
90 プログラムドット
Claims (3)
- 半導体ウエハ内に配列された複数の半導体チップとなるべき領域内にそれぞれ設けられたOTP−ROMセル配列に対応するプログラムドット配列を有するプログラムヘッドを、前記複数の半導体チップとなるべき領域のうち1つの領域内の前記OTP−ROMセル配列に位置合わせする工程と、
前記OTP−ROMセル配列を、それぞれ異なる構成の前記プログラムヘッドを用いて、前記複数の半導体チップとなるべき領域ごとに異なるパターンでプログラムする工程と、
を有し、
前記OTP−ROMセル配列をプログラムする工程は、前記OTP−ROMセル配列に含まれる複数のOTP−ROMセルに薬液を噴出させ、当該噴出された薬液を用いて前記OTP−ROMセル配列内の配線を接続することにより、前記複数のOTP−ROMセルを活性化または非活性化させることを特徴とする半導体装置の製造方法。 - 半導体ウエハ内に配列された複数の半導体チップとなるべき領域内にそれぞれ設けられたOTP−ROMセル配列に対応するプログラムドット配列を有するプログラムヘッドを、前記複数の半導体チップとなるべき領域のうち1つの領域内の前記OTP−ROMセル配列に位置合わせする工程と、
前記OTP−ROMセル配列を、それぞれ異なる構成の前記プログラムヘッドを用いて、前記複数の半導体チップとなるべき領域ごとに異なるパターンでプログラムする工程と、
を有し、
前記OTP−ROMセル配列をプログラムする工程は、前記OTP−ROMセル配列に含まれる複数のOTP−ROMセルに薬液を噴出させ、当該噴出された薬液を用いて前記OTP−ROMセル配列内の配線を切断することにより、前記複数のOTP−ROMセルを活性化または非活性化させることを特徴とする半導体装置の製造方法。 - 半導体ウエハ内に配列された複数の半導体チップとなるべき領域内にそれぞれ設けられたOTP−ROMセル配列に対応するプログラムドット配列を有するプログラムヘッドと、
前記プログラムヘッドを前記複数の半導体チップとなるべき領域のうち1つの領域内の
前記OTP−ROMセル配列に位置合わせする位置合わせ部と、を具備し、
前記プログラムヘッドは、それぞれ異なる構成を用いて、前記OTP−ROMセル配列を、前記複数の半導体チップとなるべき領域ごとに異なるパターンでプログラムし、
前記プログラムヘッドは、前記OTP−ROMセル配列に含まれる複数のOTP−ROMセルに噴出された薬液を用いて、前記OTP−ROMセル配列内の配線を接続または切断することにより、前記複数のOTP−ROMセルを活性化または非活性化させることを特徴とする半導体製造装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007151619A JP5400279B2 (ja) | 2007-06-07 | 2007-06-07 | 半導体装置及びその製造方法並びに半導体製造装置 |
US12/130,577 US8815652B2 (en) | 2007-06-07 | 2008-05-30 | Semiconductor device and method of manufacturing the same and semiconductor manufacturing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007151619A JP5400279B2 (ja) | 2007-06-07 | 2007-06-07 | 半導体装置及びその製造方法並びに半導体製造装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008305964A JP2008305964A (ja) | 2008-12-18 |
JP5400279B2 true JP5400279B2 (ja) | 2014-01-29 |
Family
ID=40136297
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007151619A Expired - Fee Related JP5400279B2 (ja) | 2007-06-07 | 2007-06-07 | 半導体装置及びその製造方法並びに半導体製造装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8815652B2 (ja) |
JP (1) | JP5400279B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8467215B2 (en) * | 2010-01-29 | 2013-06-18 | Brigham Young University | Permanent solid state memory |
KR20140095795A (ko) * | 2013-01-25 | 2014-08-04 | 삼성디스플레이 주식회사 | 디스플레이 패널 및 디스플레이 패널의 제조방법 |
KR102097568B1 (ko) | 2016-06-06 | 2020-04-06 | 도레이 카부시키가이샤 | 메모리 어레이, 메모리 어레이의 제조 방법, 메모리 어레이 시트, 메모리 어레이 시트의 제조 방법 및 무선 통신 장치 |
US11545499B2 (en) | 2020-10-06 | 2023-01-03 | International Business Machines Corporation | Read-only memory with vertical transistors |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000033712A (ja) * | 1997-09-30 | 2000-02-02 | Seiko Epson Corp | マイクロセンサーデバイス作成方法及びそれを用いた液体機能評価方法 |
EP1249042A1 (en) * | 2000-01-20 | 2002-10-16 | Zavitan Semiconductors, Inc. | Personalized hardware |
US7436032B2 (en) * | 2003-12-19 | 2008-10-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor integrated circuit comprising read only memory, semiconductor device comprising the semiconductor integrated circuit, and manufacturing method of the semiconductor integrated circuit |
JP2006236511A (ja) * | 2005-02-25 | 2006-09-07 | Toshiba Corp | 半導体集積回路装置 |
JP2007059948A (ja) * | 2006-11-27 | 2007-03-08 | Oki Electric Ind Co Ltd | 半導体チップ、半導体チップの製造方法、リードフレーム、リードフレームの製造方法、半導体装置及び半導体装置の製造方法。 |
-
2007
- 2007-06-07 JP JP2007151619A patent/JP5400279B2/ja not_active Expired - Fee Related
-
2008
- 2008-05-30 US US12/130,577 patent/US8815652B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US8815652B2 (en) | 2014-08-26 |
US20080316790A1 (en) | 2008-12-25 |
JP2008305964A (ja) | 2008-12-18 |
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