JP5396750B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP5396750B2
JP5396750B2 JP2008156435A JP2008156435A JP5396750B2 JP 5396750 B2 JP5396750 B2 JP 5396750B2 JP 2008156435 A JP2008156435 A JP 2008156435A JP 2008156435 A JP2008156435 A JP 2008156435A JP 5396750 B2 JP5396750 B2 JP 5396750B2
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Prior art keywords
oxide film
metal pad
film
semiconductor device
metal
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JP2008156435A
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JP2009302371A (en
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宏俊 立花
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Dicing (AREA)

Description

本発明は、半導体装置の製造方法に関し、特に、金属パッドを有する半導体装置の製造
方法に関する。 The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a metal pad.

半導体装置の製造プロセスにおいて、前処理工程の最終段階として、半導体ウェーハを
ダイシング装置により切断して複数の半導体装置毎にチップ状に分割する工程がある。半
導体ウェーハのダイシングの際には、半導体装置を冷却するために切削水が半導体ウェー
ハに供給される。切削水として、例えば純水が用いられる。 In the semiconductor device manufacturing process, as a final stage of the pretreatment process, there is a process of cutting a semiconductor wafer with a dicing apparatus and dividing the semiconductor wafer into a plurality of chips. When dicing the semiconductor wafer, cutting water is supplied to the semiconductor wafer in order to cool the semiconductor device. For example, pure water is used as the cutting water.

純水の比抵抗値は高いので、ダイシング中の半導体ウェーハに純水を供給すると静電気
が生じ易く、切断屑が半導体チップに付着してしまう。この解決策としては、純水に二酸
化炭素を混合して純水の比抵抗値を下げることにより、静電気の発生を防止する方法があ
る。 Since the specific resistance value of pure water is high, if pure water is supplied to the semiconductor wafer being diced, static electricity is likely to be generated, and cutting waste adheres to the semiconductor chip. As a solution to this, there is a method of preventing the generation of static electricity by mixing carbon dioxide with pure water to lower the specific resistance value of pure water.

しかし、二酸化炭素が混合された純水の酸性は高く、この純水は半導体チップの表面に
露出しているアルミニウムのボンディングパッドを腐食させる１つの原因になる。従って
、ダイシングにより分割された半導体チップのボンディングパッドの表面には、ダイシン
グ前に比べて腐食によって多数の空孔が発生する。空孔は、ボンディングパッドの実質的
なボンディング面積を減少させるので、ボンディングパッド表面にボンディングされる金
属ワイヤとの密着性を損なう原因となる。 However, the acidity of pure water mixed with carbon dioxide is high, and this pure water causes corrosion of the aluminum bonding pad exposed on the surface of the semiconductor chip. Therefore, a larger number of holes are generated on the surface of the bonding pad of the semiconductor chip divided by dicing due to corrosion than before dicing. Since the voids reduce the substantial bonding area of the bonding pad, it causes a loss of adhesion to the metal wire bonded to the bonding pad surface.

ボンディングパッドと金属ワイヤとの密着性を向上するための方法として、ボンディン
グパッドの表面に凹凸を形成することが知られている。しかし、ボンディングパッドの表
面に凹凸を形成しても、腐食によって多数の空孔が形成されることには変わりはなく、ボ
ンディングワイヤの密着性を改善することが難しい。 As a method for improving the adhesion between the bonding pad and the metal wire, it is known to form irregularities on the surface of the bonding pad. However, even if irregularities are formed on the surface of the bonding pad, there is no change in the formation of a large number of holes due to corrosion, and it is difficult to improve the adhesion of the bonding wire.

一方、ボンディングパッドの表面の空孔の発生を防止するために、半導体ウェーハのダ
イシングの前に、ポリイミドの揮発成分によりボンディングパッドの表面に保護膜を形成
し、その後にダイシングすることが知られている。 On the other hand, it is known that a protective film is formed on the surface of the bonding pad by a volatile component of polyimide before dicing the semiconductor wafer, and then dicing in order to prevent generation of holes on the surface of the bonding pad. Yes.

その保護膜の形成方法は、まず、別の基板にポリイミドを塗布し、この基板を半導体ウ
ェーハに対向させて配置させる。続いて、熱処理によって、熱硬化前のポリイミドの成分
を揮発させ、その揮発成分をボンディングパッド及びその周辺のパッシベーション膜の表
面に付着させ、保護膜を形成する。 In the method of forming the protective film, first, polyimide is applied to another substrate, and this substrate is disposed to face the semiconductor wafer. Subsequently, the component of the polyimide before thermosetting is volatilized by heat treatment, and the volatile component is attached to the surface of the bonding pad and the surrounding passivation film to form a protective film.

そのような方法においては、ポリイミドを基板に塗布する工程と、ポリイミドを熱処理
により揮発させて保護膜を形成する工程とを従来工程に加える必要がある上に、硬化した
ポリイミドを廃棄する必要がある。
特開２００４−１５８６７８号公報 特開２００８−４５９８号公報 In such a method, it is necessary to add a step of applying polyimide to the substrate and a step of volatilizing the polyimide by heat treatment to form a protective film, and it is necessary to discard the cured polyimide. .
JP 2004-158678 A JP 2008-4598 A

本発明の目的は、ダイシング後にパッドの表面に接続される金属物の密着性を改善する
ことができる半導体装置の製造方法を提供することにある。 An object of the present invention is to provide a method of manufacturing a semiconductor device that can improve the adhesion of a metal object connected to the surface of a pad after dicing.

本発明の１つの観点によれば、半導体基板の上方の絶縁膜上にアルミニウム、アルミニウム合金のいずれかを有する金属パッドを形成する工程と、酸素含有雰囲気内における熱処理により前記金属パッドの表面に金属酸化膜を形成する工程と、前記金属酸化膜を形成した後に、水を供給しながら前記半導体基板を切断することにより分割してチップを形成する工程と、超音波振動を併用する熱圧着により、前記金属酸化膜を消滅させながらワイヤの一端を前記チップ上の前記金属パッドにボンディングする工程と、を有することを特徴とする半導体装置の製造方法を提供する。
According to one aspect of the present invention, forming a metal pad with aluminum on the insulating film above the semiconductor substrate, one of the aluminum alloy, the surface of the metal pad by us Keru heat treatment in an oxygen-containing atmosphere Forming a metal oxide film on the substrate, forming a chip by cutting the semiconductor substrate while supplying water after forming the metal oxide film, and thermocompression bonding using ultrasonic vibration in combination Accordingly, that provides a method of manufacturing a semiconductor device characterized by having the steps of bonding one end of the wire while extinguished the metal oxide film on the metal pads on the chip.

本発明によれば、酸素含有雰囲気内において熱処理を行い、金属パッドの表面に金属酸
化膜を形成し、この後にダイシングを行ったので、金属パッドの表面のダイシングに起因
する腐食を防止することができ、金属パッドの表面とその表面に接続される金属物との密
着性を改善することができる。 According to the present invention, since heat treatment is performed in an oxygen-containing atmosphere, a metal oxide film is formed on the surface of the metal pad, and then dicing is performed, corrosion due to dicing on the surface of the metal pad can be prevented. In addition, the adhesion between the surface of the metal pad and the metal object connected to the surface can be improved.

以下に、本発明の実施形態を図面に基づいて詳細に説明する。
（第１の実施の形態）
図１は本発明の第１実施形態に係る半導体装置１の要部断面図である。この半導体装置
１は、半導体基板１０の上方の第ｎ層目の層間絶縁膜３６上に形成された金属パッド（ボ
ンディングパッド）４０と、金属パッド４０の表面に形成された金属酸化膜４１とを備え
ている。 Embodiments of the present invention will be described below in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a cross-sectional view of an essential part of a semiconductor device 1 according to the first embodiment of the present invention. The semiconductor device 1 includes a metal pad (bonding pad) 40 formed on an n-th interlayer insulating film 36 above the semiconductor substrate 10 and a metal oxide film 41 formed on the surface of the metal pad 40. I have.

半導体基板１０には例えばｎ型のシリコン単結晶基板が使用され、この半導体基板１０
の主面側の活性領域には複数のｐ型のウェル領域１１と複数のｎ型のウェル領域（不図示
）が形成されている。 For example, an n-type silicon single crystal substrate is used as the semiconductor substrate 10.
In the active region on the main surface side, a plurality of p-type well regions 11 and a plurality of n-type well regions (not shown) are formed.

活性領域であるウェル領域１１は、素子分離領域１２によって区画されている。素子分
離領域１２は、例えばシャロートレンチアイソレーション（ＳＴＩ）構造を採用し、ウェ
ル領域１１の表面から深さ方向に形成されたトレンチとその内部に埋設された絶縁体とを
備えて構成される。 The well region 11 which is an active region is partitioned by an element isolation region 12. The element isolation region 12 employs, for example, a shallow trench isolation (STI) structure, and includes a trench formed in the depth direction from the surface of the well region 11 and an insulator embedded therein.

なお、素子分離領域１２には、例えばウェル領域１１の表面をＬＯＣＯＳ法により選択
的に酸化して形成されたシリコン酸化膜を使用してもよい。 For the element isolation region 12, for example, a silicon oxide film formed by selectively oxidizing the surface of the well region 11 by the LOCOS method may be used.

活性領域であるウェル領域１１には、トランジスタＴが形成されている。トランジスタ
Ｔとして、ＭＯＳＦＥＴのような絶縁ゲート型電界効果トランジスタ（ＩＧＦＥＴ）が形
成されている。 A transistor T is formed in the well region 11 which is an active region. As the transistor T, an insulated gate field effect transistor (IGFET) such as a MOSFET is formed.

トランジスタＴは、チャネル形成領域として使用されるウェル領域１１と、ゲート絶縁
膜１５と、ゲート電極１６と、ソース／ドレイン領域１７ｓ、１７ｄとを有している。 The transistor T includes a well region 11 used as a channel formation region, a gate insulating film 15, a gate electrode 16, and source / drain regions 17s and 17d.

ゲート絶縁膜１５はウェル領域１１上に形成される。ゲート絶縁膜１５は、熱酸化法に
より形成してもよいし、ＣＶＤ法により形成してもよい。 The gate insulating film 15 is formed on the well region 11. The gate insulating film 15 may be formed by a thermal oxidation method or a CVD method.

ゲート電極１６Ａ、１６Ｂは、ゲート絶縁膜１５上に形成されたシリコン多結晶膜１６
ａと、このシリコン多結晶膜１６ａ上に形成された金属シリサイド膜１６ｂとを備える。 The gate electrodes 16A and 16B are formed of the silicon polycrystalline film 16 formed on the gate insulating film 15.
a and a metal silicide film 16b formed on the silicon polycrystalline film 16a.

ソース／ドレイン領域１７ｓ、１７ｄは、ウェル領域１１に形成された低不純物濃度領
域であるｎ型のエクステンション領域１７ａと、ウェル領域１１に形成された高不純物濃
度領域であるｎ型半導体領域１７ｂとを有している。ｎ型半導体領域１７ｂ上には金属シ
リサイド膜１７ｃが形成されている。 The source / drain regions 17 s and 17 d include an n-type extension region 17 a that is a low impurity concentration region formed in the well region 11 and an n-type semiconductor region 17 b that is a high impurity concentration region formed in the well region 11. Have. A metal silicide film 17c is formed on the n-type semiconductor region 17b.

エクステンション領域１７ａは、ゲート電極１６をマスクにしてその両側のウェル領域
１１に不純物をイオン注入することにより形成される。また、ｎ型半導体領域１７ｂは、
ゲート電極１６及びサイドウォールスペーサ１８をマスクとして不純物をイオン注入する
ことにより形成される。 The extension region 17a is formed by ion-implanting impurities into the well regions 11 on both sides of the gate electrode 16 as a mask. The n-type semiconductor region 17b is
An impurity is ion-implanted using the gate electrode 16 and the sidewall spacer 18 as a mask.

ここで、ゲート電極１６表面の金属シリサイド膜１６ｂ、ソース／ドレイン領域１７ｓ
、１７ｄ表面の金属シリサイド膜１７ｃのそれぞれは、製造プロセスにおいてサリサイド
技術を使用して同一工程により形成される。 Here, the metal silicide film 16b on the surface of the gate electrode 16 and the source / drain regions 17s.
Each of the metal silicide films 17c on the surface of 17d is formed by the same process using the salicide technique in the manufacturing process.

なお、第１実施形態においては、ｎチャネル導電型ＭＯＳＦＥＴのみ説明しているが、
本発明は、トランジスタＴとしてそれに限定されるものではなく、ｐチャネル導電型ＩＧ
ＦＥＴであってもよく、又双方のチャネル導電型ＭＯＳＦＥＴが混在してもよい。 In the first embodiment, only the n-channel conductivity type MOSFET is described.
The present invention is not limited to the transistor T, but is a p-channel conductivity type IG
It may be an FET, or both channel conductivity type MOSFETs may be mixed.

半導体基板１０上には、トランジスタＴを覆う絶縁膜２０と、絶縁膜２０上に形成され
た第１層目の層間絶縁膜２１とが形成される。絶縁膜２０はカバー絶縁膜として使用され
、この絶縁膜２０には例えばシリコン窒化膜が使用される。層間絶縁膜２１には例えばシ
リコン酸化膜が使用され、この層間絶縁膜２１の表面は化学機械研磨法等により平坦化さ
れる。 On the semiconductor substrate 10, an insulating film 20 covering the transistor T and a first-layer interlayer insulating film 21 formed on the insulating film 20 are formed. The insulating film 20 is used as a cover insulating film, and for example, a silicon nitride film is used as the insulating film 20. For example, a silicon oxide film is used as the interlayer insulating film 21, and the surface of the interlayer insulating film 21 is planarized by a chemical mechanical polishing method or the like.

絶縁膜２０及び層間絶縁膜２１にはトランジスタＴのソース／ドレイン領域１７ｓ、１
７ｄ上においてコンタクトホール２２が形成される。コンタクトホール２２内部には導電
性プラグ２３が形成され、導電性プラグ２３はソース／ドレイン領域１７ｓ、１７ｄ表面
の金属シリサイド膜１７ｃに電気的に接続される。 The insulating film 20 and the interlayer insulating film 21 have source / drain regions 17 s of the transistor T, 1
A contact hole 22 is formed on 7d. A conductive plug 23 is formed inside the contact hole 22 and the conductive plug 23 is electrically connected to the metal silicide film 17c on the surface of the source / drain regions 17s and 17d.

図示していないが、トランジスタＴのゲート電極１６は、導電性プラグを介してその上
の配線に接続される。この導電性プラグはゲート電極１６の金属シリサイド膜１６ｂに電
気的に接続される。 Although not shown, the gate electrode 16 of the transistor T is connected to the wiring thereon via a conductive plug. This conductive plug is electrically connected to the metal silicide film 16 b of the gate electrode 16.

導電性プラグ２３は、例えば、コンタクトホール２２内の底面及び側壁に沿って形成さ
れたグルー膜２３ａと、このグルー膜２３ａ上に形成されコンタクトホール２２内を埋め
込む金属膜２３ｂとを備えている。グルー膜２３ａには例えば窒化チタン（ＴｉＮ）膜が
使用され、金属膜２３ｂには例えばタングステン（Ｗ）膜が使用される。 The conductive plug 23 includes, for example, a glue film 23a formed along the bottom and side walls in the contact hole 22, and a metal film 23b formed on the glue film 23a and filling the contact hole 22. For example, a titanium nitride (TiN) film is used for the glue film 23a, and a tungsten (W) film is used for the metal film 23b.

層間絶縁膜２１上には、導電性プラグ２３に電気的に接続される第１層目の配線２４が
形成される。配線２４として、例えば、アルミニウム膜、又は銅（Ｃｕ）、シリコン（Ｓ
ｉ）若しくはチタン（Ｔｉ）の少なくとも１つが添加されたアルミニウム合金膜が使用さ
れる。 On the interlayer insulating film 21, a first layer wiring 24 electrically connected to the conductive plug 23 is formed. As the wiring 24, for example, an aluminum film, copper (Cu), silicon (S
An aluminum alloy film to which at least one of i) or titanium (Ti) is added is used.

図１において、配線２４は簡略化して示しているが、実際にはアルミニウム膜若しくは
アルミニウム合金膜と、その下層に形成されたバリアメタル膜と、その上層に形成された
反射防止膜とを備える。 In FIG. 1, the wiring 24 is shown in a simplified manner, but actually includes an aluminum film or an aluminum alloy film, a barrier metal film formed in the lower layer, and an antireflection film formed in the upper layer.

配線２４上には第２層目の層間絶縁膜２５が形成され、この層間絶縁膜２５にはビアホ
ール２６が形成されている。ビアホール２６内部にはその下の配線２４に電気的に接続さ
れる導ビアプラグ２７が形成されている。 A second-layer interlayer insulating film 25 is formed on the wiring 24, and a via hole 26 is formed in the interlayer insulating film 25. A conductive via plug 27 is formed in the via hole 26 and is electrically connected to the wiring 24 under the via hole 26.

図１には示していないが、層間絶縁膜２５上にはビアプラグ２７に電気的に接続される
第２層目の配線が形成される。層間絶縁膜２５は例えば層間絶縁膜２１と同一の絶縁材料
を使用して構成され、ビアプラグ２７は例えば導電性プラグ２３と同一積層構造において
同一の導電性材料を使用して構成される。また、第２層目の配線は第１層目の配線２４と
同一の導電性材料を使用して構成される。 Although not shown in FIG. 1, a second layer wiring electrically connected to the via plug 27 is formed on the interlayer insulating film 25. The interlayer insulating film 25 is configured using, for example, the same insulating material as the interlayer insulating film 21, and the via plug 27 is configured using, for example, the same conductive material in the same stacked structure as the conductive plug 23. The second layer wiring is configured using the same conductive material as the first layer wiring 24.

第２層目の配線上には複数層の層間絶縁膜と複数層の配線とが交互に積層される。第２
層目の配線の上方には第ｎ−１（ｎは４以上の整数。）層目の層間絶縁膜３０が形成され
、この層間絶縁膜３０にはビアホール３１が形成される。 A plurality of layers of interlayer insulating films and a plurality of layers of wiring are alternately stacked on the second layer wiring. Second
An n-1 (n is an integer greater than or equal to 4) layer interlayer insulating film 30 is formed above the wiring in the layer, and a via hole 31 is formed in the interlayer insulating film 30.

ビアホール３１内には、下層の第（ｎ−２）層目の配線（不図示）に電気的に接続され
るビアプラグ３２が埋設されている。 A via plug 32 that is electrically connected to a lower (n−2) -th layer wiring (not shown) is embedded in the via hole 31.

層間絶縁膜３０上にはビアプラグ３２に電気的に接続される第（ｎ−１）層目の配線３
５が形成される。層間絶縁膜３０は例えば層間絶縁膜２１と同一の絶縁材料を使用して構
成され、ビアプラグ３２は例えば導電性プラグ２３と同一積層構造において同一の導電性
材料を使用して構成される。また、第（ｎ−１）層目の配線３５は第１層目の配線２４と
同一の導電性材料を使用して構成される。 On the interlayer insulating film 30, the (n-1) th layer wiring 3 electrically connected to the via plug 32 is provided.
5 is formed. The interlayer insulating film 30 is configured using, for example, the same insulating material as that of the interlayer insulating film 21, and the via plug 32 is configured using, for example, the same conductive material in the same stacked structure as the conductive plug 23. The (n-1) -th layer wiring 35 is formed using the same conductive material as the first-layer wiring 24.

配線３５上には、最上層間絶縁膜となる第ｎ層目の層間絶縁膜３６が形成され、この層
間絶縁膜３６にはビアホール３７が形成される。ビアホール３７内には、配線３５に電気
的に接続される最上のビアプラグ３８が埋設される。 On the wiring 35, an nth interlayer insulating film 36 is formed as an uppermost interlayer insulating film, and a via hole 37 is formed in the interlayer insulating film 36. An uppermost via plug 38 electrically connected to the wiring 35 is embedded in the via hole 37.

層間絶縁膜３６上には、ビアプラグ３８に電気的に接続され最上配線層となる第ｎ層目
の配線として金属パッド（ボンディングパッド）４０が形成される。金属パッド４０を構
成する材料として、アルミニウム、又は、アルミニウムに例えばＣｕ、Ｓｉ若しくはＴｉ
の少なくとも１つの元素が添加されたアルミニウム合金が適用される。 On the interlayer insulating film 36, a metal pad (bonding pad) 40 is formed as an n-th layer wiring which is electrically connected to the via plug 38 and becomes the uppermost wiring layer. As a material constituting the metal pad 40, aluminum, or aluminum such as Cu, Si, or Ti is used.
An aluminum alloy to which at least one element is added is applied.

層間絶縁膜３６は、例えば層間絶縁膜２１と同一の絶縁材料を使用して構成され、最上
のビアプラグ３８は、例えば導電性プラグ２３と同一積層構造において同一の導電性材料
を使用して構成される。また、金属パッド４０は、例えば、配線２４と同一の導電性材料
を使用して構成される。 The interlayer insulating film 36 is configured using, for example, the same insulating material as the interlayer insulating film 21, and the uppermost via plug 38 is configured using, for example, the same conductive material in the same stacked structure as the conductive plug 23. The Further, the metal pad 40 is configured using, for example, the same conductive material as the wiring 24.

金属パッド４０上には、半導体基板１０の全域を覆い、金属パッド４０の中央部分に開
口（ボンディング開口）４３を有する絶縁膜４２が形成される。絶縁膜４２はカバー絶縁
膜としての機能を有し、例えば絶縁膜４２にはシリコン窒化膜が使用される。更に、絶縁
膜４２上には、半導体基板１０の全域を覆い、絶縁膜４２の開口４３に重複してそれより
も一回り大きな開口４５を有する保護膜４４が形成される。保護膜４４には例えば感光性
ポリイミド樹脂膜が使用される。 On the metal pad 40, an insulating film 42 that covers the entire area of the semiconductor substrate 10 and has an opening (bonding opening) 43 at the center of the metal pad 40 is formed. The insulating film 42 functions as a cover insulating film. For example, a silicon nitride film is used for the insulating film 42. Furthermore, a protective film 44 is formed on the insulating film 42 so as to cover the entire area of the semiconductor substrate 10 and overlap the opening 43 of the insulating film 42 and have an opening 45 that is slightly larger than that. For example, a photosensitive polyimide resin film is used for the protective film 44.

このような構造を有する第１実施形態に係る半導体装置１においては、絶縁膜４２の開
口４３内に露出する金属パッド４０の表面上に金属酸化膜４１が形成される。ここでは、
金属酸化膜４１には金属パッド４０の表面を酸化することにより酸化アルミニウム（Ａｌ
ｘＯｙ）膜が形成される。 In the semiconductor device 1 according to the first embodiment having such a structure, the metal oxide film 41 is formed on the surface of the metal pad 40 exposed in the opening 43 of the insulating film 42. here,
The metal oxide film 41 is formed by oxidizing the surface of the metal pad 40 to produce aluminum oxide (Al
x O y ) film is formed.

金属酸化膜４１は、後の製造方法において説明するダイシング工程に使用される冷却水
（純水）と金属パッド４０のアルミニウム粒子との反応を防止するシールド膜として機能
し、金属パッド４１の表面の腐食を防止する。 The metal oxide film 41 functions as a shield film that prevents a reaction between cooling water (pure water) used in a dicing process, which will be described later in the manufacturing method, and aluminum particles of the metal pad 40. Prevent corrosion.

本実施形態において、金属酸化膜４１は、アルミニウム粒子と純水との反応を防止する
ために、例えば厚さ約３ｎｍの自然酸化膜よりも厚く、かつ金属パッド４０とそれに電気
的に接続される金属物との間の接続抵抗値を不必要に増加させないために、例えば５ｎｍ
以上、１０ｎｍ以下の膜厚に設定される。 In the present embodiment, the metal oxide film 41 is thicker than a natural oxide film having a thickness of about 3 nm, for example, and is electrically connected to the metal pad 40 in order to prevent a reaction between aluminum particles and pure water. In order not to unnecessarily increase the connection resistance value between metal objects, for example, 5 nm.
The film thickness is set to 10 nm or less.

半導体装置１の金属パッド４０の表面には、図２に示すように、電気的接続物としてワ
イヤ５０の一端が電気的にかつ機械的に接続される。ワイヤ５０には例えば金（Ａｕ）ワ
イヤが使用され、このＡｕワイヤの一端は金属パッド４０にボンディングされる。 As shown in FIG. 2, one end of a wire 50 is electrically and mechanically connected to the surface of the metal pad 40 of the semiconductor device 1 as an electrical connection object. For example, a gold (Au) wire is used as the wire 50, and one end of the Au wire is bonded to the metal pad 40.

次に、前述の半導体装置１の製造方法を簡単に説明する。   Next, a method for manufacturing the semiconductor device 1 will be briefly described.

まず、図３に示すように、半導体基板１０にトランジスタＴを形成した後に、絶縁膜２
０、第１層目の層間絶縁膜２１、コンタクトホール２２、導電性プラグ２３、第１層目の
配線２４のそれぞれを順次形成する。引き続き、配線２４上に第２層目の層間絶縁膜２５
、ビアホール２６、導電性プラグ２７、第２層目の配線のそれぞれを順次形成し、層間絶
縁膜と配線とを交互に複数層形成する。ここで、半導体基板１０は、ダイシング工程前で
あって、半導体ウェーハの状態にある。 First, as shown in FIG. 3, after forming the transistor T on the semiconductor substrate 10, the insulating film 2
0, first-layer interlayer insulating film 21, contact hole 22, conductive plug 23, and first-layer wiring 24 are sequentially formed. Subsequently, the second interlayer insulating film 25 is formed on the wiring 24.
The via hole 26, the conductive plug 27, and the second layer wiring are sequentially formed, and a plurality of layers of interlayer insulating films and wirings are alternately formed. Here, the semiconductor substrate 10 is in a state of a semiconductor wafer before the dicing process.

そして、第ｎ層目の層間絶縁膜３６上に金属パッド４０を形成する。金属パッド４０に
は、例えばスパッタリング法を使用して形成された厚さ約７７０ｎｍ〜９５０ｎｍのアル
ミニウム合金膜を使用する。 Then, a metal pad 40 is formed on the n-th interlayer insulating film 36. For the metal pad 40, for example, an aluminum alloy film having a thickness of about 770 nm to 950 nm formed using a sputtering method is used.

次に、金属パッド４０上を覆う絶縁膜４２を形成する。この後、絶縁膜４２に金属パッ
ド４０の表面中央部が露出する開口４３を形成する。開口４３は、レジストマスク（不図
示）を使用し、絶縁膜４２にドライエッチングを行うことにより形成される。 Next, an insulating film 42 that covers the metal pad 40 is formed. Thereafter, an opening 43 is formed in the insulating film 42 so that the central portion of the surface of the metal pad 40 is exposed. The opening 43 is formed by performing dry etching on the insulating film 42 using a resist mask (not shown).

さらに、図４に示すように、絶縁膜４２上及び開口４３から露出された金属パッド４０
上を覆う保護膜４４を形成し、開口４３及び金属パッド４０の表面を露出させる開口４５
を保護膜４４に形成する。保護膜４４として、例えば塗布法を使用して成膜された感光性
樹脂、例えば感光性ポリイミド膜を使用する。開口４５は、フォトリソグラフィ技術を使
用して保護膜４４にパターンニングを行うことにより形成する。 Further, as shown in FIG. 4, the metal pad 40 exposed on the insulating film 42 and from the opening 43.
A protective film 44 is formed to cover the top, and the opening 43 and the opening 45 exposing the surface of the metal pad 40 are formed.
Is formed on the protective film 44. As the protective film 44, for example, a photosensitive resin formed using a coating method, for example, a photosensitive polyimide film is used. The opening 45 is formed by patterning the protective film 44 using a photolithography technique.

前述の図１に示したように、酸素含有雰囲気内において、金属パッド４０の開口４３か
ら露出する表面に熱酸化法を使用して金属酸化膜４１を形成する。金属酸化膜４１は、図
５に示すように、以下の熱酸化条件に基づき形成される。 As shown in FIG. 1, the metal oxide film 41 is formed on the surface exposed from the opening 43 of the metal pad 40 in the oxygen-containing atmosphere by using a thermal oxidation method. As shown in FIG. 5, the metal oxide film 41 is formed based on the following thermal oxidation conditions.

まず、酸素濃度１８％のガスを２０ｍｌ／ｍｉｎ、Ｎ2ガスを１０ｌ／ｍｉｎ程度で酸
素含有雰囲気内に供給する。その酸素含有雰囲気は、排気によって常圧よりも低い圧力に
設定される。そして、約１時間をかけて２℃／ｍｉｎ〜３℃／ｍｉｎの上昇率で２００℃
まで加熱する。この２００℃の状態を１２時間持続し、１．５℃／ｍｉｎ〜１．８℃／ｍ
ｉｎの下降率で加熱前の温度まで冷却する。 First, a gas with an oxygen concentration of 18% is supplied into an oxygen-containing atmosphere at a rate of 20 ml / min and N 2 gas at a rate of about 10 l / min. The oxygen-containing atmosphere is set to a pressure lower than normal pressure by exhaust. And it takes about 1 hour and increases at a rate of 2 ° C./min to 3 ° C./min to 200 ° C.
Until heated. This state of 200 ° C. is maintained for 12 hours, 1.5 ° C./min to 1.8 ° C./m.
Cool down to the temperature before heating at the in descending rate.

このような熱酸化条件下において、金属パッド４０のうち開口４３から露出した表面に
は、金属酸化膜（酸化アルミニウム膜）４１が約５ｎｍ〜１９ｎｍの膜厚に形成される。 Under such thermal oxidation conditions, a metal oxide film (aluminum oxide film) 41 is formed to a thickness of about 5 nm to 19 nm on the surface of the metal pad 40 exposed from the opening 43.

この後、図示しないが、プローブテスタを使用して動作試験を行い、半導体基板１０の
裏面のバックグラインド処理を行う。そして、半導体基板１０にダイシングを行い、半導
体基板１０を分割して、チップ状の複数の半導体装置１を形成する。ダイシングにおいて
は、冷却のために純水の冷却水を半導体基板１０に供給する。なお、純水に二酸化炭素、
その他の成分を混入させてもよい。 Thereafter, although not shown, an operation test is performed using a probe tester, and a back grinding process is performed on the back surface of the semiconductor substrate 10. Then, dicing is performed on the semiconductor substrate 10, and the semiconductor substrate 10 is divided to form a plurality of chip-shaped semiconductor devices 1. In dicing, pure water is supplied to the semiconductor substrate 10 for cooling. Carbon dioxide in pure water,
Other components may be mixed.

以上のように製造された半導体装置１の金属パッド４０の表面に、図２に示すように、
金属酸化膜４１を介してワイヤ５０をボンディングにより接続すると、ワイヤ５０は金属
酸化膜４１を消失させながら金属パッド４０に接続される。ボンディングは、超音波振動
を併用した熱圧着により行う。 On the surface of the metal pad 40 of the semiconductor device 1 manufactured as described above, as shown in FIG.
When the wire 50 is connected through the metal oxide film 41 by bonding, the wire 50 is connected to the metal pad 40 while the metal oxide film 41 disappears. Bonding is performed by thermocompression bonding using ultrasonic vibration.

図６（ａ）は、半導体ウェーハをダイシングする前において、金属パッド４０の表面を
金属顕微鏡を用いて撮影した写真に基づく模写図である。図６（ｂ）は、酸素含有雰囲気
中で金属パッド４０を熱処理しなかった金属パッド４０の表面を、ダイシング工程後に金
属顕微鏡を通して撮影した写真の模写図である。 FIG. 6A is a copying diagram based on a photograph of the surface of the metal pad 40 taken using a metal microscope before dicing the semiconductor wafer. FIG. 6B is a copy of a photograph of the surface of the metal pad 40 that was not heat-treated in an oxygen-containing atmosphere taken through a metal microscope after the dicing process.

ダイシング前においては、図６（ａ）に示すように、金属パッド４０の表面に腐食によ
って発生する空孔４０ｃは存在していない。これに対して、ダイシング後には、図６（ｂ
）に示すように、酸素雰囲気中で熱処理を施さない金属パッド４０の表面には、腐食によ
って発生する空孔４０ｃが存在する。 Before dicing, as shown in FIG. 6A, there is no hole 40c generated by corrosion on the surface of the metal pad 40. On the other hand, after dicing, FIG.
As shown in FIG. 5B, there are holes 40c generated by corrosion on the surface of the metal pad 40 that is not heat-treated in an oxygen atmosphere.

これに対して、本実施形態のように、半導体ウェーハをダイシングする前に金属パッド
４０の表面を酸素雰囲気中で加熱すると、半導体ウェーハをダイシングした後にも金属パ
ッド４０の表面は図６（ａ）に示す状態を保持した。 On the other hand, when the surface of the metal pad 40 is heated in an oxygen atmosphere before dicing the semiconductor wafer as in the present embodiment, the surface of the metal pad 40 after the dicing of the semiconductor wafer is as shown in FIG. The state shown in FIG.

図７は、本実施形態に係る熱酸化処理の有無と腐食の有無との関係を調べた結果を示す
表である。ここで、サンプルには８インチ半導体ウェーハ（半導体基板１０）が使用され
た。 FIG. 7 is a table showing the results of examining the relationship between the presence or absence of thermal oxidation treatment and the presence or absence of corrosion according to the present embodiment. Here, an 8-inch semiconductor wafer (semiconductor substrate 10) was used as a sample.

図７に示すように、サンプル１は、酸素雰囲気中での熱処理を実施しなかった、つまり
金属パッド４０の表面に金属酸化膜４１を積極的に形成していない半導体ウェーハである
。この半導体ウェーハにダイシングを行い、１つの金属パッド４０の表面を金属顕微鏡を
使用して観察すると、腐食の発生を確認することができ、１つの金属パッド４０の表面の
腐食個数は平均で１２個であった。 As shown in FIG. 7, Sample 1 is a semiconductor wafer that has not been heat-treated in an oxygen atmosphere, that is, the metal oxide film 41 is not actively formed on the surface of the metal pad 40. When this semiconductor wafer is diced and the surface of one metal pad 40 is observed using a metal microscope, the occurrence of corrosion can be confirmed, and the number of corrosion on the surface of one metal pad 40 is 12 on average. Met.

サンプル２は、基板温度２００℃において１０分間の熱酸化処理を実施した半導体ウェ
ーハである。この場合、熱酸化処理としては十分ではなく、金属パッド４０の表面に十分
な膜厚の金属酸化膜４１が生成されていないと推察される。従って、観察結果からも、腐
食の発生を確認することができ、１つの金属パッド４０の表面の腐食個数は平均で１１個
であった。 Sample 2 is a semiconductor wafer that has been subjected to a thermal oxidation treatment at a substrate temperature of 200 ° C. for 10 minutes. In this case, it is presumed that the metal oxide film 41 having a sufficient film thickness is not formed on the surface of the metal pad 40 because the thermal oxidation treatment is not sufficient. Therefore, the occurrence of corrosion can also be confirmed from the observation results, and the number of corrosions on the surface of one metal pad 40 was 11 on average.

サンプル３は、基板温度２００℃において８時間の熱酸化処理を実施した半導体ウェー
ハである。この場合でも、熱酸化処理としてはまだ不十分であり、金属パッド４０の表面
に十分な膜厚の金属酸化膜４１が生成されていないと推察される。従って、観察結果から
も、腐食の発生を確認することができ、腐食個数を減少することができるものの、１つの
金属パッド４０の表面の腐食個数は平均で３個であった。 Sample 3 is a semiconductor wafer that has been subjected to a thermal oxidation treatment at a substrate temperature of 200 ° C. for 8 hours. Even in this case, the thermal oxidation treatment is still insufficient, and it is assumed that the metal oxide film 41 having a sufficient thickness is not formed on the surface of the metal pad 40. Therefore, although the occurrence of corrosion can be confirmed from the observation result and the number of corrosion can be reduced, the number of corrosion on the surface of one metal pad 40 is 3 on average.

これに対して、サンプル４は、基板温度２００℃において１２時間の熱酸化処理を実施
した半導体ウェーハである。この場合、熱酸化処理としては十分であり、金属パッド４０
の表面に十分な膜厚の金属酸化膜４１が生成されていると推察される。観察結果からも明
らかなように、腐食の発生を確認することができず、１つの金属パッド４０の表面の腐食
個数は平均で０個であった。 On the other hand, Sample 4 is a semiconductor wafer that has been subjected to thermal oxidation treatment for 12 hours at a substrate temperature of 200 ° C. In this case, the thermal oxidation treatment is sufficient, and the metal pad 40
It is inferred that a metal oxide film 41 having a sufficient thickness is generated on the surface of the film. As is apparent from the observation results, the occurrence of corrosion could not be confirmed, and the number of corrosion on the surface of one metal pad 40 was 0 on average.

同様に、サンプル５、６，７においても、腐食の発生を確認することができず、１つの
金属パッド４０の表面の腐食個数は平均で０個であった。サンプル５は、基板温度２００
℃において１６時間の熱酸化処理を実施した半導体ウェーハである。サンプル６は、基板
温度２００℃において２０時間の熱酸化処理を実施した半導体ウェーハである。サンプル
７は、基板温度２００℃において２４時間の熱酸化処理を実施した半導体ウェーハである
。 Similarly, in Samples 5, 6, and 7, the occurrence of corrosion could not be confirmed, and the number of corrosion on the surface of one metal pad 40 was 0 on average. Sample 5 has a substrate temperature of 200
This is a semiconductor wafer subjected to a thermal oxidation treatment at 16 ° C. for 16 hours. Sample 6 is a semiconductor wafer that has been subjected to a thermal oxidation treatment at a substrate temperature of 200 ° C. for 20 hours. Sample 7 is a semiconductor wafer subjected to a thermal oxidation treatment for 24 hours at a substrate temperature of 200 ° C.

なお、サンプル８に関しては、第２実施形態において説明する。   The sample 8 will be described in the second embodiment.

図８は、第１実施形態に係る熱酸化処理の有無（腐食の有無）とシェア強度との関係を
調べた結果を示すグラフである。シェア強度とは、金属パッド４０の表面とワイヤ５０の
ボールとのボンディング部分の剪断応力に対する強度である。 FIG. 8 is a graph showing the results of examining the relationship between the presence / absence of thermal oxidation treatment (presence / absence of corrosion) and the shear strength according to the first embodiment. The shear strength is a strength against a shear stress at a bonding portion between the surface of the metal pad 40 and the ball of the wire 50.

図８において、サンプル９は、ダイシング前の金属パット４０の表面に腐食が無いサン
プルである。また、サンプル１は、ダイシング後に金属パッド４９に腐食が存在するサン
プルである。サンプル５は、酸素含有雰囲気で基板温度２００℃において１６時間の熱処
理を行った金属パッド４０であって、ダイシング後の本実施形態に係るサンプルである。
そして、サンプル９、１、５のそれぞれについてシェア強度の最小値、平均値並びに最大
値を調べた。 In FIG. 8, a sample 9 is a sample in which the surface of the metal pad 40 before dicing has no corrosion. Sample 1 is a sample in which corrosion occurs on the metal pad 49 after dicing. Sample 5 is a metal pad 40 that has been heat-treated for 16 hours at a substrate temperature of 200 ° C. in an oxygen-containing atmosphere, and is a sample according to this embodiment after dicing.
Then, the minimum value, average value, and maximum value of the shear strength were examined for each of Samples 9, 1, and 5.

図８に示すように、サンプル５においては、シェア強度の最小値、平均値並びに最大値
がいずれもサンプル１のそれらの値に対して高くなる。更に、サンプル５のシェア強度は
サンプル９のシェア強度に対しても高くなるという結果が得られた。 As shown in FIG. 8, in sample 5, the minimum value, average value, and maximum value of the shear strength are all higher than those in sample 1. Furthermore, the result that the shear strength of sample 5 was higher than that of sample 9 was obtained.

サンプル５においては、金属パット４０の表面に金属酸化膜４１を形成し、ダイシング
に使用される冷却水と金属パッド４０の表面との反応を金属酸化膜４１によって防止して
いるので、金属パット４０の表面に腐食により生成される空孔４０ｃが存在しない。つま
り、金属パッド４０の表面のボンディング面積は空孔４０ｃによって減少することがない
ので、金属パッド４０の表面とワイヤ５０との接合部分に金属パッド４０側からのアルミ
ニウム粒子の供給が十分に行われ、接合部分の合金化が促進され、シェア強度を向上する
ことができる。 In the sample 5, the metal oxide film 41 is formed on the surface of the metal pad 40, and the reaction between the cooling water used for dicing and the surface of the metal pad 40 is prevented by the metal oxide film 41. There are no holes 40c generated by corrosion on the surface. In other words, since the bonding area on the surface of the metal pad 40 is not reduced by the holes 40c, aluminum particles are sufficiently supplied from the metal pad 40 side to the joint portion between the surface of the metal pad 40 and the wire 50. The alloying of the joint portion is promoted, and the shear strength can be improved.

図９は、本実施形態に係る熱酸化処理の有無（腐食の有無）とワイヤプル強度との関係
を調べた結果を示すグラフである。ワイヤプル強度とは、金属パッド４０の表面とワイヤ
５０のボールとのボンディング部分の引張応力に対する強度である。シェア強度と同様に
、サンプル９、サンプル１及びサンプル５について、それぞれワイヤプル強度の最小値、
平均値並びに最大値を調べた。なお、それらの強度試験において加える力は６ｐｋｇとし
た。 FIG. 9 is a graph showing the results of examining the relationship between the presence / absence of thermal oxidation treatment (presence / absence of corrosion) and wire pull strength according to the present embodiment. The wire pull strength is the strength against tensile stress at the bonding portion between the surface of the metal pad 40 and the ball of the wire 50. Similar to the shear strength, for sample 9, sample 1 and sample 5, the minimum value of wire pull strength,
The average value and the maximum value were examined. Note that the force applied in these strength tests was 6 kg.

図９に示すように、サンプル５においては、ワイヤプル強度の最小値、平均値並びに最
大値がいずれもサンプル１のそれらの値に対して高くなる。 As shown in FIG. 9, in sample 5, the minimum value, average value, and maximum value of wire pull strength are all higher than those in sample 1.

サンプル５においては、前述のシェア強度において説明したように、金属パット４０の
表面とワイヤ５０との接合部分の合金化が促進され、ワイヤプル強度を向上することがで
きる。 In the sample 5, as described in the above-described shear strength, alloying of the joint portion between the surface of the metal pad 40 and the wire 50 is promoted, and the wire pull strength can be improved.

本実施形態に係る半導体装置１の製造方法は、保護膜４４、開口４５を形成した後、金
属パッド４０の表面に金属酸化膜４１を形成し、そしてプローブテスタを使用して動作試
験を行っている。 In the method for manufacturing the semiconductor device 1 according to this embodiment, after forming the protective film 44 and the opening 45, the metal oxide film 41 is formed on the surface of the metal pad 40, and an operation test is performed using a probe tester. Yes.

これに対して、半導体装置１の製造方法の変形例においては、プローブテスタを使用し
て動作試験を行った後に、金属パッド４０の表面に金属酸化膜４１を形成する。金属酸化
膜４１を形成した後は、バックグラインド処理、ダイシングのそれぞれを順次行う。 On the other hand, in a modification of the method for manufacturing the semiconductor device 1, the metal oxide film 41 is formed on the surface of the metal pad 40 after performing an operation test using a probe tester. After the metal oxide film 41 is formed, back grinding and dicing are sequentially performed.

金属酸化膜４１を形成する熱酸化条件は、基板温度２００℃において少なくとも１６時
間又は１６時間以上の処理時間に設定する。つまり、図７に示すサンプル５乃至８を含む
熱処理条件を適用する。 The thermal oxidation condition for forming the metal oxide film 41 is set to a processing time of at least 16 hours or 16 hours or more at a substrate temperature of 200 ° C. That is, the heat treatment conditions including the samples 5 to 8 shown in FIG. 7 are applied.

本実施形態に係る半導体装置１の製造方法においては、酸素含有雰囲気内において熱処
理を行い、金属パッド４０の表面に金属酸化膜４１を形成し、この後に半導体ウェーハの
ダイシングを行ったので、金属パッド４０の表面のダイシングに起因する腐食を防止する
ことができ、金属パッド４０の表面とその表面に接続されるワイヤ５０との密着性を改善
することができる。従って、半導体装置１の製造上の歩留まりを向上することができる。 In the manufacturing method of the semiconductor device 1 according to the present embodiment, the heat treatment is performed in an oxygen-containing atmosphere, the metal oxide film 41 is formed on the surface of the metal pad 40, and then the semiconductor wafer is diced. Corrosion caused by dicing on the surface of the metal 40 can be prevented, and adhesion between the surface of the metal pad 40 and the wire 50 connected to the surface can be improved. Therefore, the manufacturing yield of the semiconductor device 1 can be improved.

（第２実施形態）
本発明の第２実施形態は、第１実施形態に係る半導体装置１の製造方法において、金属
酸化膜４１の形成工程並びに熱酸化条件を代えた例を説明するものである。 (Second Embodiment)
The second embodiment of the present invention describes an example in which the process of forming the metal oxide film 41 and the thermal oxidation conditions are changed in the method for manufacturing the semiconductor device 1 according to the first embodiment.

第２実施形態に係る半導体装置１の製造方法は、前述の第１実施形態に係る半導体装置
１の製造方法の図４に示す保護膜４４に開口４５を形成した後に、この保護膜４４のアニ
ールを利用して、開口４５から露出する金属パッド４０の表面に金属酸化膜４１を形成す
る。 In the method for manufacturing the semiconductor device 1 according to the second embodiment, after forming the opening 45 in the protective film 44 shown in FIG. 4 of the method for manufacturing the semiconductor device 1 according to the first embodiment, annealing of the protective film 44 is performed. Then, a metal oxide film 41 is formed on the surface of the metal pad 40 exposed from the opening 45.

図１０に示すように、金属酸化膜４１は以下の熱酸化条件に基づき形成される。
１０ｍｌのＨ2Ｏと３０ｌ／ｍｉｎのＮ2を供給して常圧に設定された酸素含有雰囲気内
に半導体基板１を設置する。 As shown in FIG. 10, the metal oxide film 41 is formed based on the following thermal oxidation conditions.
10 ml of H 2 O and 30 l / min of N 2 are supplied, and the semiconductor substrate 1 is placed in an oxygen-containing atmosphere set to normal pressure.

そして、基板温度２００℃の予備加熱を数十分程度行った後、約３０分〜４０分をかけ
て５℃／ｍｉｎ〜６℃／ｍｉｎの上昇率で基板温度を３８０℃まで上げる。その後に、数
分間、例えば２分間の酸素濃度の監視を行い、酸素濃度を例えば２０ｐｐｍ以下で０ｐｐ
ｍより多くなるように調節した後に、温度３８０℃の状態を５０分〜７０分以上、好まし
くは６０分以上持続する。 Then, after preheating at a substrate temperature of 200 ° C. for about several tens of minutes, the substrate temperature is increased to 380 ° C. at a rate of increase of 5 ° C./min to 6 ° C./min over about 30 to 40 minutes. After that, the oxygen concentration is monitored for several minutes, for example, 2 minutes, and the oxygen concentration is 0 pp at 20 ppm or less.
After adjusting to be greater than m, the state at a temperature of 380 ° C. is maintained for 50 minutes to 70 minutes or more, preferably 60 minutes or more.

これにより、金属パッド４０の表面に金属酸化膜４１が形成されるとともに、保護膜４
４にアニールを行う。この後、約３０分〜４０分の時間をかけて４℃／ｍｉｎ〜６℃／ｍ
ｉｎの下降率で冷却する。このような熱酸化条件下において、金属酸化膜（酸化アルミニ
ウム膜）４１は約５ｎｍ〜１０ｎｍの膜厚に形成される。 As a result, a metal oxide film 41 is formed on the surface of the metal pad 40 and the protective film 4
4 is annealed. After this, 4 ° C / min to 6 ° C / m over a period of about 30 minutes to 40 minutes.
Cool at the rate of decrease of in. Under such thermal oxidation conditions, the metal oxide film (aluminum oxide film) 41 is formed to a thickness of about 5 nm to 10 nm.

図７に示したサンプル８は、第２実施形態に係る製造方法により形成された半導体ウェ
ーハであり、サンプル８においては、腐食の発生を確認することができず、１つの金属パ
ッド４０の表面の腐食個数は平均で０個であった。 The sample 8 shown in FIG. 7 is a semiconductor wafer formed by the manufacturing method according to the second embodiment. In the sample 8, the occurrence of corrosion cannot be confirmed, and the surface of one metal pad 40 is not observed. The average number of corrosion was 0.

金属パッド４０の表面に金属酸化膜４１を形成した後には、バックグラインド処理工程
、ダイシング工程のそれぞれが順次行われる。そして、金属パッド４０の表面にワイヤ５
０をボンディングにより接続する。 After the metal oxide film 41 is formed on the surface of the metal pad 40, the back grinding process and the dicing process are sequentially performed. Then, the wire 5
0 is connected by bonding.

第２実施形態に係る半導体装置１の製造方法においては、第１実施形態に係る半導体装
置１の製造方法と同様に、酸素含有雰囲気内において熱処理を行い、金属パッド４０の表
面に金属酸化膜４１を形成し、この後に半導体ウェーハのダイシングを行った。 In the manufacturing method of the semiconductor device 1 according to the second embodiment, similarly to the manufacturing method of the semiconductor device 1 according to the first embodiment, heat treatment is performed in an oxygen-containing atmosphere, and the metal oxide film 41 is formed on the surface of the metal pad 40. After that, the semiconductor wafer was diced.

これより、金属パッド４０の表面のダイシングに起因する腐食を防止することができ、
金属パッド４０の表面とその表面に接続されるワイヤ５０との密着性を改善することがで
きる。従って、半導体装置１の製造上の歩留まりを向上することができる。 Thus, corrosion caused by dicing on the surface of the metal pad 40 can be prevented,
The adhesion between the surface of the metal pad 40 and the wire 50 connected to the surface can be improved. Therefore, the manufacturing yield of the semiconductor device 1 can be improved.

更に、第２実施形態に係る半導体装置１の製造方法においては、金属酸化膜１１を形成
する工程と保護膜４４を加熱する工程とを重複させて行っているので、製造時間を短縮す
ることができる。 Furthermore, in the method for manufacturing the semiconductor device 1 according to the second embodiment, the process of forming the metal oxide film 11 and the process of heating the protective film 44 are performed in an overlapping manner, so that the manufacturing time can be shortened. it can.

更に、第２実施形態に係る半導体装置１の製造方法においては、基板温度を２００℃か
ら３８０℃まで高めて金属酸化膜１１を形成しているので、短時間において金属酸化膜１
１を形成することができ、製造時間を短縮することができる。その加熱時間は少なくとも
６０分又は６０分以上とすることが好ましい。 Furthermore, in the method for manufacturing the semiconductor device 1 according to the second embodiment, since the metal oxide film 11 is formed by increasing the substrate temperature from 200 ° C. to 380 ° C., the metal oxide film 1 is formed in a short time.
1 can be formed, and the manufacturing time can be shortened. The heating time is preferably at least 60 minutes or 60 minutes or longer.

第２実施形態に係る半導体装置１の製造方法は、金属パッド４０の表面に金属酸化膜４
１を形成する工程と保護膜４４を加熱する工程とを重複させるとともに、基板温度を３８
０℃の高温度に設定している。 In the method for manufacturing the semiconductor device 1 according to the second embodiment, the metal oxide film 4 is formed on the surface of the metal pad 40.
1 and the step of heating the protective film 44 are overlapped, and the substrate temperature is set to 38.
It is set to a high temperature of 0 ° C.

これに対して、半導体装置１の製造方法の変形例においては、金属パッド４０の表面に
金属酸化膜４１を形成する工程と保護膜４４を加熱する工程とを重複させるとともに、基
板温度を２００℃に設定し、この状態を１２時間又はそれ以上持続させてもよい。 On the other hand, in the modification of the manufacturing method of the semiconductor device 1, the step of forming the metal oxide film 41 on the surface of the metal pad 40 and the step of heating the protective film 44 are overlapped, and the substrate temperature is set to 200 ° C. And this state may last for 12 hours or longer.

（その他の実施形態）
上記のように、本発明を第１実施形態及び第２実施形態によって記載したが、この開示
の一部をなす論述及び図面はこの発明を限定するものでない。本発明は様々な代替実施形
態、実施例及び運用技術に適用することができる。例えば、前述の実施形態等においては
、半導体装置１に搭載されたトランジスタＴはＩＧＦＥＴであるが、本発明は、トランジ
スタＴとしてバイポーラトランジスタ等の能動素子を使用してもよい。また、本発明は、
トランジスタＴとともに若しくはトランジスタＴに代えて、抵抗、容量等の受動素子を搭
載してもよい。 (Other embodiments)
As described above, the present invention has been described by the first embodiment and the second embodiment. However, the description and the drawings constituting a part of this disclosure do not limit the present invention. The present invention can be applied to various alternative embodiments, examples and operational technologies. For example, in the above-described embodiment and the like, the transistor T mounted on the semiconductor device 1 is an IGFET. However, in the present invention, an active element such as a bipolar transistor may be used as the transistor T. The present invention also provides:
A passive element such as a resistor or a capacitor may be mounted together with or in place of the transistor T.

次に、本発明の実施形態をさらに付記する。
（付記１）
半導体基板の上方の絶縁膜上にアルミニウム、アルミニウム合金のいずれかを有する金
属パッドを形成する工程と、
酸素含有雰囲気内において熱処理を行い、前記金属パッドの表面に金属酸化膜を形成す
る工程と、
前記半導体基板を分割してチップを形成する工程と、
を有することを特徴とする半導体装置の製造方法。
（付記２）
前記金属酸化膜は酸化アルミニウム膜であることを特徴とする付記１に記載の半導体装
置の製造方法。
（付記３）
前記金属パッドを形成する工程の後に、前記金属パッドの中央部を露出しその周囲を覆
うカバー絶縁膜を形成する工程と、
前記金属パッドの前記中央部の表面に前記金属酸化膜を形成する工程と、
を有することを特徴とする付記１又は付記２に記載の半導体装置の製造方法。
（付記４）
前記金属酸化膜を形成する前に、前記金属パッド及び前記カバー絶縁膜の上に保護膜を
形成する工程と、
前記金属パッドの前記中央部を露出する開口を形成する工程と、
を有することを特徴とする付記３に記載の半導体装置の製造方法。
（付記５）
前記金属酸化膜は、前記酸素含有雰囲気内において、基板温度２００℃を維持し、１２
時間以上の時間の前記熱処理により形成されることを特徴とする付記１乃至付記４のいず
れか１つに記載の半導体装置の製造方法。
（付記６）
前記金属酸化膜は、前記酸素含有雰囲気内において、基板温度３８０℃を維持し、６０
分以上の時間の前記熱処理により形成されることを特徴とする付記１乃至付記４のいずれ
か１つに記載の半導体装置の製造方法。
（付記７）
前記酸素含有雰囲気中で、前記酸素雰囲気の温度を上昇して前記金属パッドの中央部の
表面に前記金属酸化膜を形成するとともに前記保護膜を加熱することを特徴とする付記４
に記載の半導体装置の製造方法。
（付記８）
前記金属酸化膜を形成する工程は、前記金属パッドの表面に生成される自然酸化膜の膜
厚に比べて厚い膜厚を有する前記金属酸化膜を形成する工程であることを特徴とする付記
１乃至付記７のいずれかつ項に記載の半導体装置の製造方法。
（付記９）
前記金属パッドの表面に前記金属酸化膜を介してワイヤのボンディングを行う工程を更
に備えたことを特徴とする付記１乃至付記８のいずれか１つに記載の半導体装置の製造方
法。
（付記１０）
前記半導体基板の分割は、水を共有しながら前記半導体基板を切断することを特徴とす
る付記１乃至付記９のいずれか１つに半導体装置の製造方法。 Next, embodiments of the present invention will be further described.
(Appendix 1)
Forming a metal pad having either aluminum or an aluminum alloy on the insulating film above the semiconductor substrate;
Performing a heat treatment in an oxygen-containing atmosphere to form a metal oxide film on the surface of the metal pad;
Dividing the semiconductor substrate to form a chip;
A method for manufacturing a semiconductor device, comprising:
(Appendix 2)
2. The method of manufacturing a semiconductor device according to appendix 1, wherein the metal oxide film is an aluminum oxide film.
(Appendix 3)
After the step of forming the metal pad, a step of forming a cover insulating film that exposes a central portion of the metal pad and covers the periphery thereof;
Forming the metal oxide film on the surface of the central portion of the metal pad;
The method for manufacturing a semiconductor device according to appendix 1 or appendix 2, characterized by comprising:
(Appendix 4)
Forming a protective film on the metal pad and the cover insulating film before forming the metal oxide film;
Forming an opening exposing the central portion of the metal pad;
The method for manufacturing a semiconductor device according to appendix 3, wherein:
(Appendix 5)
The metal oxide film maintains a substrate temperature of 200 ° C. in the oxygen-containing atmosphere.
5. The method of manufacturing a semiconductor device according to any one of appendices 1 to 4, wherein the semiconductor device is formed by the heat treatment for a time longer than or equal to a time.
(Appendix 6)
The metal oxide film maintains a substrate temperature of 380 ° C. in the oxygen-containing atmosphere.
The method of manufacturing a semiconductor device according to any one of appendix 1 to appendix 4, wherein the semiconductor device is formed by the heat treatment for a time of at least minutes.
(Appendix 7)
The temperature of the oxygen atmosphere is increased in the oxygen-containing atmosphere to form the metal oxide film on the surface of the central portion of the metal pad and to heat the protective film.
The manufacturing method of the semiconductor device as described in any one of Claims 1-3.
(Appendix 8)
The step of forming the metal oxide film is a step of forming the metal oxide film having a thickness larger than that of a natural oxide film generated on the surface of the metal pad. The manufacturing method of the semiconductor device according to any one of Items 7 to 7.
(Appendix 9)
9. The method of manufacturing a semiconductor device according to any one of appendices 1 to 8, further comprising a step of bonding a wire to the surface of the metal pad via the metal oxide film.
(Appendix 10)
The method of manufacturing a semiconductor device according to any one of appendix 1 to appendix 9, wherein the semiconductor substrate is divided by cutting the semiconductor substrate while sharing water.

図１は、本発明の第１実施形態に係る半導体装置の要部断面図である。FIG. 1 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment of the present invention. 図２は、第１実施形態に係る半導体装置のワイヤが接続された状態の要部断面図である。FIG. 2 is a cross-sectional view of a main part in a state where wires of the semiconductor device according to the first embodiment are connected. 図３は、第１実施形態に係る半導体装置の製造方法を説明する第１の工程断面図である。FIG. 3 is a first process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. 図４は、第２の工程断面図である。FIG. 4 is a second process cross-sectional view. 図５は、第１実施形態に係る半導体装置の製造方法において金属酸化膜を形成する熱酸化プロファイルを示す図である。FIG. 5 is a diagram showing a thermal oxidation profile for forming a metal oxide film in the method for manufacturing a semiconductor device according to the first embodiment. 図６（ａ）は、第１実施形態においてダイシング工程前の金属パッドの表面状態を示す模写図であり、図６（ｂ）は、ダイシング工程後の金属パッドの表面状態を示す模写図である。6A is a copy diagram showing the surface state of the metal pad before the dicing process in the first embodiment, and FIG. 6B is a copy view showing the surface state of the metal pad after the dicing process. . 図７は、第１実施形態において熱酸化処理の有無と金属パッドの表面の腐食の有無との関係を示す表である。FIG. 7 is a table showing the relationship between the presence or absence of thermal oxidation treatment and the presence or absence of corrosion on the surface of the metal pad in the first embodiment. 図８は、第１実施形態において金属パッドとワイヤとの接続部分のシェア強度を示すグラフである。FIG. 8 is a graph showing the shear strength of the connection portion between the metal pad and the wire in the first embodiment. 図９は、第１実施形態において金属パッドとワイヤとの接続部分のワイヤプル強度を示すグラフである。FIG. 9 is a graph showing the wire pull strength of the connection portion between the metal pad and the wire in the first embodiment. 図１０は、本発明の第２実施形態に係る半導体装置の製造方法において金属酸化膜を形成する熱酸化プロファイルを示す図である。FIG. 10 is a diagram showing a thermal oxidation profile for forming a metal oxide film in the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

符号の説明Explanation of symbols

１ 半導体装置
１０ 半導体基板
２１、２５、３０、３６ 層間絶縁膜
２３、２６、３２、３８ 導電性プラグ
２４、３５ 配線
４０ 金属パッド
４１ 金属酸化膜
４２ 絶縁膜
４３、４５ 開口
４４ 保護膜
５０ ワイヤ
Ｔ トランジスタ DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Semiconductor substrate 21, 25, 30, 36 Interlayer insulating film 23, 26, 32, 38 Conductive plug 24, 35 Wiring 40 Metal pad 41 Metal oxide film 42 Insulating film 43, 45 Opening 44 Protective film 50 Wire T Transistor

Claims (5)

半導体基板の上方の絶縁膜上にアルミニウム、アルミニウム合金のいずれかを有する金属パッドを形成する工程と、
酸素含有雰囲気内における熱処理により前記金属パッドの表面に金属酸化膜を形成する工程と、
前記金属酸化膜を形成した後に、水を供給しながら前記半導体基板を切断することにより分割してチップを形成する工程と、
超音波振動を併用する熱圧着により、前記金属酸化膜を消滅させながらワイヤの一端を前記チップ上の前記金属パッドにボンディングする工程と、
を有することを特徴とする半導体装置の製造方法。 Forming a metal pad having either aluminum or an aluminum alloy on the insulating film above the semiconductor substrate;
Forming a metal oxide film by contact Keru heat treatment in an oxygen-containing atmosphere on the surface of the metal pad,
Forming a chip the after forming a metal oxide film, is divided by cutting the semiconductor substrate while supplying water,
Bonding one end of the wire to the metal pad on the chip while eliminating the metal oxide film by thermocompression bonding using ultrasonic vibration;
A method for manufacturing a semiconductor device, comprising: 前記金属酸化膜は酸化アルミニウム膜であることを特徴とする請求項１に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the metal oxide film is an aluminum oxide film. 前記金属酸化膜は、前記酸素含有雰囲気内において、基板温度２００℃を維持し、１２時間以上の時間の前記熱処理により形成されることを特徴とする請求項１又は請求項２に記載の半導体装置の製造方法。   3. The semiconductor device according to claim 1, wherein the metal oxide film is formed by the heat treatment for 12 hours or more while maintaining a substrate temperature of 200 ° C. in the oxygen-containing atmosphere. Manufacturing method. 前記金属酸化膜は、前記酸素含有雰囲気内において、基板温度３８０℃を維持し、６０分以上の時間の前記熱処理により形成されることを特徴とする請求項１又は請求項２に記載の半導体装置の製造方法。   3. The semiconductor device according to claim 1, wherein the metal oxide film is formed by the heat treatment for 60 minutes or more while maintaining a substrate temperature of 380 ° C. in the oxygen-containing atmosphere. Manufacturing method. 前記金属酸化膜は、５ｎｍ〜１９ｎｍの厚さに形成されることを特徴とす
る請求項１乃至請求項４のいずれか１項に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 1 , wherein the metal oxide film is formed to a thickness of 5 nm to 19 nm .
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US10770384B2 (en) 2017-02-24 2020-09-08 Samsung Electronics Co., Ltd. Printed circuit board having insulating metal oxide layer covering connection pad

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