JP5362719B2 - 接合構造および電子部品の製造方法 - Google Patents
接合構造および電子部品の製造方法 Download PDFInfo
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- JP5362719B2 JP5362719B2 JP2010517680A JP2010517680A JP5362719B2 JP 5362719 B2 JP5362719 B2 JP 5362719B2 JP 2010517680 A JP2010517680 A JP 2010517680A JP 2010517680 A JP2010517680 A JP 2010517680A JP 5362719 B2 JP5362719 B2 JP 5362719B2
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- Prior art keywords
- layer
- solder
- electrode
- electronic component
- barrier layer
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K1/00—Soldering, e.g. brazing, or unsoldering
- B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
- B23K1/0016—Brazing of electronic components
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
- B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
- B23K35/0233—Sheets, foils
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
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Description
図7に、従来のパワートランジスタの一例を、筐体の一部を透視した一部透視図により示す。図示例のトランジスタ100は、筐体102の内部に半導体素子104が配され、その半導体素子104は1つの電極106に直接的に接合されている。また、半導体素子104は、他の2つの電極108および110にワイヤにより接続されている。このような従来のパワートランジスタにおいて、半導体素子104を上記1つの電極に直接的に接合するための接合部には、はんだが使用されるのが通常である。
前記接合部は、前記電子素子と前記電極との間に位置する、0.2〜6重量%の銅と、0.02〜0.2重量%のゲルマニウムと、93.8〜99.78重量%のビスマスとを含むはんだ層と、
前記はんだ層と前記電子素子との間及び前記はんだ層と前記電極との間の少なく一方に位置するニッケル層と、
前記ニッケル層と前記はんだ層との間に位置し、前記ニッケル層と前記はんだ層との間の反応を阻止するバリア層と、を含み、
前記はんだによる接合後の前記バリア層の平均厚みが、0.5μm以上である接合構造を提供する。
前記接合部は、前記電子素子と前記電極との間に位置する、0.2〜6重量%の銅と、0.02〜0.2重量%のゲルマニウムと、93.8〜99.78重量%のビスマスとを含むはんだ層と、
前記はんだ層と前記電子素子との間及び前記はんだ層と前記電極との間の少なく一方に位置するニッケル層と、
前記ニッケル層と前記はんだ層との間に位置し、前記ニッケル層と前記はんだ層との間の反応を阻止するバリア層と、からなり、
前記バリア層は、前記電子素子と前記電極とを接合する前の初期厚みが1μm以上であり、その一部分を前記はんだ層に拡散させ、残りの部分を前記バリア層として残存させることを特徴とする電子部品の製造方法を提供する。
(実施の形態1)
図1に、本発明の実施の形態1に係る接合構造の概略構成を断面図により示す。図示例の接合構造10は、図示しない電子部品を構成する電子素子12を、その電子部品を構成する電極14と接合するための接合構造である。なお、図1においては、電子素子12は断面により示しておらず、概略形状を白抜きの図形により示している。
電極14は、Cu(銅)を主成分として含む。
一方、Geの含有量を0.1重量%以下とすることによって、コストの上昇を抑えることができる。
バリア層20は、Ni層18を構成するNiと、はんだ層16に含まれるBiとが反応して、Bi3Niからなる金属間化合物が生成されるのを防ぐために設けられる層である。バリア層20は、Biとの間に化合物を作らない材料から構成することができる。そのような、材料として、Ag(銀)、Au(金)、Pd(パラジウム)、Al(アルミニウム)およびTi(チタン)を挙げることができる。これらの中でも、酸化しにくく、濡れ性が良好であるという観点から、Ag、AuおよびTiが好ましく、さらに、コストおよびBiとの接合性を考慮すると、Agが最も好ましい。
(実施例)
電子部品として、図4Aおよび図4Bに示す、IGBTディスクリート・トランジスタからなるトランジスタ30を作成した。図4Aは、トランジスタ30の斜視図であり、図4Bは、図4AのIVB−IVB線による断面図である。
Si素子32の他の端子は、アルミニウム製のワイヤ38により他の電極とそれぞれ接続している。また、Si素子32は、図示しないエポキシ樹脂のモールド体により封止して、保護している。
接合部36は、はんだ層16と、リードフレーム34の表面に形成されたNi層18と、Ni層18の上に形成されたバリア層20とを含む。
Ni層18の厚みは2μmとした。バリア層20は、Agめっきにより、厚みが3μmとなるように形成した。
以上のようにして、計40個のトランジスタ30からなる試験体を作製した。そして、それらの試験体について、接合部36におけるBi3Niの生成の有無を調べた。その結果を、図5のグラフに示す。
Ni層18とはんだ層16との間にバリア層20を設けなかったこと以外は上記実施例と同様にして、IGBTディスクリート・トランジスタからなる試験体を作製した。このとき、はんだ付け時間は、5秒(比較例1)、10秒(比較例2)、20秒(比較例3)および30秒(比較例4)の4通りとし、その4通りのはんだ付け時間で各10個の試験体を作製した。そして、それらの試験体に対して、上記実施例に対して行ったのと同様の方法で、接合部におけるBi3Niの生成の有無を調べるとともに、接合信頼性試験を行った。その結果を、図5および図6に示す。
図5に示すように、Ni層18とはんだ層16との間にバリア層20を設けた実施例1〜4においては、はんだ付け時間を30秒に設定しても、Bi3Niからなる金属間化合物が生成されたものは存在しなかった。これに対して、バリア層20を設けていない比較例においては、全ての比較例1〜4において、Bi3Niからなる金属間化合物層が形成された。
12 電子素子
14 電極
16 はんだ層
18、22 Ni層
20、24 バリア層
Claims (4)
- 電子部品内部の電子素子と、前記電子部品の電極と、前記電子素子と前記電極との接合部と、を有する接合構造であって、
前記接合部は、前記電子素子と前記電極との間に位置する、0.2〜6重量%の銅と、0.02〜0.2重量%のゲルマニウムと、93.8〜99.78重量%のビスマスとを含むはんだ層と、
前記はんだ層と前記電子素子との間及び前記はんだ層と前記電極との間の少なく一方に位置するニッケル層と、
前記ニッケル層と前記はんだ層との間に位置し、前記ニッケル層と前記はんだ層との間の反応を阻止するバリア層と、を含み、
前記はんだによる接合後の前記バリア層の平均厚みが、0.5μm以上であり、
前記バリア層が銀を含む、接合構造。 - 前記はんだによる前記接合後の前記バリア層の平均厚みが、0.5〜4.5μmである請求項1記載の接合構造。
- 前記電極が、銅を含む請求項1記載の接合構造。
- 電子部品内部の電子素子と、前記電子部品の電極との接合部を形成する電子部品の製造方法であって、
前記接合部は、前記電子素子と前記電極との間に位置する、0.2〜6重量%の銅と、0.02〜0.2重量%のゲルマニウムと、93.8〜99.78重量%のビスマスとを
含むはんだ層と、
前記はんだ層と前記電子素子との間及び前記はんだ層と前記電極との間の少なく一方に位置するニッケル層と、
前記ニッケル層と前記はんだ層との間に位置し、前記ニッケル層と前記はんだ層との間の反応を阻止するバリア層と、からなり、
前記バリア層は、銀を含み、前記電子素子と前記電極とを接合する前の初期厚みが1μm以上であり、その一部分を前記はんだ層に拡散させ、残りの部分を前記バリア層として残存させることを特徴とする電子部品の製造方法。
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JP5723225B2 (ja) * | 2011-06-03 | 2015-05-27 | パナソニック株式会社 | 接合構造体 |
JP6011254B2 (ja) * | 2012-11-02 | 2016-10-19 | 住友金属鉱山株式会社 | Biを主成分とするはんだ合金との接合部を有する電子部品 |
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