JP5357315B1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5357315B1 JP5357315B1 JP2012205618A JP2012205618A JP5357315B1 JP 5357315 B1 JP5357315 B1 JP 5357315B1 JP 2012205618 A JP2012205618 A JP 2012205618A JP 2012205618 A JP2012205618 A JP 2012205618A JP 5357315 B1 JP5357315 B1 JP 5357315B1
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- electrode
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- diode
- wiring pattern
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 239000007767 bonding agent Substances 0.000 claims description 25
- 230000005669 field effect Effects 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 20
- 229910052709 silver Inorganic materials 0.000 description 20
- 239000004332 silver Substances 0.000 description 20
- 239000010949 copper Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 10
- 229910010271 silicon carbide Inorganic materials 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Abstract
【解決手段】半導体装置10であって、基板18上に設けられたスイッチング素子(FET14)と、スイッチング素子を挟んで基板18と反対側に設けられた第1の電極(電極13)と、第1の電極を挟んでスイッチング素子と反対側に設けられたダイオード12と、ダイオード12を挟んで第1の電極と反対側に設けられた第2の電極(電極11)とを備える。
【選択図】図1
Description
前記ゲートが前記基板上の第2の配線パターンに接続され、前記ドレインが前記第1の電極に接続され、前記第1の電極の脚部と、前記基板上の前記第1の配線パターン及び前記第2の配線パターンとは異なる配線パターンとが接続され、前記ダイオードは、板状に形成されており、一方の面にアノードが設けられ、他方の面にカソードが設けられ、前記カソードが前記第1の電極に接続され、前記アノードが前記第2の電極に接続され、前記第2の電極の脚部と、前記第1の配線パターンとが接続され、前記第1の電極の脚部と、前記第2の電極の脚部とは、前記FETを挟んで対向していることを特徴とする。
また、上記課題を解決するための第二の態様は、例えば、半導体装置であって、基板上に設けられたFET(Field effect transistor)と、前記FETを挟んで前記基板と反対側に設けられた第1の電極と、前記第1の電極を挟んで前記FETと反対側に設けられたダイオードと、前記ダイオードを挟んで前記第1の電極と反対側に設けられた第2の電極と備え、前記FETは、板状に形成されており、一方の面にソースおよびゲートが設けられ、他方の面にドレインが設けられ、前記ソースが前記基板上の第1の配線パターンに接続され、前記ゲートが前記基板上の第2の配線パターンに接続され、前記ドレインが前記第1の電極に接続され、前記ダイオードは、板状に形成されており、一方の面にアノードが設けられ、他方の面にカソードが設けられ、前記カソードが前記第1の電極に接続され、前記アノードが前記第2の電極に接続され、前記第2の電極と前記第1の配線パターンとが接続され、前記第1の電極の前記ダイオードと接続する面は、前記FET及び前記ダイオードより大きく、前記FETの辺と平行かつ前記ソース及び前記ゲートを通る線を含み、前記FETの前記一方の面に直交する面で前記半導体装置を切断した断面において、前記カソードの長さは、前記ソースの長さと前記ゲートの長さの和よりも長いことを特徴とする。
また、上記課題を解決するための第四の態様は、例えば、半導体装置であって、基板上に設けられた第1のFET(Field effect transistor)と、前記第1のFETを挟んで前記基板と反対側に設けられた第1の電極と、前記第1の電極を挟んで前記第1のFETと反対側に設けられた第1のダイオードと、前記第1のダイオードを挟んで前記第1の電極と反対側に設けられた第2の電極と、前記第2の電極を挟んで前記第1のダイオードと反対側に設けられた第2のダイオードと、前記第2のダイオードを挟んで前記第2の電極と反対側に設けられた第3の電極と、前記第3の電極を挟んで前記第2のダイオードと反対側に設けられた第2のFETと、前記第2のFETを挟んで前記第3の電極と反対側に設けられた第4の電極とを備え、前記第1および第2のFETは、それぞれ板状に形成されており、一方の面にソースおよびゲートが設けられ、他方の面にドレインが設けられ、前記第1のFETのソースが前記基板上に設けられた第1の配線パターンに接続され、前記第1のFETのゲートが前記基板上に設けられた第2の配線パターンに接続され、前記第1のFETのドレインが前記第1の電極に接続され、前記第2のFETのソースが前記第3の電極に接続され、前記第2のFETのゲートが第5の電極に接続され、前記第2のFETのドレインが前記第4の電極に接続され、前記第1および第2のダイオードは、それぞれ、少なくとも一部が板状に形成されており、一方の面にアノードが設けられ、他方の面にカソードが設けられ、前記第1のダイオードのカソードが前記第1の電極に接続され、前記第1のダイオードのアノードが前記第2の電極に接続され、前記第2のダイオードのカソードが前記第2の電極に接続され、前記第2のダイオードのアノードが前記第3の電極に接続され、前記第2の電極と前記第4の電極と前記第1の配線パターンとが接続され、前記第1の電極の前記第1のダイオードと接続する面は、前記第1のFET及び前記第1のダイオードより大きく、前記第1のFETの辺と平行かつ前記第1のFETのソース及び前記第1のFETのゲートを通る線を含み、前記第1のFETの前記一方の面に直交する面で前記半導体装置を切断した断面において、前記第1のダイオードのカソードの長さは、前記第1のFETのソースの長さと前記第1のFETのゲートの長さの和よりも長いことを特徴とする。
Claims (9)
- 半導体装置であって、
基板上に設けられたFET(Field effect transistor)と、
前記FETを挟んで前記基板と反対側に設けられた第1の電極と、
前記第1の電極を挟んで前記FETと反対側に設けられたダイオードと、
前記ダイオードを挟んで前記第1の電極と反対側に設けられた第2の電極と
を備え、
前記FETは、板状に形成されており、
一方の面にソースおよびゲートが設けられ、他方の面にドレインが設けられ、
前記ソースが前記基板上の第1の配線パターンに接続され、
前記ゲートが前記基板上の第2の配線パターンに接続され、
前記ドレインが前記第1の電極に接続され、
前記第1の電極の脚部と、前記基板上の前記第1の配線パターン及び前記第2の配線パターンとは異なる配線パターンとが接続され、
前記ダイオードは、板状に形成されており、
一方の面にアノードが設けられ、他方の面にカソードが設けられ、
前記カソードが前記第1の電極に接続され、
前記アノードが前記第2の電極に接続され、
前記第2の電極の脚部と、前記第1の配線パターンとが接続され、
前記第1の電極の脚部と、前記第2の電極の脚部とは、前記FETを挟んで対向している
ことを特徴とする半導体装置。 - 半導体装置であって、
基板上に設けられたFET(Field effect transistor)と、
前記FETを挟んで前記基板と反対側に設けられた第1の電極と、
前記第1の電極を挟んで前記FETと反対側に設けられたダイオードと、
前記ダイオードを挟んで前記第1の電極と反対側に設けられた第2の電極と
を備え、
前記FETは、板状に形成されており、
一方の面にソースおよびゲートが設けられ、他方の面にドレインが設けられ、
前記ソースが前記基板上の第1の配線パターンに接続され、
前記ゲートが前記基板上の第2の配線パターンに接続され、
前記ドレインが前記第1の電極に接続され、
前記ダイオードは、板状に形成されており、
一方の面にアノードが設けられ、他方の面にカソードが設けられ、
前記カソードが前記第1の電極に接続され、
前記アノードが前記第2の電極に接続され、
前記第2の電極と前記第1の配線パターンとが接続され、
前記第1の電極の前記ダイオードと接続する面は、前記FET及び前記ダイオードより大きく、
前記FETの辺と平行かつ前記ソース及び前記ゲートを通る線を含み、前記FETの前記一方の面に直交する面で前記半導体装置を切断した断面において、前記カソードの長さは、前記ソースの長さと前記ゲートの長さの和よりも長い
ことを特徴とする半導体装置。 - 請求項1又は2に記載の半導体装置であって、
前記FETの辺と平行かつ前記ソース及び前記ゲートを通る線を含み、前記FETの前記一方の面に直交する面で前記半導体装置を切断した断面において、前記第1の電極及び前記第2の電極はL字形状であり、
前記第1の電極及び前記第2の電極は、前記L字形状のうちの長辺に相当する部分が前記基板と平行、かつ前記L字形状のうちの短辺に相当する部分の先端が前記基板上のパターンと当接するように設けられる
ことを特徴とする半導体装置。 - 請求項1から3のいずれかに記載の半導体装置であって、
前記第1および第2の電極は、少なくとも一部が板状の電極であり、
前記第1の電極は、
前記FETにおける前記ドレインの面で前記FETと接続し、前記ダイオードにおける前記カソードの面で前記ダイオードと接続し、
前記第2の電極は、
前記ダイオードにおける前記アノードの面で前記ダイオードと接続し、
前記第1の配線パターンは、
前記FETにおける前記ソースの面で前記FETと接続していることを特徴とする半導体装置。 - 請求項1から4のいずれかに記載の半導体装置であって、
前記第1の電極には、
前記FETと接続される面に、前記第1の電極と前記FETとの位置を合わせるための窪みまたは突起が設けられ、
前記ダイオードと接続される面に、前記第1の電極と前記ダイオードとの位置を合わせるための窪みまたは突起が設けられており、
前記第2の電極には、
前記ダイオードと接続される面に、前記第2の電極と前記ダイオードとの位置を合わせるための窪みまたは突起が設けられており、
前記1の配線パターンには、
前記FETと接続される面に、前記第1の配線パターンと前記FETとの位置を合わせるための窪みまたは突起が設けられていることを特徴とする半導体装置。 - 請求項1から5のいずれか一項に記載の半導体装置であって、
前記第1の電極と前記FET、前記第1の電極と前記ダイオード、前記第2の電極と前記ダイオード、前記第1の配線パターンと前記FETは、それぞれ導電性の接合剤で接続され、
前記第1の電極における前記FETが接続される側および前記ダイオードが接続される側、前記第2の電極における前記ダイオードが接続される側、ならびに、前記第1の配線パターンにおける前記FETが接続される側には、それぞれ、前記導電性の接合剤の広がりを抑えるための堰き止め部が設けられていることを特徴とする半導体装置。 - 請求項1から6のいずれか一項に記載の半導体装置において、
前記第2の電極を挟んで前記ダイオードと反対側に設けられ絶縁層と、
前記絶縁層を挟んで前記第2の電極と反対側に設けられた放熱板と
をさらに備え、
前記半導体装置を樹脂封止し、前記放熱板において前記絶縁層に接する面と反対側の部分を外部に露出させたことを特徴とする半導体装置。 - 半導体装置であって、
基板上に設けられた第1のFET(Field effect transistor)と、
前記第1のFETを挟んで前記基板と反対側に設けられた第1の電極と、
前記第1の電極を挟んで前記第1のFETと反対側に設けられた第1のダイオードと、
前記第1のダイオードを挟んで前記第1の電極と反対側に設けられた第2の電極と、
前記第2の電極を挟んで前記第1のダイオードと反対側に設けられた第2のダイオードと、
前記第2のダイオードを挟んで前記第2の電極と反対側に設けられた第3の電極と、
前記第3の電極を挟んで前記第2のダイオードと反対側に設けられた第2のFETと、
前記第2のFETを挟んで前記第3の電極と反対側に設けられた第4の電極と
を備え、
前記第1および第2のFETは、それぞれ板状に形成されており、一方の面にソースおよびゲートが設けられ、他方の面にドレインが設けられ、
前記第1のFETのソースが前記基板上に設けられた第1の配線パターンに接続され、
前記第1のFETのゲートが前記基板上に設けられた第2の配線パターンに接続され、
前記第1のFETのドレインが前記第1の電極に接続され、
前記第1の電極の脚部と、前記基板上の前記第1の配線パターン及び前記第2の配線パターンとは異なる配線パターンとが接続され、
前記第2のFETのソースが前記第3の電極に接続され、
前記第2のFETのゲートが第5の電極に接続され、
前記第2のFETのドレインが前記第4の電極に接続され、
前記第1および第2のダイオードは、それぞれ、少なくとも一部が板状に形成されており、一方の面にアノードが設けられ、他方の面にカソードが設けられ、
前記第1のダイオードのカソードが前記第1の電極に接続され、
前記第1のダイオードのアノードが前記第2の電極に接続され、
前記第2のダイオードのカソードが前記第2の電極に接続され、
前記第2のダイオードのアノードが前記第3の電極に接続され、
前記第2の電極の脚部と前記第1の配線パターンとが接続され、
前記第1の電極の脚部と、前記第2の電極の脚部及び前記第4の電極の脚部とは、前記第1のFET、前記第2のFET、前記第1のダイオード及び前記第2のダイオードを挟んで対向している
ことを特徴とする半導体装置。 - 半導体装置であって、
基板上に設けられた第1のFET(Field effect transistor)と、
前記第1のFETを挟んで前記基板と反対側に設けられた第1の電極と、
前記第1の電極を挟んで前記第1のFETと反対側に設けられた第1のダイオードと、
前記第1のダイオードを挟んで前記第1の電極と反対側に設けられた第2の電極と、
前記第2の電極を挟んで前記第1のダイオードと反対側に設けられた第2のダイオードと、
前記第2のダイオードを挟んで前記第2の電極と反対側に設けられた第3の電極と、
前記第3の電極を挟んで前記第2のダイオードと反対側に設けられた第2のFETと、
前記第2のFETを挟んで前記第3の電極と反対側に設けられた第4の電極と
を備え、
前記第1および第2のFETは、それぞれ板状に形成されており、一方の面にソースおよびゲートが設けられ、他方の面にドレインが設けられ、
前記第1のFETのソースが前記基板上に設けられた第1の配線パターンに接続され、
前記第1のFETのゲートが前記基板上に設けられた第2の配線パターンに接続され、
前記第1のFETのドレインが前記第1の電極に接続され、
前記第2のFETのソースが前記第3の電極に接続され、
前記第2のFETのゲートが第5の電極に接続され、
前記第2のFETのドレインが前記第4の電極に接続され、
前記第1および第2のダイオードは、それぞれ、少なくとも一部が板状に形成されており、一方の面にアノードが設けられ、他方の面にカソードが設けられ、
前記第1のダイオードのカソードが前記第1の電極に接続され、
前記第1のダイオードのアノードが前記第2の電極に接続され、
前記第2のダイオードのカソードが前記第2の電極に接続され、
前記第2のダイオードのアノードが前記第3の電極に接続され、
前記第2の電極と前記第4の電極と前記第1の配線パターンとが接続され、
前記第1の電極の前記第1のダイオードと接続する面は、前記第1のFET及び前記第1のダイオードより大きく、
前記第1のFETの辺と平行かつ前記第1のFETのソース及び前記第1のFETのゲートを通る線を含み、前記第1のFETの前記一方の面に直交する面で前記半導体装置を切断した断面において、前記第1のダイオードのカソードの長さは、前記第1のFETのソースの長さと前記第1のFETのゲートの長さの和よりも長い
ことを特徴とする半導体装置。
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CN201380002517.8A CN103828044A (zh) | 2012-09-19 | 2013-08-30 | 半导体器件 |
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US9922970B2 (en) * | 2015-02-13 | 2018-03-20 | Qualcomm Incorporated | Interposer having stacked devices |
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CN103828044A (zh) | 2014-05-28 |
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US9159715B2 (en) | 2015-10-13 |
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