JP5344829B2 - Integrated circuit - Google Patents

Integrated circuit Download PDF

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JP5344829B2
JP5344829B2 JP2008058904A JP2008058904A JP5344829B2 JP 5344829 B2 JP5344829 B2 JP 5344829B2 JP 2008058904 A JP2008058904 A JP 2008058904A JP 2008058904 A JP2008058904 A JP 2008058904A JP 5344829 B2 JP5344829 B2 JP 5344829B2
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integrated circuit
light receiving
reference potential
receiving element
wiring pattern
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JP2009218308A (en
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小野　　純
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TDK Corp
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TDK Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

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  • Optical Head (AREA)
  • Die Bonding (AREA)
  • Light Receiving Elements (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

本発明は集積回路に関し、特に、フレキシブルプリント配線板上に集積回路素子が配置される集積回路に関する。   The present invention relates to an integrated circuit, and more particularly to an integrated circuit in which an integrated circuit element is disposed on a flexible printed wiring board.

光学ドライブ装置の光ヘッドにおいては、記録面で反射したレーザー光を受光して電気信号に変換するための受光素子を含む集積回路が用いられる（例えば特許文献１参照。）。この集積回路は通常、フレキシブルプリント配線板（ＦＰＣ）を用いて構成される。ＦＰＣは形状に自由度を有し、柔軟性の高い回路接続が可能となるからである。   In an optical head of an optical drive device, an integrated circuit including a light receiving element for receiving a laser beam reflected on a recording surface and converting it into an electric signal is used (see, for example, Patent Document 1). This integrated circuit is usually configured using a flexible printed wiring board (FPC). This is because the FPC has a degree of freedom in shape and allows a highly flexible circuit connection.

ところで、近年光ヘッドの性能向上に対する要求が増しており、受光素子にも周波数特性の向上が求められている。そこで従来、半導体プロセス技術、回路技術、実装技術など複数種の技術を駆使することによって受光素子の周波数特性の向上が図られている。
特開２００８−４１２２６号公報 Incidentally, in recent years, demands for improving the performance of optical heads are increasing, and light receiving elements are also required to improve frequency characteristics. Therefore, conventionally, the frequency characteristics of the light receiving element have been improved by making full use of a plurality of types of technologies such as semiconductor process technology, circuit technology, and mounting technology.
JP 2008-41226 A

受光素子の周波数特性を向上させるための具体的な技術のひとつに、受光素子裏面の電位を基準電位とする技術がある。以下、簡単に説明する。   One specific technique for improving the frequency characteristics of the light receiving element is a technique in which the potential on the back surface of the light receiving element is set as a reference potential. A brief description is given below.

図４はＦＰＣ１００の一部を示している。同図に示すように、ＦＰＣ１００上には基準電圧に接続されたダイパッドエリア１０１が設けられ、その上に受光素子１０２が配置される。こうすることで受光素子裏面の電位を基準電位に保つことが可能となり、特に大光量時の周波数特性の劣化が防止される。   FIG. 4 shows a part of the FPC 100. As shown in the figure, a die pad area 101 connected to a reference voltage is provided on the FPC 100, and a light receiving element 102 is arranged thereon. In this way, the potential on the back surface of the light receiving element can be maintained at the reference potential, and deterioration of the frequency characteristics especially when the amount of light is large is prevented.

しかしながら、上記技術ではダイパッドエリアが必要になるため、ＦＰＣの面積が大きくなってしまうという問題があった。加えて、ＦＰＣは比較的高価であるため、ＦＰＣの面積が大きくなった分、光ヘッド全体の価格が高くなってしまうという問題があった。   However, since the above technique requires a die pad area, there is a problem that the area of the FPC becomes large. In addition, since the FPC is relatively expensive, there is a problem that the price of the entire optical head increases as the area of the FPC increases.

このような問題は受光素子に限って発生するものではなく、集積回路の構成要素としての集積回路素子全般に広く起こり得る問題である。   Such a problem does not occur only in the light receiving element, but is a problem that can occur widely in general integrated circuit elements as components of the integrated circuit.

したがって、本発明の目的は、集積回路素子裏面の電位を基準電位に保ちながら、フレキシブルプリント配線板の面積の増大を抑制できる集積回路を提供することにある。   Accordingly, an object of the present invention is to provide an integrated circuit capable of suppressing an increase in the area of a flexible printed wiring board while keeping the potential of the back surface of the integrated circuit element at a reference potential.

上記課題を解決するための本発明による集積回路は、配線パターンを有するフレキシブルプリント配線板と、前記配線パターン上の一部に覆設された絶縁性保護膜と、少なくとも前記絶縁性保護膜上の一部に覆設され、かつ基準電位に接続される導電性接着膜と、前記導電性接着膜上に接して配置された集積回路素子とを備えることを特徴とする。   In order to solve the above problems, an integrated circuit according to the present invention includes a flexible printed wiring board having a wiring pattern, an insulating protective film partially covered on the wiring pattern, and at least on the insulating protective film. A conductive adhesive film partially covered and connected to a reference potential, and an integrated circuit element disposed in contact with the conductive adhesive film are provided.

本発明によれば、ダイパッドエリアを設けなくても集積回路素子裏面の電位を基準電位に保つことが可能になり、したがってフレキシブルプリント配線板の面積の増大を抑制できる。   According to the present invention, it is possible to keep the potential of the back surface of the integrated circuit element at the reference potential without providing a die pad area, and therefore it is possible to suppress an increase in the area of the flexible printed wiring board.

また、上記各集積回路において、前記配線パターンは前記基準電位に接続された基準電位パターンを含み、前記絶縁性保護膜は前記基準電位パターンの少なくとも一部を残して前記配線パターン上に覆設され、前記導電性接着膜は前記絶縁性保護膜及び前記基準電位パターンに接触して覆設されることとしてもよい。これによれば、導電性接着膜の電位を基準電位に保つことができる。   In each of the integrated circuits, the wiring pattern includes a reference potential pattern connected to the reference potential, and the insulating protective film is provided on the wiring pattern leaving at least a part of the reference potential pattern. The conductive adhesive film may be covered with the insulating protective film and the reference potential pattern. According to this, the potential of the conductive adhesive film can be kept at the reference potential.

なお、上記各集積回路において、前記導電性接着膜はエポキシ系導電性接着剤であることが好適であり、前記絶縁性保護膜はカバーレイ又は絶縁レジストであることが好適である。   In each of the integrated circuits, the conductive adhesive film is preferably an epoxy conductive adhesive, and the insulating protective film is preferably a cover lay or an insulating resist.

また、上記各集積回路において、前記集積回路素子と前記配線パターンとはボンディングワイヤによって接続されていることとしてもよい。これによれば、ワイヤボンディング法によって集積回路素子をフレキシブルプリント配線板上に実装できる。   In each of the integrated circuits, the integrated circuit element and the wiring pattern may be connected by a bonding wire. According to this, the integrated circuit element can be mounted on the flexible printed wiring board by the wire bonding method.

また、上記集積回路において、前記ボンディングワイヤと前記配線パターンとの接続部は樹脂により封止されていることとしてもよい。これによれば、樹脂によって接続部を保護することができる。   In the integrated circuit, a connection portion between the bonding wire and the wiring pattern may be sealed with resin. According to this, a connection part can be protected with resin.

また、上記集積回路において、前記集積回路素子は受光面を有する受光素子であり、前記受光面は前記樹脂上に露出していることとしてもよい。こうすれば、受光素子は好適に光ビームを受光できる。   In the integrated circuit, the integrated circuit element may be a light receiving element having a light receiving surface, and the light receiving surface may be exposed on the resin. In this way, the light receiving element can receive the light beam suitably.

本発明によれば、集積回路素子裏面の電位を基準電位に保ちながら、フレキシブルプリント配線板の面積の増大を抑制できる。   ADVANTAGE OF THE INVENTION According to this invention, the increase in the area of a flexible printed wiring board can be suppressed, keeping the electric potential of an integrated circuit element back surface at a reference electric potential.

以下、添付図面を参照しながら、本発明の好ましい実施の形態について詳細に説明する。   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

図１は本実施の形態による集積回路１の一部を拡大してなる平面図である。同図に示すように、集積回路１は、多数の銅箔配線パターン４を有するＦＰＣ２と、受光素子３とを備えている。   FIG. 1 is an enlarged plan view of a part of an integrated circuit 1 according to the present embodiment. As shown in the figure, the integrated circuit 1 includes an FPC 2 having a large number of copper foil wiring patterns 4 and a light receiving element 3.

この集積回路１は光ディスクを読み取るために用いられる光ヘッドに備えられるものであり、受光素子３は４分割された受光部（カソード）Ｄ１〜Ｄ４と各受光部に対応するアノードＰ１〜Ｐ４を備えている。受光部Ｄ１〜Ｄ４はそれぞれ受光面を有しており、光ディスクで反射してきた光ビームを受光面で受光し、その受光量を示す電気信号を出力する。   The integrated circuit 1 is provided in an optical head used for reading an optical disk, and the light receiving element 3 includes four divided light receiving portions (cathodes) D1 to D4 and anodes P1 to P4 corresponding to the light receiving portions. ing. Each of the light receiving parts D1 to D4 has a light receiving surface, receives the light beam reflected by the optical disk by the light receiving surface, and outputs an electric signal indicating the amount of light received.

受光部Ｄ１〜Ｄ４及びアノードＰ１〜Ｐ４はそれぞれボンディングワイヤによって配線パターン４に接続されている。具体的には、配線パターン４は、図１に示すように、ボンディングワイヤを接続するための複数のボンディングパッド４ａと、基準電位（グランド）が接続された基準電位パターン４ｂとを含んで構成されており、受光部Ｄ１〜Ｄ４及びアノードＰ１〜Ｐ４はそれぞれいずれかのボンディングパッド４ａにボンディングワイヤによって接続されている。   The light receiving portions D1 to D4 and the anodes P1 to P4 are connected to the wiring pattern 4 by bonding wires, respectively. Specifically, as shown in FIG. 1, the wiring pattern 4 includes a plurality of bonding pads 4a for connecting bonding wires and a reference potential pattern 4b to which a reference potential (ground) is connected. Each of the light receiving portions D1 to D4 and the anodes P1 to P4 is connected to one of the bonding pads 4a by a bonding wire.

受光素子３は、配線パターン４上に、複数の配線を跨って配置されている。以下、具体的に説明する。   The light receiving element 3 is disposed on the wiring pattern 4 across a plurality of wirings. This will be specifically described below.

図２は図１のＡ−Ａ'線断面図であり、図３は図１のＢ−Ｂ'線断面図である。両図に示すように、集積回路１は配線パターン４上の一部に複数の配線を跨って覆設された絶縁性保護膜７と、この絶縁性保護膜７上の一部に覆設され、かつ基準電位に接続される導電性接着膜８とを備えている。受光素子３は導電性接着膜８上に接して配置されている。したがって、受光素子３裏面の電位は基準電位に保たれている。   2 is a cross-sectional view taken along the line AA ′ in FIG. 1, and FIG. 3 is a cross-sectional view taken along the line BB ′ in FIG. As shown in both figures, the integrated circuit 1 is covered with an insulating protective film 7 that covers a part of the wiring pattern 4 across a plurality of wires and a part of the insulating protective film 7. And a conductive adhesive film 8 connected to a reference potential. The light receiving element 3 is disposed in contact with the conductive adhesive film 8. Therefore, the potential on the back surface of the light receiving element 3 is kept at the reference potential.

導電性接着膜８は次のようにして基準電位に接続される。すなわち、絶縁性保護膜７は、図２及び図３に示すように、基準電位パターン４ｂの少なくとも一部を残して配線パターン４上に覆設されている。そして、導電性接着膜８は絶縁性保護膜７及び基準電位パターン４ｂ（絶縁性保護膜７が覆設されていない部分）に接触して覆設される。これにより導電性接着膜８は基準電位パターン４ｂと電気的に接触するので、導電性接着膜８は基準電位に接続されることになる。   The conductive adhesive film 8 is connected to the reference potential as follows. That is, as shown in FIGS. 2 and 3, the insulating protective film 7 is provided on the wiring pattern 4 while leaving at least a part of the reference potential pattern 4b. Then, the conductive adhesive film 8 is placed in contact with the insulating protective film 7 and the reference potential pattern 4b (a portion where the insulating protective film 7 is not covered). As a result, the conductive adhesive film 8 is in electrical contact with the reference potential pattern 4b, so that the conductive adhesive film 8 is connected to the reference potential.

なお、絶縁性保護膜７は、導電性接着膜８が基準電位パターン４ｂ以外の配線パターン４に接触しないよう覆設される。   The insulating protective film 7 is provided so that the conductive adhesive film 8 does not contact the wiring pattern 4 other than the reference potential pattern 4b.

絶縁性保護膜７の形成は、フィルム張り合わせ、もしくはスクリーン印刷法を用い、ＦＰＣ２上の所定領域に基準電位パターン４ｂを露出させたカバーレイ又は絶縁レジストを形成することによって行うことが好適である。このようにして形成した絶縁性保護膜７は、図２及び図３にも示すように配線パターン４に沿って若干の凹凸を有する。   The insulating protective film 7 is preferably formed by forming a cover lay or an insulating resist in which the reference potential pattern 4b is exposed in a predetermined region on the FPC 2 by using film bonding or screen printing. The insulating protective film 7 formed in this way has some unevenness along the wiring pattern 4 as shown in FIGS.

導電性接着膜８としてはエポキシ系導電性接着剤を用いることが好適である。集積回路１では、絶縁性保護膜７の表面に上記凹凸があることによって、エポキシ系導電性接着剤を用いて接着した場合の受光素子３の密着性が高められている。また、エポキシ系導電性接着剤を用いることによって受光素子３を極力水平に保つことが可能になっている。   As the conductive adhesive film 8, an epoxy-based conductive adhesive is preferably used. In the integrated circuit 1, the unevenness on the surface of the insulating protective film 7 enhances the adhesion of the light receiving element 3 when bonded using an epoxy conductive adhesive. Further, by using an epoxy conductive adhesive, the light receiving element 3 can be kept horizontal as much as possible.

また、図２及び図３に示すように、集積回路１の一部（ボンディングワイヤ５と配線パターン４の接続部を含む。）は表面に形成された樹脂層９により封止されている。光ビームを受光する必要があるため、受光素子３の受光部Ｄ１〜Ｄ４の受光面上には樹脂層９は形成されず、受光部Ｄ１〜Ｄ４の受光面は樹脂上に露出している。   As shown in FIGS. 2 and 3, a part of the integrated circuit 1 (including a connection portion between the bonding wire 5 and the wiring pattern 4) is sealed with a resin layer 9 formed on the surface. Since it is necessary to receive the light beam, the resin layer 9 is not formed on the light receiving surfaces of the light receiving portions D1 to D4 of the light receiving element 3, and the light receiving surfaces of the light receiving portions D1 to D4 are exposed on the resin.

以上説明したように、集積回路１によれば、ダイパッドエリアを設けなくても受光素子３裏面の電位を基準電位に保つことが可能になり、したがってＦＰＣ２の面積の増大を抑制できる。そしてこれにより、光ヘッド全体の価格を抑制する効果が得られている。   As described above, according to the integrated circuit 1, it is possible to keep the potential of the back surface of the light receiving element 3 at the reference potential without providing a die pad area, and thus it is possible to suppress an increase in the area of the FPC 2. As a result, an effect of suppressing the price of the entire optical head is obtained.

また、従来は、ダイパッドエリア上に受光素子を配置する際、直接的にはリードフレーム等の中間部材を配置し、中間部材内に設けられるダイパッド上に受光素子を配置するという構成が採用されることがあった。ダイパッドと受光素子裏面とは密着性がよいため、ダイパッドを基準電位に接続さえしておけば受光素子裏面の電位を確実に基準電位にすることができるからであるが、集積回路１によれば導電性接着膜８と受光素子裏面とを確実に密着させられるので、中間部材を用いなくとも受光素子３裏面の電位を確実に基準電位に保つことが可能になる。   Conventionally, when a light receiving element is disposed on the die pad area, an intermediate member such as a lead frame is directly disposed, and the light receiving element is disposed on a die pad provided in the intermediate member. There was a thing. This is because the adhesion between the die pad and the back surface of the light receiving element is good, and as long as the die pad is connected to the reference potential, the potential on the back surface of the light receiving element can be reliably set to the reference potential. Since the conductive adhesive film 8 and the back surface of the light receiving element can be reliably adhered, the potential of the back surface of the light receiving element 3 can be reliably maintained at the reference potential without using an intermediate member.

以上、本発明の好ましい実施の形態について説明したが、本発明はこうした実施の形態に何等限定されるものではなく、本発明が、その要旨を逸脱しない範囲において、種々なる態様で実施され得ることは勿論である。   As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to such embodiment at all, and this invention can be implemented in various aspects in the range which does not deviate from the summary. Of course.

例えば上記実施の形態では受光素子３を用いる場合について説明したが、受光素子３以外の集積回路素子にも本発明は適用可能である。また、光ヘッドに用いられる集積回路だけでなく、他の用途に用いられる集積回路にも本発明は適用可能である。   For example, although the case where the light receiving element 3 is used has been described in the above embodiment, the present invention can be applied to an integrated circuit element other than the light receiving element 3. Further, the present invention can be applied not only to an integrated circuit used for an optical head but also to an integrated circuit used for other purposes.

本発明の好ましい実施の形態による集積回路の一部を拡大してなる平面図である。It is a top view formed by enlarging a part of integrated circuit by preferable embodiment of this invention. 図１のＡ−Ａ'線断面図である。It is the sectional view on the AA 'line of FIG. 図１のＢ−Ｂ'線断面図である。FIG. 3 is a cross-sectional view taken along line BB ′ in FIG. 1. 受光素子の周波数特性を向上させるための技術によるＦＰＣの平面図である。It is a top view of FPC by the technique for improving the frequency characteristic of a light receiving element.

符号の説明Explanation of symbols

１ 集積回路
２ ＦＰＣ（フレキシブルプリント配線板）
３ 受光素子
４ 配線パターン
４ 配線パターン
４ａ ボンディングパッド
４ｂ 基準電位パターン
５ ボンディングワイヤ
７ 絶縁性保護膜
８ 導電性接着膜
９ 樹脂層
Ｄ１〜Ｄ４ 受光部（カソード）
Ｐ１〜Ｐ４ アノード 1 Integrated Circuit 2 FPC (Flexible Printed Wiring Board)
3 Photodetector 4 Wiring pattern 4 Wiring pattern 4a Bonding pad 4b Reference potential pattern 5 Bonding wire 7 Insulating protective film 8 Conductive adhesive film 9 Resin layers D1 to D4 Light receiving part (cathode)
P1-P4 anode

Claims (5)

互いに同一平面内に形成された基準電位パターン及び通常配線パターンを含む配線パターンを有するフレキシブルプリント配線板と、
前記配線パターン上に、少なくとも前記基準電位パターンの少なくとも一部を残して覆設された絶縁性保護膜と、
少なくとも前記絶縁性保護膜上の一部に覆設され、かつ前記基準電位パターンの前記残された部分に接触する導電性接着膜と、
前記導電性接着膜上に接して配置された受光素子とを備え、
前記受光素子は、垂直方向に見て前記基準電位パターン及び前記通常配線パターンのそれぞれと重なる位置に配置される集積回路であって、
前記配線パターンは、第１及び第２のボンディングパッド列を構成する複数のボンディングパッドをさらに有し、
前記集積回路は、前記複数のボンディングパッドのそれぞれと前記受光素子とを接続する複数のボンディングワイヤをさらに備え、
前記基準電位パターンのうち垂直方向に見て前記受光素子の下にある部分は、前記第１のボンディングパッド列と前記第２のボンディングパッド列との間の領域を延伸することを特徴とする集積回路。 A flexible printed wiring board having a wiring pattern including a reference potential pattern and a normal wiring pattern formed in the same plane;
An insulating protective film overlaid on the wiring pattern leaving at least a part of the reference potential pattern;
A conductive adhesive film that covers at least part of the insulating protective film and contacts the remaining portion of the reference potential pattern;
A light receiving element disposed on and in contact with the conductive adhesive film,
The light receiving element is an integrated circuit disposed at a position overlapping each of the reference potential pattern and the normal wiring pattern when viewed in the vertical direction,
The wiring pattern further includes a plurality of bonding pads constituting first and second bonding pad rows ,
The integrated circuit further comprises a plurality of bonding wires connecting each of the plurality of bonding pads and the light receiving element,
Area below the light-receiving element as viewed in the vertical direction of the reference potential pattern is characterized by stretching the realm between the first bonding pad row and the second bonding pad row Integrated circuit. 前記導電性接着膜はエポキシ系導電性接着剤であることを特徴とする請求項１に記載の集積回路。   The integrated circuit according to claim 1, wherein the conductive adhesive film is an epoxy-based conductive adhesive. 前記絶縁性保護膜はカバーレイ又は絶縁レジストであることを特徴とする請求項１又は２に記載の集積回路。   The integrated circuit according to claim 1, wherein the insulating protective film is a cover lay or an insulating resist. 前記ボンディングワイヤと前記配線パターンとの接続部は樹脂により封止されていることを特徴とする請求項１乃至３のいずれか一項に記載の集積回路。   The integrated circuit according to claim 1, wherein a connection portion between the bonding wire and the wiring pattern is sealed with resin. 前記受光素子は受光面を有し、
前記受光面は前記樹脂上に露出していることを特徴とする請求項４に記載の集積回路。 The light receiving element have a light receiving surface,
The integrated circuit according to claim 4, wherein the light receiving surface is exposed on the resin.
JP2008058904A 2008-03-10 2008-03-10 Integrated circuit Expired - Fee Related JP5344829B2 (en)

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