JP5292591B2 - Tft基板の製造方法 - Google Patents
Tft基板の製造方法 Download PDFInfo
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- JP5292591B2 JP5292591B2 JP2007272088A JP2007272088A JP5292591B2 JP 5292591 B2 JP5292591 B2 JP 5292591B2 JP 2007272088 A JP2007272088 A JP 2007272088A JP 2007272088 A JP2007272088 A JP 2007272088A JP 5292591 B2 JP5292591 B2 JP 5292591B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 44
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- 238000000034 method Methods 0.000 claims description 35
- 239000004065 semiconductor Substances 0.000 claims description 25
- 239000010408 film Substances 0.000 description 168
- 108091006146 Channels Proteins 0.000 description 51
- 238000002513 implantation Methods 0.000 description 27
- 238000010586 diagram Methods 0.000 description 19
- 238000004380 ashing Methods 0.000 description 18
- 239000010409 thin film Substances 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 238000000605 extraction Methods 0.000 description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 7
- 230000001133 acceleration Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
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- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 101000945093 Homo sapiens Ribosomal protein S6 kinase alpha-4 Proteins 0.000 description 1
- 101000945096 Homo sapiens Ribosomal protein S6 kinase alpha-5 Proteins 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
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- 102100033645 Ribosomal protein S6 kinase alpha-5 Human genes 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Description
前記ゲートに覆われていない半導体膜のN型不純物がドープされた領域をソース及びドレインとするN型のTFTと、前記ゲートに覆われていない半導体膜のP型不純物がドープされた領域をソース及びドレインとするP型のTFTが形成されているとともに、
前記半導体膜と同層の半導体膜にN型不純物がドープされた領域を下部容量電極とし、金属膜からなる上部容量電極との間に前記ゲート絶縁膜と同層の絶縁膜を介在させた容量が形成されたTFT基板の製造方法であって、
第1のマスクを透明な領域と不透明な領域と半透明な領域を有するハーフトーンマスクとし、第2のマスクを透明な領域と不透明な領域を有するマスクとして、
第1と第2のマスクを用いて前記N型及びP型のTFTのゲート及び上部容量電極を加工し、
N型TFTのチャネルと、N型TFTのソース及びドレインと、P型TFTのチャネルと、P型TFTのソース及びドレインと、下部容量電極となる領域の半導体膜の不純物濃度を前記第1のマスクと第2のマスクのパターンにより作り分ける工程を含み、
N型TFTのチャネルとN型TFTのソース及びドレインとの境界、及びP型TFTのチャネルとP型TFTのソース及びドレインとの境界が全て、前記ハーフトーンマスクの不透明領域と半透明領域及び不透明領域と透明領域の境界以外で定義されていることを特徴とする。
図1は、本発明による第1の実施例の製造方法に用いられるマスクパターンとそれによって得られるTFT基板の構成を示す図である。
図6は、本発明による第2の実施例の製造方法に用いられるマスクパターンとそれによって得られるTFT基板の構成を示す図である。また、図7はTFT基板上の部材の各領域とマスクパターンとの対応関係を示した表である。
図11は、本発明による第3の実施例の製造方法に用いられるマスクパターンとそれによって得られるTFT基板の構成を示す図である。また、図12はTFT基板上の部材の各領域とマスクパターンの対応関係を示した表である。
図15は、本発明による第3の実施例の製造方法に用いられるマスクパターンとそれによって得られるTFT基板の構成を示す図である。また、図16はTFT基板上の部材の各領域とマスクパターンの対応関係を示した表である。
Claims (1)
- 絶縁基板上に形成された半導体膜と、前記半導体膜上に積層されたゲート絶縁膜と、前記ゲート絶縁膜上に形成された金属膜からなるゲートを有し、前記ゲートに覆われた領域の前記半導体膜をチャネルとするTFTであって、
前記ゲートに覆われていない半導体膜のN型不純物がドープされた領域をソース及びドレインとするN型のTFTと、前記ゲートに覆われていない半導体膜のP型不純物がドープされた領域をソース及びドレインとするP型のTFTが形成されているとともに、
前記半導体膜と同層の半導体膜にN型不純物がドープされた領域を下部容量電極とし、金属膜からなる上部容量電極との間に前記ゲート絶縁膜と同層の絶縁膜を介在させた容量が形成されたTFT基板の製造方法であって、
第1のマスクを透明な領域と不透明な領域と半透明な領域を有するハーフトーンマスクとし、第2のマスクを透明な領域と不透明な領域を有するマスクとして、
第1と第2のマスクを用いて前記N型及びP型のTFTのゲート及び上部容量電極を加工し、
N型TFTのチャネルと、N型TFTのソース及びドレインと、P型TFTのチャネルと、P型TFTのソース及びドレインと、下部容量電極となる領域の半導体膜の不純物濃度を前記第1のマスクと第2のマスクのパターンにより作り分ける工程を含み、
N型TFTのチャネルとN型TFTのソース及びドレインとの境界、及びP型TFTのチャネルとP型TFTのソース及びドレインとの境界が全て、前記ハーフトーンマスクの不透明領域と半透明領域及び不透明領域と透明領域の境界以外で定義されていることを特徴とするTFT基板の製造方法。
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JP2007272088A JP5292591B2 (ja) | 2007-10-19 | 2007-10-19 | Tft基板の製造方法 |
US12/251,486 US8101472B2 (en) | 2007-10-19 | 2008-10-15 | Method for manufacturing TFT substrate |
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JP2007272088A JP5292591B2 (ja) | 2007-10-19 | 2007-10-19 | Tft基板の製造方法 |
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KR101048987B1 (ko) * | 2009-12-10 | 2011-07-12 | 삼성모바일디스플레이주식회사 | 평판 표시 장치 및 그의 제조 방법 |
KR101210146B1 (ko) | 2010-04-05 | 2012-12-07 | 삼성디스플레이 주식회사 | 표시 장치 및 그의 제조 방법 |
KR101193197B1 (ko) * | 2010-07-07 | 2012-10-19 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치 및 이의 제조 방법 |
KR101889748B1 (ko) * | 2011-01-10 | 2018-08-21 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치 및 이의 제조 방법 |
KR101876819B1 (ko) * | 2011-02-01 | 2018-08-10 | 삼성디스플레이 주식회사 | 박막트랜지스터 기판 및 그의 제조방법 |
JP5807352B2 (ja) * | 2011-03-18 | 2015-11-10 | セイコーエプソン株式会社 | 半導体装置の製造方法、及び電気光学装置の製造方法 |
US20140051238A1 (en) * | 2011-05-09 | 2014-02-20 | Sharp Kabushiki Kaisha | Method for producing semiconductor device |
CN104124206A (zh) | 2013-04-23 | 2014-10-29 | 上海和辉光电有限公司 | Ltps阵列基板的制造方法 |
JP2016171104A (ja) | 2015-03-11 | 2016-09-23 | 株式会社ジャパンディスプレイ | 半導体装置の製造方法 |
CN105489552B (zh) * | 2016-01-28 | 2018-08-14 | 武汉华星光电技术有限公司 | Ltps阵列基板的制作方法 |
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JPH1096956A (ja) * | 1996-09-24 | 1998-04-14 | Toshiba Corp | 液晶表示装置及びその製造方法 |
JP2001094108A (ja) * | 1999-09-22 | 2001-04-06 | Toshiba Corp | 電界効果トランジスタ、トランジスタアレイ基板、およびその製造方法 |
JP3481902B2 (ja) * | 2000-05-30 | 2003-12-22 | 株式会社東芝 | Tftアレイの製造方法 |
JP4171179B2 (ja) | 2001-01-22 | 2008-10-22 | 三洋電機株式会社 | 光電変換素子 |
JP2002217419A (ja) * | 2001-01-23 | 2002-08-02 | Hitachi Ltd | 薄膜トランジスタ基板とその製法 |
US7524593B2 (en) * | 2005-08-12 | 2009-04-28 | Semiconductor Energy Laboratory Co., Ltd. | Exposure mask |
JP4850616B2 (ja) | 2005-08-12 | 2012-01-11 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
TWI303888B (en) * | 2006-07-21 | 2008-12-01 | Au Optronics Corp | Ltps-lcd structure and method for manufacturing the same |
JP5005302B2 (ja) * | 2006-09-19 | 2012-08-22 | 株式会社ジャパンディスプレイイースト | 表示装置の製造方法 |
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