JP5250929B2 - Transistor and manufacturing method thereof - Google Patents
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本発明は、酸化物半導体を用いたトランジスタおよびその製造方法に関する。 The present invention relates to a transistor using an oxide semiconductor and a manufacturing method thereof.
一般に、電子デバイスの駆動用トランジスタとして、アモルファスシリコンや多結晶シリコン等を用いた薄膜トランジスタが用いられてきた。しかしながら、高品質なアモルファスシリコンや多結晶シリコンは、成膜に２００℃以上の温度を必要とするため、フレキシブルなポリマーフィルムを基材として用いて、フレキシブルデバイスを実現することは困難であった。
また近年、有機半導体材料を用いた薄膜トランジスタが盛んに研究されている。有機半導体材料は、真空プロセスを用いず、例えば、印刷プロセスで作成できるため、低温でトランジスタの製造の可能性があり、可撓性のプラスチック基材上に設けられる等の利点を有する。
しかしながら、有機半導体材料は、移動度が極めて低く、また経時劣化にも弱いという難点があり、未だ広範な使用、実用に至っていない。
In general, a thin film transistor using amorphous silicon, polycrystalline silicon, or the like has been used as a transistor for driving an electronic device. However, since high-quality amorphous silicon and polycrystalline silicon require a temperature of 200 ° C. or higher for film formation, it has been difficult to realize a flexible device using a flexible polymer film as a base material.
In recent years, thin film transistors using organic semiconductor materials have been actively studied. The organic semiconductor material can be produced by, for example, a printing process without using a vacuum process. Therefore, the organic semiconductor material can be manufactured at a low temperature, and has an advantage that it is provided on a flexible plastic substrate.
However, organic semiconductor materials have a drawback that they have extremely low mobility and are weak against deterioration over time, and have not yet been used widely and practically.
以上のような状況を踏まえて、透明酸化物半導体を用いたデバイスの開発が行われている。透明酸化物は、低温で作成可能で、しかも高い移動度を示す特性を有しているので、例えば、基材、電極、絶縁膜等に透明材料を用いれば透明なデバイスを実現できる等、従来の材料になかった特性を持つ。前記透明酸化物半導体として、例えば、非晶質In-Ga-Zn-O材料を用いた電界効果型トランジスタが提案されている（非特許文献１参照）。
上記非特許文献１に記載の材料を用いたアモルファス酸化物半導体を半導体活性層として用いることで、室温でPET基板上に移動度が１０cm2/Vs前後の優れた特性を持つ透明電界効果型トランジスタの作成に成功している。
A transparent field effect transistor having excellent characteristics with a mobility of around 10 cm 2 / Vs on a PET substrate at room temperature by using an amorphous oxide semiconductor using the material described in Non-Patent Document 1 as a semiconductor active layer Has been successfully created.
前記酸化物半導体は、低温で形成することができるので、各種基板を用いたトランジスタが得られる可能性が高まった。
しかしながら、本発明は、酸化物半導体をチャネル層に用いると、チャネル層とソース電極、ドレイン電極間の接触抵抗が大きくなり、良好なトランジスタが得られない恐れがあった。
また、前記チャネル層にドレイン集中が生じやすく同様に良好なトランジスタが得られない恐れがあった。
Since the oxide semiconductor can be formed at a low temperature, there is an increased possibility that a transistor using various substrates is obtained.
However, in the present invention, when an oxide semiconductor is used for the channel layer, the contact resistance between the channel layer, the source electrode, and the drain electrode is increased, and a good transistor may not be obtained.
In addition, drain concentration tends to occur in the channel layer, and there is a risk that a good transistor cannot be obtained.
本発明は、酸化物半導体をチャネル層に用いると、チャネル層とソース電極、ドレイン電極間の接触抵抗が大きくなる課題、また、前記チャネル層にドレイン集中が生じやすくなる課題を解決し、酸化物半導体をチャネル層とした良好なトランジスタおよびその製造方法を提供することを目的とする。 The present invention solves the problem that, when an oxide semiconductor is used for a channel layer, the contact resistance between the channel layer, the source electrode, and the drain electrode increases, and the problem that drain concentration easily occurs in the channel layer. An object is to provide a good transistor using a semiconductor as a channel layer and a method for manufacturing the transistor.
請求項１に記載の発明は、基材上に設けられたゲート電極と、該ゲート電極上に、ゲート絶縁層、酸化物半導体からなるチャネル層、およびソース電極とドレイン電極を順次備えた半導体装置において、前記チャネル層とソース電極とドレイン電極の間に、前記チャネル層より導電率が高い介在層を設け、前記チャネル層および介在層が、同一組成で、組成比が異なる酸化物半導体であるＩｎＧａＺｎＯからなり、前記チャネル層の導電率σ１が、１０ −９ ≦σ１≦１０ −３ Ｓ／ｃｍ、介在層の導電率σ２が、１０ −３ ＜σ１≦１０ ３ Ｓ／ｃｍの範囲とし、前記ゲート絶縁層が、チャネル層より導電率が小さい酸化物半導体から構成され、前記ゲート絶縁膜が、前記チャネル層および介在層と、同一組成で、組成比が異なる酸化物半導体であることを特徴とするトランジスタである。 The invention according to claim 1 is a semiconductor device comprising a gate electrode provided on a base material, a gate insulating layer, a channel layer made of an oxide semiconductor, and a source electrode and a drain electrode sequentially on the gate electrode. In the structure, an intervening layer having higher conductivity than the channel layer is provided between the channel layer, the source electrode, and the drain electrode, and the channel layer and the intervening layer are oxide semiconductors having the same composition and different composition ratios. Tona is, the conductivity .sigma.1 of the channel layer, 10 -9 ≦ σ1 ≦ 10 -3 S / cm, the conductivity σ2 of the intervening layer, in the range of 10 -3 <σ1 ≦ 10 3 S / cm, the The gate insulating layer is made of an oxide semiconductor having a conductivity lower than that of the channel layer, and the gate insulating film is made of an oxide semiconductor having the same composition and a different composition ratio as the channel layer and the intervening layer. It is a transistor characterized by being.
請求項２記載の発明は、前記ゲート絶縁膜の導電率σ３が、１０−１４≦σ３＜１０−９ Ｓ／ｃｍの範囲であることを特徴とする請求項１記載のトランジスタである。 According to a second aspect of the invention, the gate insulating film conductivity .sigma.3 is a transistor according to claim 1, wherein in the range of 10 -14 ≦ σ3 <10 -9 S / cm.
請求項３記載の発明は、前記基材が、プラスチック基材であることを特徴とする請求項１または２記載のトランジスタである。 Third aspect of the present invention, wherein the substrate is a transistor according to claim 1 or 2, wherein the a plastic base material.
請求項４に記載の発明は、
基材上にゲート電極を設ける工程と、
該ゲート電極上に、ゲート絶縁層、酸化物半導体からなるチャネル層を設ける工程と、
前記チャネル層上に、前記チャネル層の導電率よりも高い導電率を有する酸化物半導体からなる介在層を設ける工程と、
前記介在層上に、ソース電極とドレイン電極を形成するための電極層を形成する工程と、
前記ソース電極と前記ドレイン電極を形成する工程と、
を有し、
前記チャネル層および介在層が、同一組成で、組成比が異なる酸化物半導体であるＩｎＧａＺｎＯからなり、前記チャネル層の導電率σ１が、１０ −９ ≦σ１≦１０ −３ Ｓ／ｃｍ、介在層の導電率σ２が、１０ −３ ＜σ１≦１０ ３ Ｓ／ｃｍの範囲とし、前記ゲート絶縁層が、チャネル層より導電率が小さい酸化物半導体から構成され、前記ゲート絶縁膜が、前記チャネル層および介在層と、同一組成で、組成比が異なる酸化物半導体であることを特徴とするトランジスタの製造方法である。
The invention according to claim 4
Providing a gate electrode on a substrate;
Providing a gate insulating layer and a channel layer made of an oxide semiconductor on the gate electrode;
Providing an intervening layer made of an oxide semiconductor having a conductivity higher than that of the channel layer on the channel layer;
Forming an electrode layer for forming a source electrode and a drain electrode on the intervening layer;
Forming the source electrode and the drain electrode;
Have
The channel layer and intermediate layer is the same composition, Ri InGaZnO composition ratio are different oxide semiconductor Tona, conductivity .sigma.1 of the channel layer, 10 -9 ≦ σ1 ≦ 10 -3 S / cm, intervening layer And the gate insulating layer is made of an oxide semiconductor having a conductivity lower than that of the channel layer, and the gate insulating film is formed of the channel layer in the range of 10 −3 <σ 1 ≦ 10 3 S / cm. And an oxide semiconductor having the same composition and different composition ratio as the intervening layer .
請求項５に記載の発明は、
基材上にゲート電極を設ける工程と、
該ゲート電極上に、ゲート絶縁層、酸化物半導体からなるチャネル層を設ける工程と、
前記チャネル層上に、前記チャネル層の導電率よりも高い導電率を有する酸化物半導体からなる介在層を設ける工程と、
少なくとも前記チャネル層と介在層の周辺部をエッチング処理により、島状とする工程と、
前記介在層上に、ソース電極とドレイン電極を形成するための電極層を形成する工程と、
前記ソース電極と前記ドレイン電極を形成する工程と、
を有し、
前記チャネル層および介在層が、同一組成で、組成比が異なる酸化物半導体であるＩｎＧａＺｎＯからなり、前記チャネル層の導電率σ１が、１０ −９ ≦σ１≦１０ −３ Ｓ／ｃｍ、介在層の導電率σ２が、１０ −３ ＜σ１≦１０ ３ Ｓ／ｃｍの範囲とし、前記ゲート絶縁層が、チャネル層より導電率が小さい酸化物半導体から構成され、前記ゲート絶縁膜が、前記チャネル層および介在層と、同一組成で、組成比が異なる酸化物半導体であることを特徴とするトランジスタの製造方法である。
The invention described in claim 5
Providing a gate electrode on a substrate;
Providing a gate insulating layer and a channel layer made of an oxide semiconductor on the gate electrode;
Providing an intervening layer made of an oxide semiconductor having a conductivity higher than that of the channel layer on the channel layer;
A step of etching at least the periphery of the channel layer and the intervening layer into an island shape;
Forming an electrode layer for forming a source electrode and a drain electrode on the intervening layer;
Forming the source electrode and the drain electrode;
Have
The channel layer and intermediate layer is the same composition, Ri InGaZnO composition ratio are different oxide semiconductor Tona, conductivity .sigma.1 of the channel layer, 10 -9 ≦ σ1 ≦ 10 -3 S / cm, intervening layer And the gate insulating layer is made of an oxide semiconductor having a conductivity lower than that of the channel layer, and the gate insulating film is formed of the channel layer in the range of 10 −3 <σ 1 ≦ 10 3 S / cm. And an oxide semiconductor having the same composition and different composition ratio as the intervening layer .
請求項６に記載の発明は、前記チャネル層と介在層が、連続成膜法により形成することを特徴とする請求項４または５記載のトランジスタの製造方法である。 The invention according to claim 6 is the transistor manufacturing method according to claim 4 or 5 , wherein the channel layer and the intervening layer are formed by a continuous film forming method.
本発明は、以上の構成からなるので、チャネル層とソース電極、ドレイン電極間に前記チャネル層より低抵抗の介在層を設けることにより、ドレイン電界集中と接触抵抗の低減化を図ることができた。
また、ゲート絶縁層とチャネル層、介在層のうち、少なくとも二層を、組成が同じで、酸素以外の構成元素の組成比が異なる酸化物半導体を用いることで、複数層を連続成膜することができ、高スループット、かつ、界面汚染の抑制が可能となった。
Since the present invention is configured as described above, the drain electric field concentration and the contact resistance can be reduced by providing an intervening layer having a resistance lower than that of the channel layer between the channel layer and the source and drain electrodes. .
In addition, at least two of the gate insulating layer, the channel layer, and the intervening layer may be formed in succession by using oxide semiconductors having the same composition and different composition ratios of constituent elements other than oxygen. It was possible to suppress interface contamination with high throughput.
さらに、また、低温プロセスで、ゲート電極、ゲート絶縁膜、チャネル層、介在層およびソース電極とドレイン電極を形成することが可能となり、基材として、プラスチック基材を用いることが可能となった。 Furthermore, a gate electrode, a gate insulating film, a channel layer, an intervening layer, a source electrode and a drain electrode can be formed by a low temperature process, and a plastic substrate can be used as a substrate.
本発明のトランジスタの一例を図１に示す。
基材１上に設けられたゲート電極２と、該ゲート電極２上に、ゲート絶縁層３、酸化物半導体からなるチャネル層４、およびチャネル領域１０を有するソース電極８とドレイン電極９を順次備えた半導体装置において、前記チャネル層４とソース電極８とドレイン電極９の間に、チャネル領域１０を有し、かつ前記チャネル層４より導電率が高い介在層７を設けたことを特徴とするトランジスタである。
An example of the transistor of the present invention is shown in FIG.
A gate electrode 2 provided on the substrate 1, a gate insulating layer 3, a channel layer 4 made of an oxide semiconductor, and a source electrode 8 and a drain electrode 9 having a channel region 10 are sequentially provided on the gate electrode 2. In the semiconductor device, a transistor having a channel region 10 and a higher conductivity than the channel layer 4 is provided between the channel layer 4, the source electrode 8, and the drain electrode 9. It is.
ここで、前記基材１は、ガラス、プラスチック等の基材を使用することができ、特に、プラスチック基材を用いることで、フレキシブルなトランジスタの提供が可能となる。
また、ゲート電極２は、インジウム（In）、アルミニウム（Al）、金（Au）、銀（Ag）等の金属薄膜であってもよいし、酸化インジウム（In2O3）、酸化スズ（SnO2）、酸化亜鉛（ZnO）、酸化カドミウム（CdO）、酸化インジウムカドミウム（CdIn2O4）、酸化カドミウムスズ（Cd2SnO4）、酸化亜鉛スズ（Zn2SnO4）等の酸化物材料でもよい。
また、前記酸化物材料に不純物をドープしたものも好適に用いられる。例えば、In2O3にスズ（Sn）やモリブデン（Mo）、チタン（Ti）をドープしたもの、SnO2にアンチモン（Sb）やフッ素（F）をドープしたもの、ZnOにインジウム、アルミニウム、ガリウム（Ga）をドープしたものなどである。
Here, a substrate such as glass or plastic can be used as the substrate 1, and in particular, a flexible transistor can be provided by using a plastic substrate.
The gate electrode 2 may be a metal thin film such as indium (In), aluminum (Al), gold (Au), silver (Ag), indium oxide (In 2 O 3 ), tin oxide (SnO). 2 ), oxide materials such as zinc oxide (ZnO), cadmium oxide (CdO), indium cadmium oxide (CdIn 2 O 4 ), cadmium tin oxide (Cd 2 SnO 4 ), zinc tin oxide (Zn 2 SnO 4 ) Good.
Moreover, what doped the impurity to the said oxide material is used suitably. For example, In 2 O 3 doped with tin (Sn), molybdenum (Mo), titanium (Ti), SnO 2 doped with antimony (Sb) or fluorine (F), ZnO indium, aluminum, gallium For example, doped with (Ga).
また、ソース電極８およびドレイン電極９は、前記ゲート電極２と同じ材料、または異なる材料を用いてもよい。
また、前記それぞれの電極は、真空蒸着法、イオンプレーティング法、スパッタリング法、レーザーアブレーション法、プラズマCVD法、光CVD法、ホットワイヤーCVD法、または、導電性ペーストを用いてスクリーン印刷等の方法を用いて形成される。そして、それぞれの電極は、膜厚が１５ｎｍ以上とすること好ましい。
The source electrode 8 and the drain electrode 9 may be made of the same material as the gate electrode 2 or a different material.
In addition, each of the electrodes may be a vacuum deposition method, an ion plating method, a sputtering method, a laser ablation method, a plasma CVD method, a photo CVD method, a hot wire CVD method, or a method such as screen printing using a conductive paste. It is formed using. Each electrode preferably has a film thickness of 15 nm or more.
チャネル層４は、亜鉛、インジウム、スズ、タングステン、マグネシウム、ガリウムのうち一種類以上の元素を含む酸化物である、酸化亜鉛、酸化インジウム、酸化スズ、酸化タングステン、酸化亜鉛ガリウムインジウム等の酸化物半導体材料を用いることができるが、これらに限定されるものではない。
このチャネル層４に用いる酸化物半導体は、導電率σ１が、10-9≦σ１≦10-3 S/cmであるのが好ましい。
The channel layer 4 is an oxide containing one or more elements selected from zinc, indium, tin, tungsten, magnesium, gallium, and oxides such as zinc oxide, indium oxide, tin oxide, tungsten oxide, and zinc gallium indium oxide. Although a semiconductor material can be used, it is not limited to these.
The oxide semiconductor used for the channel layer 4 preferably has a conductivity σ1 of 10 −9 ≦ σ1 ≦ 10 −3 S / cm.
また、介在層７は、前記チャネル層４と同じ組成で、組成比の異なる酸化物半導体からなり、導電率が前記チャネル層４の導電率より高い酸化物半導体を用いる。
この介在層４に用いる酸化物半導体は、導電率σ２が、10-3<σ２≦103 S/cmの範囲であるのが好ましい。
The intervening layer 7 is made of an oxide semiconductor having the same composition as that of the channel layer 4 and having a different composition ratio, and an oxide semiconductor having a higher conductivity than that of the channel layer 4 is used.
The oxide semiconductor used for the intervening layer 4 preferably has a conductivity σ2 in the range of 10 −3 <σ2 ≦ 10 3 S / cm.
ゲート絶縁層３は、絶縁材料であれば特に限定されないが、無機酸化物および無機窒化物もしくは無機酸化-窒化物（オキシナイトライド）を用いるのが好ましい。
具体的には、酸化シリコン、窒化シリコン、酸化アルミニウム、酸化タンタル、酸化イットリウム、酸化ハフニウム、ハフニウムアルミネート、酸化ジルコニアなどのいずれかの単独、もしくは二種以上の混合系、または二層以上積層して使用できるが、これらに限定されるものではない。
特に、前記チャネル層４および介在層７と同じ組成で、組成比が異なる高抵抗の酸化物半導体を用いるのが好ましい。具体的には、ゲート絶縁膜は、導電率σ３が、10-14≦σ３ <10-9S/cmの範囲の酸化物半導体を用いるのが好ましい。
そして、ゲート絶縁層４は、真空蒸着法、イオンプレーティング法、スパッタリング法、レーザーアブレーション法、プラズマCVD（Chemical VaporDeposition）、光CVD法、ホットワイヤーCVD法、ゾルゲル法などの方法を用いて形成される。
絶縁層４は、厚さが４０ｎｍnm〜１μｍの範囲であることが望ましいが、これらに限定されるものではない。
The gate insulating layer 3 is not particularly limited as long as it is an insulating material, but it is preferable to use an inorganic oxide and an inorganic nitride or an inorganic oxide-nitride (oxynitride).
Specifically, any one of silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconia oxide, or a mixture of two or more kinds, or two or more layers are laminated. However, the present invention is not limited to these.
In particular, it is preferable to use a high-resistance oxide semiconductor having the same composition as the channel layer 4 and the intervening layer 7 but having a different composition ratio. Specifically, the gate insulating film is preferably formed using an oxide semiconductor having a conductivity σ3 in the range of 10 −14 ≦ σ3 <10 −9 S / cm.
The gate insulating layer 4 is formed using a method such as a vacuum vapor deposition method, an ion plating method, a sputtering method, a laser ablation method, a plasma CVD (Chemical Vapor Deposition), a photo CVD method, a hot wire CVD method, or a sol-gel method. The
The insulating layer 4 desirably has a thickness in the range of 40 nm nm to 1 μm, but is not limited thereto.
次に、本発明のトランジスタの製造方法を、図２を参照して説明する。
基材上にスパッタリング法等を用いゲート電極層を形成後、フォトリソグラフィーなど公知の手法でゲート電極２を形成する（図２（ａ）参照。
次に、前記ゲート電極上に、ゲート絶縁層３、酸化物半導体からなるチャネル層４を、スパッタリング法など公知の手法で設け、さらに介在層７を同様にスパッタリング法など公知の手法で設ける（図２（ｂ）参照）。
ここで、介在層７は、前記チャネル層の導電率よりも高い導電率を有する酸化物半導体を使用する。
次に、チャネル層４と介在層７をフォトリソグラフィーなどの手法で、周辺部を一括エッチングして、島状にとする（図２（ｃ）参照）。
このとき、ゲート絶縁層３も同様に周辺部を一括エッチングしての島状としてもよい。
Next, a method for manufacturing the transistor of the present invention will be described with reference to FIG.
After forming the gate electrode layer on the base material by sputtering or the like, the gate electrode 2 is formed by a known method such as photolithography (see FIG. 2A).
Next, a gate insulating layer 3 and a channel layer 4 made of an oxide semiconductor are provided on the gate electrode by a known method such as sputtering, and an intervening layer 7 is similarly provided by a known method such as sputtering (see FIG. 2 (b)).
Here, the intervening layer 7 uses an oxide semiconductor having a conductivity higher than that of the channel layer.
Next, the peripheral portion of the channel layer 4 and the intervening layer 7 is collectively etched into a island shape by a technique such as photolithography (see FIG. 2C).
At this time, the gate insulating layer 3 may be formed in an island shape by collectively etching the peripheral portion.
次に、前記介在層７上に、ソース電極８とドレイン電極９を形成するための電極層６を同様にスパッタリング法など公知の手法で形成する（図２（ｄ）参照）。
前記電極層６および介在層７にチャネル領域１０を形成することで、ソース電極８とドレイン電極９を形成され、トランジスタが完成する（図２（ｅ）参照）。
なお、電極層６および介在層７にチャネル領域１０の形成は、まず、電極層６を、フォトリソグラフィーなどの手法で、ソース電極８とドレイン電極９を形成した後、このソース電極８とドレイン電極９をマスクとして用い、介在層７にドレイン領域１０を形成する。
あるいは、電極層６および介在層７を、フォトリソグラフィーなどの手法で同時に処理し、ドレイン領域１０を形成する。
Next, the electrode layer 6 for forming the source electrode 8 and the drain electrode 9 is similarly formed on the intervening layer 7 by a known method such as a sputtering method (see FIG. 2D).
By forming the channel region 10 in the electrode layer 6 and the intervening layer 7, the source electrode 8 and the drain electrode 9 are formed, and the transistor is completed (see FIG. 2E).
The channel region 10 is formed in the electrode layer 6 and the intervening layer 7. First, after forming the source electrode 8 and the drain electrode 9 on the electrode layer 6 by a technique such as photolithography, the source electrode 8 and the drain electrode 9 are formed. A drain region 10 is formed in the intervening layer 7 using 9 as a mask.
Alternatively, the electrode layer 6 and the intervening layer 7 are simultaneously processed by a technique such as photolithography to form the drain region 10.
本発明の薄膜トランジスタは、液晶ディスプレー、有機ELディスプレー、光書き込み型コレステリック液晶型ディスプレー、Twisting Ball 方式ディスプレー、トナーディスプレー方式ディスプレー、可動フィルム方式ディスプレー、センサーなどのデバイスに使用することができる。 The thin film transistor of the present invention can be used in devices such as a liquid crystal display, an organic EL display, a light writing type cholesteric liquid crystal display, a twisting ball type display, a toner display type display, a movable film type display, and a sensor.
まず、ＰＥＴからなる基板１上に、スパッタリング法でアルミニウム膜を製膜し、該アルミニウム膜を、フォトリソグラフィー法を用いてゲート電極２を形成する。
次に、スパッタリング法によりゲート絶縁層３と、チャネル層となる半導体層４と介在層７を連続成膜し、積層構成とする。
このとき、少なくともチャネル層４および介在層７を構成する酸化物半導体５は、InGaZnOで構成され、チャネル層４形成と介在層７形成時で、スパッタリングのガス雰囲気を、チャネル層４形成時の酸素流量比が２％、介在層７形成時の酸素流量比が０％とすることで、チャネル層４の導電率が1×10-4 S/cm、介在層７の導電率がσ×100S/cmであった。
そして、チャネル層となる半導体層４と介在層７を、フォトリソグラフィー法で一括エッチングしてトランジスタを形成する領域を島状とした。
次に、アルミニウムをターゲットとし、スパッタリング法で、ソース電極、ドレイン電極となる電極層６を製膜した。
前記電極層６をフォトリソグラフィー法で、ソース電極８とドレイン電極９を形成した。
そして、ソース電極８とドレイン電極９間の介在層９を、エッチングしてトランジスタのチャネル領域１０を形成した。
以上の工程を経て、プラスチック基板上に設置されたゲート電極と、ゲート絶縁層と島状のチャネル層と介在層が積層され設けられたトランジスタを得ることができた。
また、介在層の上には、ソース電極とドレイン電極が形成され、ソース電極とドレイン電極の間にはチャネル領域が形成された構成とすることができた。
First, an aluminum film is formed on a substrate 1 made of PET by a sputtering method, and a gate electrode 2 is formed from the aluminum film by using a photolithography method.
Next, the gate insulating layer 3, the semiconductor layer 4 serving as a channel layer, and the intervening layer 7 are continuously formed by sputtering to form a stacked structure.
At this time, the oxide semiconductor 5 constituting at least the channel layer 4 and the intervening layer 7 is composed of InGaZnO, and when the channel layer 4 and the intervening layer 7 are formed, the sputtering gas atmosphere is changed to oxygen during the formation of the channel layer 4. By setting the flow rate ratio to 2% and the oxygen flow rate ratio when forming the intervening layer 7 to 0%, the conductivity of the channel layer 4 is 1 × 10 −4 S / cm, and the conductivity of the intervening layer 7 is σ × 10 0. S / cm.
Then, the semiconductor layer 4 and the intervening layer 7 to be the channel layer are collectively etched by a photolithography method to form an island shape in a region where a transistor is formed.
Next, an electrode layer 6 to be a source electrode and a drain electrode was formed by sputtering using aluminum as a target.
A source electrode 8 and a drain electrode 9 were formed on the electrode layer 6 by photolithography.
Then, the intervening layer 9 between the source electrode 8 and the drain electrode 9 was etched to form a channel region 10 of the transistor.
Through the above steps, a transistor in which a gate electrode provided on a plastic substrate, a gate insulating layer, an island-shaped channel layer, and an intervening layer are stacked can be obtained.
In addition, a source electrode and a drain electrode were formed on the intervening layer, and a channel region was formed between the source electrode and the drain electrode.
１・・・基材
２・・・ゲート電極
３・・・ゲート絶縁層
４・・・チャネル層
６・・・電極層
７・・・介在層
８・・・ソース電極
９・・・ドレイン電極
１０・・・ドレイン領域
DESCRIPTION OF SYMBOLS 1 ... Base material 2 ... Gate electrode 3 ... Gate insulating layer 4 ... Channel layer 6 ... Electrode layer 7 ... Interposition layer 8 ... Source electrode 9 ... Drain electrode 10 ... Drain region
Claims (6)
該ゲート電極上に、ゲート絶縁層、酸化物半導体からなるチャネル層を設ける工程と、
前記チャネル層上に、前記チャネル層の導電率よりも高い導電率を有する酸化物半導体からなる介在層を設ける工程と、
前記介在層上に、ソース電極とドレイン電極を形成するための電極層を形成する工程と、
前記ソース電極と前記ドレイン電極を形成する工程と、
を有し、
前記チャネル層および介在層が、同一組成で、組成比が異なる酸化物半導体であるＩｎＧａＺｎＯからなり、前記チャネル層の導電率σ１が、１０ −９ ≦σ１≦１０ −３ Ｓ／ｃｍ、介在層の導電率σ２が、１０ −３ ＜σ１≦１０ ３ Ｓ／ｃｍの範囲とし、前記ゲート絶縁層が、チャネル層より導電率が小さい酸化物半導体から構成され、前記ゲート絶縁膜が、前記チャネル層および介在層と、同一組成で、組成比が異なる酸化物半導体であることを特徴とするトランジスタの製造方法。 Providing a gate electrode on a substrate;
Providing a gate insulating layer and a channel layer made of an oxide semiconductor on the gate electrode;
Providing an intervening layer made of an oxide semiconductor having a conductivity higher than that of the channel layer on the channel layer;
Forming an electrode layer for forming a source electrode and a drain electrode on the intervening layer;
Forming the source electrode and the drain electrode;
Have
The channel layer and intermediate layer is the same composition, Ri InGaZnO composition ratio are different oxide semiconductor Tona, conductivity .sigma.1 of the channel layer, 10 -9 ≦ σ1 ≦ 10 -3 S / cm, intervening layer And the gate insulating layer is made of an oxide semiconductor having a conductivity lower than that of the channel layer, and the gate insulating film is formed of the channel layer in the range of 10 −3 <σ 1 ≦ 10 3 S / cm. And a method for manufacturing a transistor, which is an oxide semiconductor having the same composition and different composition ratio as the intervening layer .
該ゲート電極上に、ゲート絶縁層、酸化物半導体からなるチャネル層を設ける工程と、
前記チャネル層上に、前記チャネル層の導電率よりも高い導電率を有する酸化物半導体からなる介在層を設ける工程と、
少なくとも前記チャネル層と介在層の周辺部をエッチング処理により、島状とする工程と、
前記介在層上に、ソース電極とドレイン電極を形成するための電極層を形成する工程と、
前記ソース電極と前記ドレイン電極を形成する工程と、
を有し、
前記チャネル層および介在層が、同一組成で、組成比が異なる酸化物半導体であるＩｎＧａＺｎＯからなり、前記チャネル層の導電率σ１が、１０ −９ ≦σ１≦１０ −３ Ｓ／ｃｍ、介在層の導電率σ２が、１０ −３ ＜σ１≦１０ ３ Ｓ／ｃｍの範囲とし、前記ゲート絶縁層が、チャネル層より導電率が小さい酸化物半導体から構成され、前記ゲート絶縁膜が、前記チャネル層および介在層と、同一組成で、組成比が異なる酸化物半導体であることを特徴とするトランジスタの製造方法。 Providing a gate electrode on a substrate;
Providing a gate insulating layer and a channel layer made of an oxide semiconductor on the gate electrode;
Providing an intervening layer made of an oxide semiconductor having a conductivity higher than that of the channel layer on the channel layer;
A step of etching at least the periphery of the channel layer and the intervening layer into an island shape;
Forming an electrode layer for forming a source electrode and a drain electrode on the intervening layer;
Forming the source electrode and the drain electrode;
Have
The channel layer and intermediate layer is the same composition, Ri InGaZnO composition ratio are different oxide semiconductor Tona, conductivity .sigma.1 of the channel layer, 10 -9 ≦ σ1 ≦ 10 -3 S / cm, intervening layer And the gate insulating layer is made of an oxide semiconductor having a conductivity lower than that of the channel layer, and the gate insulating film is formed of the channel layer in the range of 10 −3 <σ 1 ≦ 10 3 S / cm. And a method for manufacturing a transistor, which is an oxide semiconductor having the same composition and different composition ratio as the intervening layer .
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