JP5220749B2 - デュアル応力ライナ技術におけるデバイス性能の変動を改善するための方法及び構造体 - Google Patents
デュアル応力ライナ技術におけるデバイス性能の変動を改善するための方法及び構造体 Download PDFInfo
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Description
少なくとも1つの活性ゲート領域に近接した少なくとも1つのダミー・ゲート領域を有する半導体基板と、
基板上に位置する引張応力ライナ及び圧縮応力ライナを含む半導体構造体であって、引張応力ライナ及び圧縮応力ライナは、応力ライナ間存在する境界又はギャップが少なくとも1つのダミー・ゲート領域の上部にあるように、少なくとも1つのダミー・ゲート領域上に部分的に存在する、半導体構造体を提供する。
少なくとも1つのpFETに近接した少なくとも1つのダミー・ゲート領域を有する半導体基板と、
基板上に位置する引張応力ライナ及び圧縮応力ライナを含み、圧縮応力ライナは、応力ライナ間に存在する境界又はギャップが少なくとも1つのダミー・ゲート領域の上部に置かれるように、少なくとも1つのpFETを覆い、且つ少なくとも1つのダミー・ゲート領域上に部分的に存在する。
少なくとも1つのnFETに近接した少なくとも1つのダミー・ゲート領域を有する半導体基板と、
基板上に位置する引張応力ライナ及び圧縮応力ライナを含み、引張応力ライナは、応力ライナ間に存在する境界又はギャップが少なくとも1つのダミー・ゲート領域の上部に置かれるように、少なくとも1つのnFETを覆い、且つ少なくとも1つのダミー・ゲート領域上に部分的に存在する。
少なくとも1つの活性ゲート領域に近接した少なくとも1つのダミー・ゲート領域を有する半導体基板を提供するステップと、
基板上に引張応力ライナ及び圧縮応力ライナを任意の順序で配置するステップとを含み、引張応力ライナ及び圧縮応力ライナは、応力ライナ間の境界又はギャップが少なくとも1つのダミー・ゲート領域の上部に置かれるように、少なくとも1つのダミー・ゲート領域上に部分的に存在する。
14:ダミー・ゲート領域
16:活性ゲート領域
20:ゲート電極
30:第1応力ライナ
32:第2応力ライナ
34:重なり部
36:デュアル応力ライナ境界
50:分離領域
Claims (21)
- 半導体構造体であって、
少なくとも1つの活性ゲート領域と、当該少なくとも1つの活性ゲート領域に近接した少なくとも1つのダミー・ゲート領域とを有する半導体基板であって、前記活性ゲート領域にはそのゲート電極上に酸化物又は窒化物からなるキャッピング層が配置されており、且つ、前記ダミー・ゲート領域にはそのゲート電極上に酸化物又は窒化物からなるキャッピング層が配置されている、前記半導体基板と、
前記半導体基板上に配置された引張応力ライナ及び圧縮応力ライナであって、前記引張応力ライナ及び圧縮応力ライナ間に存在する境界又はギャップが前記少なくとも1つのダミー・ゲート領域の上部に置かれるように、前記引張応力ライナ及び圧縮応力ライナが前記少なくとも1つのダミー・ゲート領域上に部分的に存在する、前記引張応力ライナ及び圧縮応力ライナと
を備えている、前記半導体構造体。 - 前記半導体基板が単一の結晶方位を有するSi含有基板を含む、請求項1に記載の半導体構造体。
- 前記半導体基板が異なる結晶方位の表面領域を含むハイブリッド基板である、請求項1又は2に記載の半導体構造体。
- 前記圧縮応力ライナが前記少なくとも1つの活性ゲート領域を覆い、且つ前記ダミー・ゲート領域上の引張応力ライナのセグメントの上に重なる、請求項1〜3のいずれか一項に記載の半導体構造体。
- 前記少なくとも1つの活性ゲート領域がpFETである、請求項4に記載の半導体構造体。
- 前記引張応力ライナが前記少なくとも1つの活性ゲート領域を覆い、且つ前記ダミー・ゲート領域上の圧縮応力ライナのセグメントの上に重なる、請求項1〜3のいずれか一項に記載の半導体構造体。
- 前記少なくとも1つの活性ゲート領域がnFETである、請求項6に記載の半導体構造体。
- 前記引張応力ライナ及び圧縮応力ライナが前記ダミー・ゲート領域の上で互いに当接し、又はそれらの間にスペースが存在する、請求項1〜7のいずれか一項に記載の半導体構造体。
- 前記ダミー・ゲート領域が、前記半導体基板内又は基板上に配置された分離領域の上に位置する、請求項1〜8のいずれか一項に記載の半導体構造体。
- 半導体構造体であって、
活性ゲート領域である少なくとも1つのpFETと、当該少なくとも1つのpFETに近接した少なくとも1つのダミー・ゲート領域を有する半導体基板であって、前記活性ゲート領域にはそのゲート電極上に酸化物又は窒化物からなるキャッピング層が配置されており、且つ、前記ダミー・ゲート領域にはそのゲート電極上に酸化物又は窒化物からなるキャッピング層が配置されている、前記半導体基板と、
前記半導体基板上に配置された引張応力ライナ及び圧縮応力ライナであって、前記引張応力ライナ及び圧縮応力ライナ間に存在する境界又はギャップが前記少なくとも1つのダミー・ゲート領域の上部に置かれるように、前記圧縮応力ライナが、前記少なくとも1つのpFETを覆い、且つ前記少なくとも1つのダミー・ゲート領域上に部分的に存在する、前記引張応力ライナ及び圧縮応力ライナと
を備えている、前記半導体構造体。 - 前記引張応力ライナ及び圧縮応力ライナが前記ダミー・ゲート領域の上で互いに重なる、請求項10に記載の半導体構造体。
- 前記引張応力ライナ及び圧縮応力ライナが前記ダミー・ゲート領域の上で互いに当接し、又は前記ダミー・ゲート領域の上の2つの応力ライナ間にスペースが位置する、請求項10に記載の半導体構造体。
- 前記ダミー・ゲート領域が、前記半導体基板内又は基板上に配置された分離領域の上に位置する、請求項10〜12のいずれか一項のいずれかに記載の半導体構造体。
- 半導体構造体であって、
活性ゲート領域である少なくとも1つのnFETと、当該少なくとも1つのnFETに近接した少なくとも1つのダミー・ゲート領域とを有する半導体基板であって、前記活性ゲート領域にはそのゲート電極上に酸化物又は窒化物からなるキャッピング層が配置されており、且つ、前記ダミー・ゲート領域にはそのゲート電極上に酸化物又は窒化物からなるキャッピング層が配置されている、前記半導体基板と、
前記半導体基板上に配置された引張応力ライナ及び圧縮応力ライナであって、前記引張応力ライナ及び圧縮応力ライナ間に存在する境界又はギャップが前記少なくとも1つのダミー・ゲート領域の上部に置かれるように、前記引張応力ライナが、前記少なくとも1つのnFETを覆い、且つ前記少なくとも1つのダミー・ゲート領域上に部分的に存在する、前記引張応力ライナ及び圧縮応力ライナと
を備えている、前記半導体構造体。 - 半導体構造体であって、
活性ゲート領域である少なくとも1つのFETと、当該少なくとも1つのFETに近接した少なくとも1つのダミー・ゲート領域とを有する半導体基板であって、前記活性ゲート領域にはそのゲート電極上に酸化物又は窒化物からなるキャッピング層が配置されており、且つ、前記ダミー・ゲート領域にはそのゲート電極上に酸化物又は窒化物からなるキャッピング層が配置されている、前記半導体基板と、
前記半導体基板上に配置された引張応力ライナ及び圧縮応力ライナであって、前記引張応力ライナ及び圧縮応力ライナのエッチングされた縁部が前記少なくとも1つのダミー・ゲート領域の上に置かれるように、前記引張応力ライナ及び圧縮応力ライナが、前記少なくとも1つのFETを覆い、且つ前記少なくとも1つのダミー・ゲート領域上に部分的に存在する、前記引張応力ライナ及び圧縮応力ライナと
を備えている、前記半導体構造体。 - 半導体構造体の製造方法であって、
少なくとも1つの活性ゲート領域と当該少なくとも1つの活性ゲート領域に近接した少なくとも1つのダミー・ゲート領域とを有する半導体基板上に、引張応力ライナ及び圧縮応力ライナを任意の順序で配置するステップ
を含み、
前記活性ゲート領域にはそのゲート電極上に酸化物又は窒化物からなるキャッピング層が配置されており、且つ、前記ダミー・ゲート領域にはそのゲート電極上に酸化物又は窒化物からなるキャッピング層が配置されており、
前記引張応力ライナ及び圧縮応力ライナ間に存在する境界又はギャップが前記少なくとも1つのダミー・ゲート領域の上部に置かれるように、前記引張応力ライナ及び圧縮応力ライナが前記少なくとも1つのダミー・ゲート領域上に部分的に存在する、
前記方法。 - 最初に前記引張応力ライナが配置され、次に前記圧縮応力ライナが配置され、それにより、前記圧縮応力ライナが前記少なくとも1つの活性ゲート領域を覆い、且つ前記ダミー・ゲート領域の上の前記引張応力ライナのセグメントの上に重なる、請求項16に記載の方法。
- 最初に前記圧縮応力ライナが配置され、次に前記引張応力ライナが配置され、それにより、前記引張応力ライナが前記少なくとも1つの活性ゲート領域を覆い、且つ前記ダミー・ゲート領域の上の前記圧縮応力ライナのセグメントの上に重なる、請求項16に記載の方法。
- 前記半導体基板が、異なる結晶方位の表面領域を含むハイブリッド基板である、請求項16〜18のいずれか一項に記載の方法。
- 各々のダミー・ゲート領域が、下から上に向かって、ゲート誘電体とゲート電極とを含むスタックを含む、請求項16〜19のいずれか一項に記載の方法。
- 各々の活性ゲート領域が、下から上に向かってゲート誘電体とゲート電極とを含むスタックと、前記スタックと隣接ソース/ドレーン領域との間のチャネル領域とを含む、請求項16〜20のいずれか一項に記載の方法。
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US7843024B2 (en) | 2010-11-30 |
US7462522B2 (en) | 2008-12-09 |
WO2008025661A1 (en) | 2008-03-06 |
JP2010502026A (ja) | 2010-01-21 |
TW200830552A (en) | 2008-07-16 |
US20080057653A1 (en) | 2008-03-06 |
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