JP5181544B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP5181544B2
JP5181544B2 JP2007162821A JP2007162821A JP5181544B2 JP 5181544 B2 JP5181544 B2 JP 5181544B2 JP 2007162821 A JP2007162821 A JP 2007162821A JP 2007162821 A JP2007162821 A JP 2007162821A JP 5181544 B2 JP5181544 B2 JP 5181544B2
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active element
groove
substrate
conductive layer
semiconductor device
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JP2009004498A (en
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修 山形
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Sony Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

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Description

本発明は、半導体チップ等の能動素子を有する半導体装置の製造方法であり、特に、チップサイズパッケージとする半導体装置の製造方法に関する。 The present invention is a method of manufacturing a semiconductor device having an active element such as a semiconductor chip, in particular, it relates to a method of manufacturing a semiconductor device according to a chip size package.

ＣＣＤやＣＭＯＳ等の受光素子や発光素子を含む半導体チップ等の能動素子を備える半導体装置において、これを組み込むデジタルカメラやビデオカメラ、携帯電話等の電子機器の小型化の要求に伴って、更なる小型化が求められている。このため、能動素子上に再配線を行い、外部電極を形成してベアチップと同程度のパッケージングを行うチップサイズパッケージ（ＣＳＰ）とすることが提案されている。   In a semiconductor device including an active element such as a semiconductor chip including a light receiving element and a light emitting element such as a CCD and a CMOS, in accordance with a demand for miniaturization of electronic devices such as a digital camera, a video camera, and a mobile phone incorporating the same Miniaturization is required. For this reason, it has been proposed that a chip size package (CSP) in which rewiring is performed on an active element and an external electrode is formed to perform packaging similar to a bare chip.

このように半導体チップ等の能動素子上に再配線を行うにあたり、能動素子に受発光素子が含まれる場合は回路面を絶縁層で遮蔽できない。したがって、外部電極は回路面とは反対側に形成することが求められる。この場合は、例えば能動素子の電極を回路から取り出して能動素子の下部に配線を行う必要がある。   Thus, when performing rewiring on an active element such as a semiconductor chip, the circuit surface cannot be shielded by an insulating layer if the active element includes a light emitting / receiving element. Therefore, the external electrode is required to be formed on the side opposite to the circuit surface. In this case, for example, it is necessary to take out the electrode of the active element from the circuit and perform wiring under the active element.

能動素子の回路面と異なる面に電極を設ける方法としては、従来は、両面電極付の基板にワイヤーボンドで接続するか、能動素子そのものの側面をシリコン貫通して、貫通口いわゆるＶＩＡを形成する必要がある（例えば特許文献１及び２参照）。
特開２００６−３０３４８２号公報 特開２００６−７３８５２号公報 As a method of providing an electrode on a surface different from the circuit surface of the active element, conventionally, a through-hole so-called VIA is formed by connecting to a substrate with a double-sided electrode by wire bonding or penetrating the side surface of the active element itself with silicon. There is a need (see, for example, Patent Documents 1 and 2).
JP 2006-303482 A JP 2006-73852 A

しかしながら、ワイヤーボンドによる場合はワイヤーパスが必要であり、能動素子から２００μｍ程度離さなければならないため、チップサイズが大きくなってしまう。例えば上記特許文献１においては、スルーホール電極を有する有機基板を用いる構成が提案されているが、チップからワイヤーの接続を必要とし、チップサイズとすることは難しい。
また、下記の特許文献２においては、シリコン貫通孔を設ける構成が提案されているが、シリコン貫通を行う場合は、貫通用の特殊なレイアウトとする必要があり、チップサイズとすることができない。また特殊なプロセスを要し、工程数が増加するので、コストが高くなるという不都合を有する。 However, in the case of wire bonding, a wire pass is necessary, and the chip size becomes large because it must be separated from the active element by about 200 μm. For example, in the above-mentioned Patent Document 1, a configuration using an organic substrate having a through-hole electrode is proposed. However, it is difficult to obtain a chip size because a wire needs to be connected from the chip.
Further, in the following Patent Document 2, a configuration in which a silicon through hole is provided is proposed. However, when silicon penetration is performed, it is necessary to have a special layout for penetration, and the chip size cannot be achieved. Moreover, since a special process is required and the number of steps increases, there is a disadvantage that the cost increases.

以上の問題に鑑みて、本発明は、ワイヤー接続やシリコン貫通を行うことなく、能動素子の受光及び／又は発光が可能なチップサイズの半導体装置を製造することを目的とする。 In view of the above problems, an object of the present invention is to manufacture a chip-sized semiconductor device capable of receiving and / or emitting light from an active element without performing wire connection or silicon penetration.

上記課題を解決するため、本発明は、能動素子を有する基体の第１の面に溝を形成する工程と、溝内に導電層を形成して、能動素子の電極に接続する工程と、基体上に、光透過性基体を搭載する工程と、基体を、第１の面とは反対側の裏面側から溝の底部まで薄化して、基体の第１の面とは反対側の第２の面に溝の底部側の導電層の表面を露出する工程と、基体を反転させて、第２の面上に再配線を行って、第１及び第２の面に貫通する導電層より成る配線部を形成する工程と、第２の面側の配線部上に電極を形成する工程と、を有し、溝内に導電層を形成する工程において、溝内の中央部に絶縁層を形成し、溝の側面と中央部の絶縁層との間に導電層を形成する。 In order to solve the above problems, the present invention includes a step of forming a groove on a first surface of a substrate having an active element, a step of forming a conductive layer in the groove and connecting to an electrode of the active element, And a step of mounting the light-transmitting substrate, and the substrate is thinned from the back surface side opposite to the first surface to the bottom of the groove to form a second surface on the side opposite to the first surface of the substrate. A step of exposing the surface of the conductive layer on the bottom side of the groove on the surface, a wiring comprising a conductive layer penetrating the first and second surfaces by inverting the substrate and performing rewiring on the second surface Forming an electrode on the wiring portion on the second surface side, and forming a conductive layer in the groove, and forming an insulating layer in the central portion in the groove A conductive layer is formed between the side surface of the groove and the insulating layer at the center .

上述したように、本発明による半導体装置の製造方法においては、能動素子を有する基体の第１の面に溝を形成して、その側面に導電層を形成して能動素子の電極と接続し、基体上に光透過性基体を搭載し、一方基体の裏面側を薄化して、この溝内に形成した導電層を露出させ、薄化した裏面側に再配線を行って、第１及び第２の面に導通する導電層より成る配線部を形成して、この配線部に電極を形成するものである。 As described above, in the method of manufacturing a semiconductor device according to the present invention, a groove is formed on the first surface of the substrate having an active element, a conductive layer is formed on the side surface thereof, and connected to the electrode of the active element. A light-transmitting substrate is mounted on the substrate, while the back surface side of the substrate is thinned to expose the conductive layer formed in the groove, and rewiring is performed on the thinned back surface side. A wiring portion made of a conductive layer is formed on this surface, and an electrode is formed on this wiring portion .

本発明の半導体装置の製造方法によれば、ワイヤー接続やシリコン貫通を行うことなく、能動素子の受光及び／又は発光が可能なチップサイズの半導体装置を提供することができる。 According to the method for manufacturing a semiconductor device of the present invention, it is possible to provide a chip-sized semiconductor device capable of receiving and / or emitting light from an active element without performing wire connection or silicon penetration.

以下本発明を実施するための最良の形態の例を説明するが、本発明は以下の例に限定されるものではない。
図１〜図５の製造工程図を参照して、本発明の一実施の形態に係る半導体装置の製造方法について説明する。
先ず、図１Ａに示すように、能動素子ウエーハサイズと同じ封止用の石英ガラス基板より成る光透過性基体２０を用意する。
一方、図１Ｂに示すように、例えば能動素子ウエーハ型の基体１の第１の面１Ａ上に能動素子２が配置される。その他シリコンウエーハ基体上に能動素子が搭載された構成としてもよく、また基体１はシリコン等の半導体基板に限定されるものではない。図１Ｂにおいては能動素子２の電極３のみを示し、回路部や下地絶縁層等は図示を省略する。能動素子２の電極３と回路部（図示せず）は保護層４いわゆるパッシベーションで覆われる。能動素子２はチップサイズに応じて溝２Ｓいわゆるスクライブラインが形成され、溝２Ｓ内は保護膜４が除去される。本実施の形態に適用される能動素子２は、受光及び／又は発光素子や、受光及び／又は発光用のセンサー面等が回路上に形成してある。 Examples of the best mode for carrying out the present invention will be described below, but the present invention is not limited to the following examples.
A manufacturing method of a semiconductor device according to an embodiment of the present invention will be described with reference to the manufacturing process diagrams of FIGS.
First, as shown in FIG. 1A, a light-transmitting substrate 20 made of a quartz glass substrate for sealing that is the same as the active element wafer size is prepared.
On the other hand, as shown in FIG. 1B, for example, the active element 2 is disposed on the first surface 1A of the active element wafer-type substrate 1. In addition, the active element may be mounted on a silicon wafer substrate, and the substrate 1 is not limited to a semiconductor substrate such as silicon. In FIG. 1B, only the electrode 3 of the active element 2 is shown, and the circuit portion, the base insulating layer, and the like are not shown. The electrode 3 and the circuit part (not shown) of the active element 2 are covered with a protective layer 4 so-called passivation. In the active element 2, a groove 2 </ b> S so-called scribe line is formed according to the chip size, and the protective film 4 is removed in the groove 2 </ b> S. The active element 2 applied to the present embodiment has a light receiving and / or light emitting element, a light receiving and / or light emitting sensor surface, and the like formed on a circuit.

この溝２Ｓの幅いわゆるスクライブ幅は、能動素子２を形成する際のプロセスルールで規定されており、パッケージに内蔵するため薄化個片化を行うためのブレード幅で決定される。一般的には５０μｍ以上のダイシング幅が選択される。これは、ブレードダイシングによるチッピングいわゆる割れ、欠けが回路面に到達しないような幅で設計されるためである。つまりスクライブラインはダイシングのためのもので能動素子２の機能とは無関係である。この部分を上下の接続用に応用した構造が本発明の半導体装置となる。   The width of the groove 2S, the so-called scribe width, is defined by the process rule when forming the active element 2, and is determined by the blade width for thinning and dividing into a package. Generally, a dicing width of 50 μm or more is selected. This is because the chipping by blade dicing is so designed that cracks and chips do not reach the circuit surface. In other words, the scribe line is for dicing and is not related to the function of the active element 2. A structure in which this portion is applied for upper and lower connections is a semiconductor device of the present invention.

次に、図１Ｃに示すように、溝２ａをダイシングブレード等により掘り下げていわばハーフカットを行い、溝５を形成する。この溝５の底部５ｂまでの深さｄとしては、最終的に得る１層目の能動素子の厚さをｔとすると、ｔ＋１０μｍ程度の深さとする。
溝２ａすなわちスクライブラインの幅が２００μｍ程度の場合は、ダイシングストリート部に１５０μｍ幅のブレードで、高さ６０±５μｍ（最終厚さが５０μｍの場合）として、ダイシングを行なう。コンタミ等に注意が必要な半導体装置ではベベルカットいわゆる縁取りを行ってカットしてもよい。このとき溝加工の条件としては、例えば以下の条件とすることができる。
スピンドル回転数：約３０，０００ｒｐｍ
送り速度：５ｍｍ／ｓ以下 Next, as shown in FIG. 1C, if the groove 2 a is dug down with a dicing blade or the like, half-cut is performed to form the groove 5. The depth d to the bottom 5b of the groove 5 is about t + 10 μm, where t is the thickness of the first active element finally obtained.
When the width of the groove 2a, that is, the scribe line is about 200 μm, dicing is performed with a blade having a width of 150 μm in the dicing street portion to a height of 60 ± 5 μm (when final thickness is 50 μm). In a semiconductor device that requires attention to contamination or the like, it may be cut by bevel cutting or so-called edging. At this time, the conditions for grooving can be, for example, the following conditions.
Spindle speed: about 30,000 rpm
Feeding speed: 5mm / s or less

この溝加工を行なった能動素子ウエーハ等より成る基体１上に、図１Ｄに示すように、感光性ポリイミド等の絶縁層６をスピンコート等により塗布形成する。   As shown in FIG. 1D, an insulating layer 6 such as photosensitive polyimide is applied and formed by spin coating or the like on the substrate 1 made of the active element wafer or the like subjected to the groove processing.

この絶縁層６の厚さが５０μｍの場合は、粘度を６Ｐａ・ｓ、厚さ１００μｍの場合は、粘度を１０Ｐａ・ｓ程度とし得る。コーティング条件は、厚さ５０μｍの場合は例えば、
回転数及び時間：８００ｒｐｍ・３０ｓ＋１１００ｒｐｍ・３０ｓ
プリベーク：９０℃・２４０ｓ＋１１０℃・２４０ｓ
キュア：２００℃・０.５ｈ＋３２０℃・１ｈ
とすることができる。 When the thickness of the insulating layer 6 is 50 μm, the viscosity can be 6 Pa · s, and when the thickness is 100 μm, the viscosity can be about 10 Pa · s. The coating condition is, for example, when the thickness is 50 μm.
Rotation speed and time: 800rpm ・ 30s + 1100rpm ・ 30s
Pre-baking: 90 ° C / 240s + 110 ° C / 240s
Cure: 200 ℃ ・ 0.5h + 320 ℃ ・ 1h
It can be.

また、絶縁層６の厚さが１００μｍの場合は、例えば
回転数：８００ｒｐｍ・３０ｓ＋１５００ｒｐｍ・３０ｓ
プリベーク：９０℃・３００ｓ＋１１０℃・３００ｓ
キュア：２００℃・０.５ｈ＋３２０℃・１ｈ
とすることができる。絶縁層６の材料としては、エポキシ系、シリコン系、ポリオレフィン系等の樹脂を用いてもよい。
なお、絶縁層６の材料としてはこのような硬化性樹脂等のワニスではなく、真空ラミネートによる感光性フィルムを用いてもよい。 Further, when the thickness of the insulating layer 6 is 100 μm, for example, the number of rotations: 800 rpm · 30 s + 1500 rpm · 30 s
Pre-bake: 90 ℃ ・ 300s + 110 ℃ ・ 300s
Cure: 200 ℃ ・ 0.5h + 320 ℃ ・ 1h
It can be. As a material of the insulating layer 6, an epoxy resin, a silicon resin, a polyolefin resin, or the like may be used.
In addition, as a material of the insulating layer 6, you may use the photosensitive film by vacuum lamination instead of varnish, such as such curable resin.

次に、図２Ａに示すように、能動素子２上の電極３及び溝５上、また図示しないが受光部及び／又は発光部上の絶縁層６を除去するため、露光現像により開口６ａ、６ｂを形成し、すなわちＶＩＡ窓明けを行う。なお溝５内においては、溝５内中央部の絶縁層６を残して底部５ｂまで露出する開口６ｂとする。これは、溝内が全て導電層すなわちメタルであると、後の個片化の工程において、通常のスクライブ方法では剥離等を生じ、良好にダイシングを行えないためである。すなわち中央部に絶縁層を残すパターンとすることによって、剥離等を生じることなく通常のスクライブ方法で良好に個片化することが容易となる。
なお、図２Ａにおいては、溝５の能動素子２側の側面上及びこれとは反対側の側面上に比較的厚さの薄い絶縁層６を残しているが、設けなくてもよい。 Next, as shown in FIG. 2A, in order to remove the insulating layer 6 on the electrode 3 and the groove 5 on the active element 2 and on the light receiving portion and / or the light emitting portion (not shown), openings 6a and 6b are formed by exposure and development. , Ie, VIA window opening. In addition, in the groove | channel 5, it is set as the opening 6b exposed to the bottom part 5b, leaving the insulating layer 6 of the center part in the groove | channel 5. FIG. This is because if the entire groove is made of a conductive layer, that is, a metal, peeling or the like occurs in the subsequent singulation process, and dicing cannot be performed satisfactorily. That is, by using a pattern that leaves an insulating layer in the center, it becomes easy to singulate well by a normal scribing method without causing peeling or the like.
In FIG. 2A, the relatively thin insulating layer 6 is left on the side surface of the groove 5 on the active element 2 side and the side surface on the opposite side, but it may not be provided.

その後、配線とＶＩＡ電極をＣｕ等のめっきで形成するための電解めっき用のシードとして、また能動素子電極のＵＢＭ（Under Bump Metal）として、ＴｉＣｕ等よりなる下地層７を図２Ｂに示すようにスパッタ等により成膜する。この下地層７の膜厚は、ＴｉＣｕを用いる場合は例えばＴｉを１６０ｎｍ、Ｃｕを６００ｎｍとする。
次に、配線部のみに選択的にＣｕ等のめっきを行うためのレジストパターンを形成する。レジストを全面的に塗布し、図２Ｃに示すように、露光、現像により、電極３上と、溝５内の開口６ａ、６ｂ上を露出するパターンのレジスト８を形成する。
そして、図２Ｄに示すように、Ｃｕ等の電解めっきを行い、厚さ例えば７μｍの導電層９を形成して、いわゆるＶＩＡフィルを行う。この導電層９によって後の工程で基体１の表裏に通じる配線部が構成され、すなわち能動素子２の外縁部に配線部が形成される。 Thereafter, as shown in FIG. 2B, an underlayer 7 made of TiCu or the like is used as a seed for electrolytic plating for forming wiring and a VIA electrode by plating such as Cu, and as an UBM (Under Bump Metal) of an active element electrode. A film is formed by sputtering or the like. The film thickness of the underlayer 7 is, for example, 160 nm for Ti and 600 nm for Cu when TiCu is used.
Next, a resist pattern for selectively plating Cu or the like is formed only on the wiring portion. A resist is applied on the entire surface, and as shown in FIG. 2C, a resist 8 having a pattern exposing the electrode 3 and the openings 6a and 6b in the groove 5 is formed by exposure and development.
Then, as shown in FIG. 2D, electrolytic plating such as Cu is performed to form a conductive layer 9 having a thickness of, for example, 7 μm, and so-called VIA fill is performed. The conductive layer 9 forms a wiring portion that communicates with the front and back of the substrate 1 in a later step, that is, a wiring portion is formed on the outer edge portion of the active element 2.

ここで、図１Ｃにおいて形成する溝５の幅すなわちスクライブ幅を１００μｍとした場合は、後の個片化の工程において用いるスクライブでのダイシングブレード幅を４０μｍ、チッピングを１５μｍ程度とすると、図２Ａの工程において溝５内の中央部に残す絶縁層６の幅は５５μｍ程度あれば十分となる。このとき溝５内に形成する導電層９の幅は片側２２μｍ程度確保できる。   Here, when the width of the groove 5 formed in FIG. 1C, that is, the scribe width is set to 100 μm, when the dicing blade width in the scribe used in the subsequent singulation process is set to 40 μm and chipping is about 15 μm, FIG. In the process, it is sufficient that the width of the insulating layer 6 to be left in the central portion in the groove 5 is about 55 μm. At this time, the width of the conductive layer 9 formed in the groove 5 can be secured about 22 μm on one side.

次に、図３Ａに示すように、レジストを剥離して能動素子２上と、溝５内中央部の絶縁層６上の下地層７を例えばＣｕ、Ｔｉの順番でエッチングにより除去を行う。
図３Ｂに示すように、石英ガラス基板等の光透過性基体を貼り合わせるため、接着層１０を形成する。この幅ｗは、切り残しが５０μｍ以上必要であるためガラス等の光透過性基体が個片の場合は５０μｍ以上、ウエーハ状態では５０μｍ＋ダイシングカーフ幅以上が必要となる。またこの接着層１０は、外側に幅を広げて形成するとチップサイズが大きくなるため、内側に広げて形成する。このため、能動素子２の受光、発光エリアに掛からないサイズが最大となる。したがって、接着層１０の幅ｗは５０μｍ以上１５０μｍ以下程度として形成することが望ましい。接着層１０は、感光性接着シートもしくは印刷法によるＢステージ（半硬化状態）エポキシ樹脂を使用することができる。 Next, as shown in FIG. 3A, the resist is peeled off, and the underlying layer 7 on the active element 2 and the insulating layer 6 at the center in the groove 5 is removed by etching in the order of Cu and Ti, for example.
As shown in FIG. 3B, an adhesive layer 10 is formed to bond a light-transmitting substrate such as a quartz glass substrate. The width w needs to be not less than 50 μm, so if the light-transmitting substrate such as glass is a single piece, it needs to be 50 μm or more, and in the wafer state, it needs to be 50 μm + dicing kerf width or more. Further, the adhesive layer 10 is formed to be expanded inward because the chip size increases when formed with the width increased outward. For this reason, the size which does not cover the light receiving and light emitting area of the active element 2 is maximized. Therefore, it is desirable to form the width w of the adhesive layer 10 to be about 50 μm or more and 150 μm or less. The adhesive layer 10 can use a photosensitive adhesive sheet or a B-stage (semi-cured state) epoxy resin by a printing method.

そして、図３Ｃに示すように、石英ガラス等より成る光透過性基体２０の圧着を行う。光透過性基体２０の材料は、その他例えば可視光や紫外光を比較的高い透過率をもって、光損失を抑えて透過する材料、構成であればよい。またこの光透過性基体２０の圧着は、例えばウエーハ外形基準で油圧プレス又は真空ラミネーターで行う。
光透過性基体２０をウエーハ状態で圧着する場合は、シートラミネータで７μｍ程度の厚さの配線層を埋め込むための荷重が必要であり、ローラー送り速度０．６ｍ／分、温度１００℃、圧力５０Ｐｓｉｇ程度である。一方、光透過性基体２０を個片として圧着する場合は、荷重２．０Ｎ、温度１００℃、時間０．５ｓ程度で圧着する。したがって、荷重は０．５〜２．０ＭＰａ程度、時間は０．５〜５ｓ程度とする。なお、個片での圧着では下地とのアライメント時間が必要であるため、ウエーハ状態の方が圧着時間は少なくなるという利点を有する。 Then, as shown in FIG. 3C, a light-transmitting substrate 20 made of quartz glass or the like is pressed. The material of the light-transmitting substrate 20 may be any other material or structure that transmits visible light or ultraviolet light with a relatively high transmittance while suppressing light loss. The light-transmitting substrate 20 is pressure-bonded by, for example, a hydraulic press or a vacuum laminator based on the wafer outer shape.
When pressure bonding the light-transmitting substrate 20 in a wafer state, a load is required to embed a wiring layer having a thickness of about 7 μm with a sheet laminator, a roller feed speed of 0.6 m / min, a temperature of 100 ° C., and a pressure of 50 Psig. Degree. On the other hand, when the light-transmitting substrate 20 is pressure-bonded as a single piece, it is pressure-bonded at a load of 2.0 N, a temperature of 100 ° C., and a time of about 0.5 s. Therefore, the load is about 0.5 to 2.0 MPa, and the time is about 0.5 to 5 s. In addition, since the time for alignment with the base is required for pressure bonding with individual pieces, the wafer state has an advantage that the time for pressure bonding is reduced.

石英ガラス等の光透過性基体２０と能動素子ウエーハ等より成る基体１とを貼り合わせた後、石英ガラス面に裏面研削用の保護テープをラミネートして、裏面研削を行う。研削は例えば＃６００、＃２０００の粒径の砥石で行い、図３Ｄに示すように、基体１を薄化して溝５内に形成した導電層９の溝底部側の表面９Ｓ、いわゆるＶＩＡ部を露出させる。   After the light-transmitting substrate 20 such as quartz glass and the substrate 1 made of an active element wafer or the like are bonded together, a back surface grinding protective tape is laminated on the quartz glass surface to perform back surface grinding. Grinding is performed with, for example, a grindstone having a particle diameter of # 600 or # 2000, and a surface 9S on the groove bottom side of the conductive layer 9 formed in the groove 5 by thinning the base 1 is formed as shown in FIG. Expose.

このようにＶＩＡ部すなわち導電層９の表面９Ｓを露出した基体１の第２の面１Ｂ上に、図４Ａに示すように、樹脂等の絶縁層１１を、スピンコート、印刷、ディスペンス、フィルムラミネート等により成膜する。そしてこの絶縁層１１を、ＶＩＡ部すなわち導電層９の表面９Ｓを除去するパターンとして露光、現像により形成する。絶縁層１１の材料は、エポキシ樹脂、ポリイミド樹脂、ＰＢＯ（ポリパラフェニレンベンゾビスオキサゾール）樹脂、アクリル樹脂等を用い得る。感光材を用いる場合はそのまま、露光、現像により表面９Ｓを除去するパターニングを行うことができる。   As shown in FIG. 4A, an insulating layer 11 such as a resin is applied to the VIA portion, that is, the second surface 1B of the base 1 from which the surface 9S of the conductive layer 9 is exposed, as shown in FIG. 4A. A film is formed by, for example. The insulating layer 11 is formed by exposure and development as a pattern for removing the VIA portion, that is, the surface 9S of the conductive layer 9. As a material of the insulating layer 11, an epoxy resin, a polyimide resin, a PBO (polyparaphenylene benzobisoxazole) resin, an acrylic resin, or the like can be used. When the photosensitive material is used, patterning for removing the surface 9S by exposure and development can be performed as it is.

次に、図４Ｂに示すように、Ｃｕめっき等の配線形成のためのシードとなる下地層１２をスパッタ法等により形成する。例えば下地層１２として、Ｔｉを厚さ１６０ｎｍ、Ｃｕを厚さ６００ｎｍとする。
図４Ｃに示すように、配線形成のためレジスト１３のパターニングを行い、電解めっき等によりＣｕ等の成膜を行って、図４Ｄに示すように、所定の配線パターンの導電層１４を形成する。この導電層１４と導電層９とにより、能動素子２の外縁部において基体１の第１の面１Ａから第２の面１Ｂに貫通する配線部２１が形成される。 Next, as shown in FIG. 4B, a base layer 12 serving as a seed for wiring formation such as Cu plating is formed by sputtering or the like. For example, as the underlayer 12, Ti is 160 nm thick and Cu is 600 nm thick.
As shown in FIG. 4C, the resist 13 is patterned for wiring formation, and Cu or the like is formed by electrolytic plating or the like to form a conductive layer 14 having a predetermined wiring pattern as shown in FIG. 4D. The conductive layer 14 and the conductive layer 9 form a wiring portion 21 penetrating from the first surface 1A of the base 1 to the second surface 1B at the outer edge portion of the active element 2.

導電層１４を形成した後、レジスト１３を剥離し、更にレジスト１３の下部の下地層１２を例えばＣｕ、Ｔｉの順番でエッチングして、図５Ａに示すように除去する。
次に、外部電極用の例えばバンプを形成するため、絶縁層１５を塗布し、露光現像により電極を形成する領域を図５Ｂに示すように露出させる。
その後、この場合下ウエーハのＣｕポストである導電層１４上に、図５Ｃに示すように、バンプ等の電極１６を形成する。この外部電極となる電極１６は、印刷、めっき又はボール搭載等によって形成する。 After the conductive layer 14 is formed, the resist 13 is peeled off, and the underlying layer 12 below the resist 13 is etched in the order of Cu and Ti, for example, and removed as shown in FIG. 5A.
Next, in order to form, for example, a bump for an external electrode, an insulating layer 15 is applied, and a region where the electrode is formed by exposure and development is exposed as shown in FIG. 5B.
Thereafter, electrodes 16 such as bumps are formed on the conductive layer 14 which is the Cu post of the lower wafer in this case, as shown in FIG. 5C. The electrode 16 serving as the external electrode is formed by printing, plating, ball mounting, or the like.

そしてダイシング等により石英ガラス基板等より成る光透過性基体２０と、能動素子ウエーハ等より成る基体１の個片化を行う。このダイシング等の個片化に際して能動素子２のサイズの周囲に要する大きさとしては、溝５内の絶縁層６、導電層９及び１４よりなる配線部２１の幅があればよい。上述したように、溝５すなわちスクライブ幅を１００μｍとして、中央部に残す絶縁層を４０＋１５μｍ、導電層を２２μｍ程度として形成できるので、この場合、能動素子２の外縁部から＋５０μｍ程度の余裕があれば配線部２１を形成できる。したがって、片側＋０．０５ｍｍであるので両側に＋０．１ｍｍとなり、能動素子２の大きさに対して外側に＋０．１ｍｍの大きさがあればよい。   Then, the light transmitting base 20 made of a quartz glass substrate or the like and the base 1 made of an active element wafer or the like are separated into individual pieces by dicing or the like. As a size required around the size of the active element 2 for dicing or the like, the width of the wiring portion 21 including the insulating layer 6 and the conductive layers 9 and 14 in the groove 5 may be sufficient. As described above, it is possible to form the groove 5, that is, the scribe width of 100 μm, the insulating layer remaining in the central portion as 40 + 15 μm, and the conductive layer as about 22 μm. In this case, if there is a margin of about +50 μm from the outer edge of the active element 2 The wiring part 21 can be formed. Accordingly, since it is +0.05 mm on one side, it is +0.1 mm on both sides, and the size of the active element 2 only needs to be +0.1 mm on the outside.

これにより、図６に示すように、本発明構成の半導体装置１００を容易に形成することができる。この半導体装置１００は、基体の第１の面１Ａ上に能動素子２を備え、能動素子２を覆って光透過性基体２０が搭載されて封止される。そして、能動素子２の外縁部に、基体１の第１の面１Ａからこれとは反対側の第２の面１Ｂに貫通する導電層９及び１４より成る配線部２１が設けられる。第２の面１Ｂ側の配線部２１上には、バンプ等の電極１６、すなわち外部電極が設けられて成る。能動素子２のサイズに対して＋０．１ｍｍの大きさのチップサイズ構造を実現できる。   Thereby, as shown in FIG. 6, the semiconductor device 100 having the configuration of the present invention can be easily formed. The semiconductor device 100 includes an active element 2 on the first surface 1A of the base, and a light-transmitting base 20 is mounted on the active element 2 and sealed. A wiring portion 21 including conductive layers 9 and 14 penetrating from the first surface 1A of the base 1 to the second surface 1B opposite to the first surface 1A of the base 1 is provided on the outer edge portion of the active element 2. On the wiring part 21 on the second surface 1B side, electrodes 16 such as bumps, that is, external electrodes are provided. A chip size structure having a size of +0.1 mm with respect to the size of the active element 2 can be realized.

なお、光透過性基体２０として、予め個片化された石英ガラス基板等の光透過性部材を用いることもできる。前述の図３Ｂから図３Ｄの工程において、接着層１０によって、精度良く基体１上に搭載することが可能となる。
一方、チップサイズではなくウエーハサイズに近い石英ガラス基板を用いる場合は、搭載時の位置合わせが不要となり、搭載作業の簡易化を図ることができる。上述したように圧着時間も短縮でき、また基体１の個片化と同時工程で個片化が可能である。 In addition, as the light-transmitting substrate 20, a light-transmitting member such as a quartz glass substrate that has been separated into pieces can be used. In the steps of FIGS. 3B to 3D described above, the adhesive layer 10 can be mounted on the substrate 1 with high accuracy.
On the other hand, when a quartz glass substrate close to the wafer size is used instead of the chip size, alignment at the time of mounting becomes unnecessary, and the mounting operation can be simplified. As described above, the crimping time can be shortened, and the substrate 1 can be separated into pieces at the same time as the separation.

以上説明したように、本発明の半導体装置の製造方法によれば、ワイヤーボンドやシリコン貫通プロセスによらず、したがって貫通用の特殊な能動素子レイアウトを使用することなく、能動素子を設ける面と反対側の面に外部電極を容易に形成することができる。これにより、能動素子の大きさから＋０．１ｍｍの大きさのチップサイズ構造とすることができる。
また、薄化個片化した能動素子の搭載工程を必要とせず、ウエーハ状態で貫通ＶＩＡを形成することが可能になることで、能動素子の受光及び／又は発光が可能なチップサイズパッケージ構成の半導体装置を、低コストで容易に製造することができる。 As described above, according to the method of manufacturing a semiconductor device of the present invention, it is opposite to the surface on which the active element is provided, without using a wire bond or a silicon through process, and thus without using a special active element layout for penetrating. The external electrode can be easily formed on the side surface. Thus, a chip size structure having a size of +0.1 mm from the size of the active element can be obtained.
In addition, since a through VIA can be formed in a wafer state without requiring a process of mounting a thinned and separated active element, a chip size package configuration capable of receiving and / or emitting light from the active element is possible. A semiconductor device can be easily manufactured at low cost.

なお、本発明の半導体装置とその製造方法は、上述の実施形態例において説明した構成や製造方法に限定されるものではなく、その他基体や光透過性基体など各部の材料構成、電極形状等、本発明構成を逸脱しない範囲において種々の変形、変更が可能である。   The semiconductor device and the manufacturing method thereof according to the present invention are not limited to the configuration and manufacturing method described in the above-described embodiment, and other material configurations such as a base and a light transmissive base, electrode shapes, and the like. Various modifications and changes can be made without departing from the configuration of the present invention.

Ａ〜Ｄは本発明の一実施の形態に係る半導体装置の製造方法の製造工程図（その１）である。A to D are manufacturing process diagrams (No. 1) of a manufacturing method of a semiconductor device according to an embodiment of the present invention; Ａ〜Ｄは本発明の一実施の形態に係る半導体装置の製造方法の製造工程図（その２）である。A to D are manufacturing process diagrams (part 2) of the method for manufacturing the semiconductor device according to the embodiment of the invention. Ａ〜Ｄは本発明の一実施の形態に係る半導体装置の製造方法の製造工程図（その３）である。A to D are manufacturing process diagrams (part 3) of the method for manufacturing a semiconductor device according to the embodiment of the present invention. Ａ〜Ｄは本発明の一実施の形態に係る半導体装置の製造方法の製造工程図（その４）である。FIGS. 4A to 4D are manufacturing process diagrams (part 4) of a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIGS. Ａ〜Ｃは本発明の一実施の形態に係る半導体装置の製造方法の製造工程図（その５）である。FIGS. 8A to 8C are manufacturing process diagrams (part 5) of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIGS. 本発明の一実施の形態に係る半導体装置の断面構成図である。It is a section lineblock diagram of a semiconductor device concerning one embodiment of the present invention.

符号の説明Explanation of symbols

１．基体、２．能動素子、３．電極、４．保護層、５．溝、６．絶縁層、６ａ、６ｂ．開口、７．下地層、８．レジスト、９．導電層、９Ｓ．表面、１０．接着層、１１．絶縁層、１２．下地層、１３．レジスト、１４．導電層、１５．絶縁層、１６．電極、２０．光透過性基体、２１．配線部、１００．半導体装置   1. 1. substrate, 2. active element; Electrodes, 4. 4. protective layer; Groove, 6. Insulating layer, 6a, 6b. 6. opening, 7. Underlayer, Resist, 9. Conductive layer, 9S. Surface, 10. 10. adhesive layer; An insulating layer, 12. Underlayer, 13. Resist, 14. Conductive layer, 15. Insulating layer, 16. Electrodes, 20. 21. a light transmissive substrate; Wiring part, 100. Semiconductor device

Claims (1)

能動素子を有する基体の第１の面に溝を形成する工程と、
前記溝内に導電層を形成して、前記能動素子の電極に接続する工程と、
前記基体上に、光透過性基体を搭載する工程と、
前記基体を、前記第１の面とは反対側の裏面側から前記溝の底部まで薄化して、前記基体の前記第１の面とは反対側の第２の面に前記溝の底部側の前記導電層の表面を露出する工程と、
前記基体を反転させて、前記第２の面上に再配線を行って、前記第１及び第２の面に貫通する導電層より成る配線部を形成する工程と、
前記第２の面側の配線部上に電極を形成する工程と、を有し、
前記溝内に導電層を形成する工程において、前記溝内の中央部に絶縁層を形成し、前記溝の側面と中央部の絶縁層との間に前記導電層を形成する
半導体装置の製造方法。 Forming a groove in a first surface of a substrate having active elements ;
Forming a conductive layer in the trench and connecting to the electrode of the active element;
Mounting a light transmissive substrate on the substrate;
The base is thinned from the back surface side opposite to the first surface to the bottom of the groove, and the second surface of the base opposite to the first surface is placed on the bottom side of the groove. Exposing the surface of the conductive layer;
Reversing the base and performing rewiring on the second surface to form a wiring portion made of a conductive layer penetrating the first and second surfaces;
Forming an electrode on the wiring portion on the second surface side ,
A method of manufacturing a semiconductor device , wherein in the step of forming a conductive layer in the groove, an insulating layer is formed in a central portion of the groove, and the conductive layer is formed between a side surface of the groove and the insulating layer in the central portion. .
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