JP5180495B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP5180495B2 JP5180495B2 JP2007065277A JP2007065277A JP5180495B2 JP 5180495 B2 JP5180495 B2 JP 5180495B2 JP 2007065277 A JP2007065277 A JP 2007065277A JP 2007065277 A JP2007065277 A JP 2007065277A JP 5180495 B2 JP5180495 B2 JP 5180495B2
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- 239000004065 semiconductor Substances 0.000 title claims description 63
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 229920005989 resin Polymers 0.000 claims description 34
- 239000011347 resin Substances 0.000 claims description 34
- 238000007789 sealing Methods 0.000 claims description 19
- 239000000725 suspension Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 description 9
- 239000012212 insulator Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
半導体チップ及びリードフレームを備え、
前記リードフレームは、
前記半導体チップが載置された第1面、および前記第1面と反対の面である第2面を有するアイランドと、
前記アイランドに連結され、当該アイランドを保持する吊ピンと、
前記吊ピンから分岐した分岐部と、を有しており、
すべての前記分岐部の端部は、前記吊りピンよりも前記アイランドの前記第2面側に位置しており、
前記分岐部は、前記吊りピンと同一方向に分岐している、
半導体装置が提供される。
10 半導体チップ
12 パッド
20 アイランド
30 吊ピン
40 分岐部
42 分岐部
44 分岐部
50 リード端子
60 リードフレーム
70 ワイヤ
80 金型
82 上金型
84 下金型
90 封止樹脂
Claims (7)
- 半導体チップ及びリードフレームを備え、
前記リードフレームは、
前記半導体チップが載置された第1面、および前記第1面と反対の面である第2面を有するアイランドと、
前記アイランドに連結され、当該アイランドを保持する吊ピンと、
前記吊ピンから分岐した分岐部と、を有しており、
すべての前記分岐部の端部は、前記吊りピンよりも前記アイランドの前記第2面側に位置しており、
前記分岐部は、前記吊りピンと同一方向に分岐しており、
前記半導体チップを覆う封止樹脂層を更に備え、
前記アイランドの前記第2面は、前記封止樹脂層の表面に露出している半導体装置。 - 請求項1に記載の半導体装置において、
前記分岐部は、前記第2面側に向けて曲げ加工されている、半導体装置。 - 請求項1または2に記載の半導体装置において、
前記分岐部は、前記吊ピンの両側に設けられた第1および第2の分岐部を含む、半導体装置。 - 請求項1乃至3いずれか1項に記載の半導体装置において、
前記アイランドの前記第2面を下にしたとき、
前記アイランドは、前記吊ピンの先端部よりも低い位置に存在する、半導体装置。 - 請求項1乃至4いずれか1項に記載の半導体装置において、
前記吊りピンが複数配置されており、
それぞれの前記吊りピンに、前記分岐部が配置されている、半導体装置。 - 請求項1乃至5いずれか1項に記載の半導体装置において、
前記半導体チップを介して前記吊りピンが互いに反対側に配置されている、半導体装置。 - 請求項1乃至6いずれかに記載のリードフレームを準備する工程と、
前記アイランドの前記第1面上に、前記半導体チップを載置する工程と、
前記半導体チップを載置する工程よりも後に、上金型および下金型を有する金型に前記リードフレームを設置する工程と、
前記リードフレームが前記金型に設置された状態で、当該金型内に封止樹脂を注入する工程と、を含み、
前記リードフレームは、前記上金型および前記下金型によって前記分岐部が挟み込まれるように、前記金型に設置されており、
前記リードフレームは、前記アイランドの前記第2面が前記下金型の底面に接するように、前記金型に設置される半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007065277A JP5180495B2 (ja) | 2007-03-14 | 2007-03-14 | 半導体装置およびその製造方法 |
US12/048,447 US7944027B2 (en) | 2007-03-14 | 2008-03-14 | Lead frame, semiconductor device, and method of manufacturing the semiconductor device |
US13/081,174 US8236620B2 (en) | 2007-03-14 | 2011-04-06 | Method of manufacturing a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007065277A JP5180495B2 (ja) | 2007-03-14 | 2007-03-14 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008227280A JP2008227280A (ja) | 2008-09-25 |
JP5180495B2 true JP5180495B2 (ja) | 2013-04-10 |
Family
ID=39761815
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2007065277A Expired - Fee Related JP5180495B2 (ja) | 2007-03-14 | 2007-03-14 | 半導体装置およびその製造方法 |
Country Status (2)
Country | Link |
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US (2) | US7944027B2 (ja) |
JP (1) | JP5180495B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP7030481B2 (ja) | 2017-11-10 | 2022-03-07 | エイブリック株式会社 | 樹脂封止金型および半導体装置の製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1246743B (it) * | 1990-12-28 | 1994-11-26 | Sgs Thomson Microelectronics | Stampo per la fabbricazione di contenitori in plastica, per circuiti integrati,con dissipatore termico incorporato. |
JP2621814B2 (ja) * | 1994-11-29 | 1997-06-18 | 日本電気株式会社 | 樹脂封止型半導体装置 |
JP3616469B2 (ja) | 1997-01-24 | 2005-02-02 | ローム株式会社 | 半導体装置およびその製造方法 |
JP3285815B2 (ja) * | 1998-03-12 | 2002-05-27 | 松下電器産業株式会社 | リードフレーム,樹脂封止型半導体装置及びその製造方法 |
KR100319616B1 (ko) * | 1999-04-17 | 2002-01-05 | 김영환 | 리드프레임 및 이를 이용한 버텀리드 반도체패키지 |
JP3602997B2 (ja) * | 1999-12-15 | 2004-12-15 | 松下電器産業株式会社 | 半導体装置及び半導体装置の製造方法 |
TW508774B (en) * | 2000-09-15 | 2002-11-01 | Samsung Techwin Co Ltd | Lead frame, semiconductor package having the same, method of manufacturing semiconductor package, molding plates and molding machine for manufacturing semiconductor package |
JP4417150B2 (ja) * | 2004-03-23 | 2010-02-17 | 株式会社ルネサステクノロジ | 半導体装置 |
-
2007
- 2007-03-14 JP JP2007065277A patent/JP5180495B2/ja not_active Expired - Fee Related
-
2008
- 2008-03-14 US US12/048,447 patent/US7944027B2/en active Active
-
2011
- 2011-04-06 US US13/081,174 patent/US8236620B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7944027B2 (en) | 2011-05-17 |
US8236620B2 (en) | 2012-08-07 |
US20110183473A1 (en) | 2011-07-28 |
US20080224280A1 (en) | 2008-09-18 |
JP2008227280A (ja) | 2008-09-25 |
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