JP5141945B2 - Semiconductor device and capacitor - Google Patents

Semiconductor device and capacitor Download PDF

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JP5141945B2
JP5141945B2 JP2007056151A JP2007056151A JP5141945B2 JP 5141945 B2 JP5141945 B2 JP 5141945B2 JP 2007056151 A JP2007056151 A JP 2007056151A JP 2007056151 A JP2007056151 A JP 2007056151A JP 5141945 B2 JP5141945 B2 JP 5141945B2
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insulating film
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JP2008218827A (en
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アヘメト パールハット
洋 岩井
健雄 服部
一生 筒井
邦之 角嶋
豊裕 知京
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本発明は、高誘電率（ｈｉｇｈ−ｋ）材料を用いた半導体装置及びコンデンサに関する。   The present invention relates to a semiconductor device and a capacitor using a high dielectric constant (high-k) material.

半導体集積回路技術の発展に伴い、トランジスタ、コンデンサ、ダイオード等の素子の微細化が要求されている。例えば、ゲート電極（金属：Ｍｅｔａｌ）−ゲート酸化膜（Ｏｘｉｄｅ）−半導体（Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）の積層構造を基本とするＭＯＳＦＥＴ（Metal Oxide Semiconductor FET）の微細化では、その構成要素であるゲート絶縁膜（ゲート酸化膜）の薄膜化が要求される。   With the development of semiconductor integrated circuit technology, miniaturization of elements such as transistors, capacitors, and diodes is required. For example, in the miniaturization of a MOSFET (Metal Oxide Semiconductor FET) based on a stacked structure of a gate electrode (metal) -gate oxide film (Oxide) -semiconductor (Semiconductor), a gate insulating film (gate) which is a constituent element thereof is used. Thinning of the oxide film is required.

従来、ＭＯＳＦＥＴのゲート絶縁膜としてＳｉＯ２、ＳｉＯｘＮｙなどが使われてきたが、素子の微細化に伴い、まもなくそれらの絶縁膜の限界に達する状況にある。それはゲート絶縁膜の膜厚が３ｎｍを切ってどんどん薄くなっていくと、電子の絶縁膜をトンネルするトンネル確率がどんどん大きくなり、ゲート絶縁膜を介してゲート電極とチャネル間に大きなリーク電流が流れてしまうためである。ＳｉＯｘＮｙ絶縁膜を用いたシリコン酸化膜換算膜厚（EOT：Equivalent Oxide Thickness）が１ｎｍ程度のＭＯＳＦＥＴ素子も開発されているが、絶縁膜の物理膜厚が１ｎｍ以下になると素子の動作が難しくなる程の大きなリーク電流が流れてしまうため、ＳｉＯ２、ＳｉＯｘＮｙに代わる新しいゲート絶縁膜材料の導入が必要となる。 Conventionally, as a gate insulating film of the MOSFET SiO 2, although such SiO x N y has been used, with the miniaturization of elements, in a situation where soon reach the limits of their insulating film. That is, as the thickness of the gate insulation film becomes thinner than 3 nm, the tunnel probability of tunneling through the electron insulation film increases, and a large leakage current flows between the gate electrode and the channel through the gate insulation film. It is because it ends. MOSFET elements having an equivalent oxide thickness (EOT) of about 1 nm using an SiO x N y insulating film have been developed. However, when the physical film thickness of the insulating film is 1 nm or less, the operation of the element is improved. Since a leak current that becomes difficult to flow flows, it is necessary to introduce a new gate insulating film material in place of SiO 2 and SiO x N y .

ＥＯＴは、絶縁膜の物理膜厚をＴ、誘電率をε、ＳｉＯ２膜の誘電率をεSiO2とすると、次の関係を満たす。 EOT satisfies the following relationship, where T is the physical film thickness of the insulating film, ε is the dielectric constant, and εSiO 2 is the dielectric constant of the SiO 2 film.

ＥＯＴ＝εSiO2×Ｔ/ε
この式からＳｉＯ２膜よりも誘電率の大きい材料（高誘電率材料）を用いれば、物理膜厚を厚くしてリーク電流を抑えることが可能であることがわかる。 EOT = εSiO 2 × T / ε
From this equation, it can be seen that if a material (high dielectric constant material) having a dielectric constant larger than that of the SiO 2 film is used, it is possible to suppress the leakage current by increasing the physical film thickness.

高誘電率（ｈｉｇｈ−ｋ）材料の絶縁膜として、例えば、Ｈｆ系のｈｉｇｈ−ｋ絶縁膜が挙げられる（例えば、非特許文献１参照。）。しかし、Ｈｆ系のｈｉｇｈ−ｋ絶縁膜では、ｈｉｇｈ−ｋ絶縁膜とＳｉとの間に０．５ｎｍ程度のＳｉＯ２膜を積層しなければならず、０．７ｎｍ以下のＥＯＴの達成が難しい。つまり、Ｈｆ系のｈｉｇｈ−ｋ絶縁膜は、ＥＯＴの要求が０．７ｎｍぐらいまでの素子には用いることが可能であるが、０．７ｎｍ以下のＥＯＴが要求される素子の微細化の為には、他の高誘電率材料の導入が必要となる。 As an insulating film made of a high dielectric constant (high-k) material, for example, an Hf-based high-k insulating film can be given (for example, see Non-Patent Document 1). However, in an Hf-based high-k insulating film, an SiO 2 film of about 0.5 nm must be laminated between the high-k insulating film and Si, and it is difficult to achieve an EOT of 0.7 nm or less. In other words, the Hf-based high-k insulating film can be used for an element having an EOT requirement up to about 0.7 nm, but for miniaturization of an element requiring an EOT of 0.7 nm or less. However, it is necessary to introduce other high dielectric constant materials.

M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, A. Shanware, and L. Colombo, Appl. Phys. Lett. 80, p3183, (2002)M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, A. Shanware, and L. Colombo, Appl. Phys. Lett. 80, p3183, (2002) M. Suzuki, M. Tomita, T. Yamaguguchi, and N. Fukushima, IEDM Tech.Dig., p433, (2005)M. Suzuki, M. Tomita, T. Yamaguguchi, and N. Fukushima, IEDM Tech.Dig., P433, (2005) Y. Zhao, K. Kita, K. Kyuno, and A. Toriumi, Appl. Phys. Lett. 89, p252905 (2006)Y. Zhao, K. Kita, K. Kyuno, and A. Toriumi, Appl. Phys. Lett. 89, p252905 (2006)

０．７ｎｍ以下のＥＯＴが得られる高誘電率材料として、酸化ランタン（Ｌａ２Ｏ３）が注目されている（例えば、非特許文献２参照。）。しかしながら、Ｌａ２Ｏ３は、強い吸湿性を有しており、空気中の水分によってＬａ（ＯＨ）３に変化してしまうため、絶縁膜として安定性が問題となっていた。 As a high dielectric constant material capable of obtaining an EOT of 0.7 nm or less, lanthanum oxide (La 2 O 3 ) has attracted attention (see, for example, Non-Patent Document 2). However, since La 2 O 3 has a strong hygroscopic property and changes to La (OH) 3 due to moisture in the air, stability as an insulating film has been a problem.

また、非特許文献３には、吸湿性を改善するためにＹを４０％、又は７０％添加したＬａＹＯｘ膜をｈｉｇｈ−ｋ絶縁膜に用いることが記載されているが、Ｙの添加割合が大きいため、混合割合の大きい混合膜ではＬａ２Ｏ３の絶縁膜としての特有の性質を維持することが困難である。 Non-Patent Document 3 describes that a LaYOx film added with 40% or 70% Y is used for a high-k insulating film in order to improve hygroscopicity, but the addition ratio of Y is large. Therefore, it is difficult to maintain the characteristic properties of the La 2 O 3 insulating film in a mixed film having a large mixing ratio.

本発明は、このような従来の実情に鑑みて提案されたものであり、Ｌａ２Ｏ３の強い吸湿性を改善し、優れた耐湿性及びデバイス特性を有する半導体装置及びコンデンサを提供することを目的とする。 The present invention has been proposed in view of such conventional circumstances, and provides a semiconductor device and a capacitor that improve the strong hygroscopicity of La 2 O 3 and have excellent moisture resistance and device characteristics. Objective.

本件発明者らは、上述した目的を達成するために、様々な観点から鋭意研究を重ねてきた。その結果、酸化ランタンに他の金属酸化物を少量添加することにより、Ｌａ２Ｏ３の絶縁膜としての特有の性質を維持させることができるとともに、耐湿性を飛躍的に向上させることができることを見出した。本発明は、このような知見に基づいて完成されたものである。 In order to achieve the above-described object, the present inventors have conducted intensive research from various viewpoints. As a result, by adding a small amount of other metal oxides to lanthanum oxide, it is possible to maintain the characteristic properties of La 2 O 3 as an insulating film and to drastically improve moisture resistance. I found it. The present invention has been completed based on such findings.

すなわち、本発明に係る半導体装置は、第１導電型の半導体基板と、前記半導体基板上に形成された高誘電率絶縁膜と、前記高誘電率絶縁膜上に形成されたゲート電極と、前記半導体基板の前記ゲート電極下両側に形成され、第２導電型のソース／ドレイン領域とを備える半導体装置において、前記高誘電率絶縁膜は、（Ｌａ１−ｘＭｘ）２Ｏ３（０＜ｘ≦０．３、ＭはＳｃ、Ｙ、Ｈｆ、Ｔｉ、Ｔａ、Ａｌ、Ｎｂの群から選ばれる１又は２以上の金属）で表記される組成からなることを特徴とする。 That is, a semiconductor device according to the present invention includes a first conductivity type semiconductor substrate, a high dielectric constant insulating film formed on the semiconductor substrate, a gate electrode formed on the high dielectric constant insulating film, In the semiconductor device formed on both sides of the semiconductor substrate below the gate electrode and having a source / drain region of the second conductivity type, the high dielectric constant insulating film is (La 1-x M x ) 2 O 3 (0 < x ≦ 0.3, and M is composed of a composition represented by 1 or 2 or more metals selected from the group of Sc, Y, Hf, Ti, Ta, Al, and Nb.

また、本発明に係るコンデンサは、高誘電率絶縁膜を介して下部電極と上部電極とが対向形成されてなるコンデンサにおいて、前記高誘電率絶縁膜は、（Ｌａ１−ｘＭｘ）２Ｏ３（０＜ｘ≦０．３、ＭはＳｃ、Ｙ、Ｈｆ、Ｔｉ、Ｔａ、Ａｌ、Ｎｂの群から選ばれる１又は２以上の金属）で表記される組成からなることを特徴としている。 The capacitor according to the present invention is a capacitor in which a lower electrode and an upper electrode are formed to face each other with a high dielectric constant insulating film interposed therebetween, wherein the high dielectric constant insulating film is (La 1-x M x ) 2 O. 3 (0 <x ≦ 0.3, where M is one or more metals selected from the group of Sc, Y, Hf, Ti, Ta, Al, and Nb).

本発明によれば、酸化ランタンに他の金属酸化物が添加された高誘電率絶縁膜を用いるため、酸化ランタン特有の性質が維持されるとともに耐湿性が向上する。   According to the present invention, since a high dielectric constant insulating film in which another metal oxide is added to lanthanum oxide is used, properties unique to lanthanum oxide are maintained and moisture resistance is improved.

以下、本発明を適用した具体的な実施の形態について、図面を参照しながら詳細に説明する。   Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

図１は、本発明の一実施形態に係る半導体装置の構造の概略を示す断面図である。この半導体装置１０は、ＭＯＳ型トランジスタの構造を有しており、第１導電型（例えばｐ型）の半導体基板１１と、半導体基板１１上に形成された高誘電率絶縁膜１２と、高誘電率絶縁膜１２上に形成されたゲート電極１３と、半導体基板１１のゲート電極１３下両側に形成された、第２導電型（例えばｎ型）のソース領域１４と、ドレイン領域１５とを備えて構成されている。   FIG. 1 is a cross-sectional view schematically showing the structure of a semiconductor device according to an embodiment of the present invention. The semiconductor device 10 has a MOS transistor structure, and includes a first conductivity type (for example, p-type) semiconductor substrate 11, a high dielectric constant insulating film 12 formed on the semiconductor substrate 11, and a high dielectric constant. A gate electrode 13 formed on the insulating film 12, a second conductivity type (for example, n-type) source region 14 formed on both sides of the semiconductor substrate 11 below the gate electrode 13, and a drain region 15. It is configured.

半導体基板１１は、例えば第１導電型（例えばｐ型）の単結晶（１００）シリコン基板である。ソース領域１４とドレイン領域１５との間のチャネル形成領域には、所望の閾値電圧が得られるように、例えばホウ素（Ｂ）等のｐ型不純物が導入される。   The semiconductor substrate 11 is, for example, a first conductivity type (for example, p-type) single crystal (100) silicon substrate. A p-type impurity such as boron (B) is introduced into the channel formation region between the source region 14 and the drain region 15 so as to obtain a desired threshold voltage.

高誘電率絶縁膜１２は、半導体基板１１のチャネル形成領域上に設けられる。また、高誘電率絶縁膜１２は、（Ｌａ１−ｘＭｘ）２Ｏ３（０＜ｘ≦０．３、ＭはＳｃ、Ｙ、Ｈｆ、Ｔｉ、Ｔａ、Ａｌ、Ｎｂの群から選ばれる１又は２以上の金属）で表記される組成からなる。これにより、高誘電率絶縁膜１２の耐湿性が改善され、半導体装置１０の安定性が向上する。一方、酸化ランタン混合膜が、ランタン以外の他の金属が原子比で３０％を越える場合、Ｌａ２Ｏ３の絶縁膜としての特有の性質を維持することが困難となる。 The high dielectric constant insulating film 12 is provided on the channel formation region of the semiconductor substrate 11. Further, the high dielectric constant insulating film 12 is selected from the group of (La 1-x M x ) 2 O 3 (0 <x ≦ 0.3, M is Sc, Y, Hf, Ti, Ta, Al, Nb). 1 or 2 or more metals). Thereby, the moisture resistance of the high dielectric constant insulating film 12 is improved, and the stability of the semiconductor device 10 is improved. On the other hand, if the metal other than lanthanum exceeds 30% in terms of the atomic ratio, it becomes difficult to maintain the characteristic properties of La 2 O 3 as an insulating film.

図２に示すように、酸化ランタン（Ｌａ２Ｏ３）は、Ｈｆ系酸化物よりも誘電率が大きい。そのため、高誘電率絶縁膜１２に酸化ランタンを用いれば、リーク電流を抑制することが可能となる。 As shown in FIG. 2, lanthanum oxide (La 2 O 3 ) has a dielectric constant larger than that of the Hf-based oxide. For this reason, if lanthanum oxide is used for the high dielectric constant insulating film 12, leakage current can be suppressed.

図３は、酸化ランタン絶縁膜の膜厚（EOT換算）対リーク電流特性を示すグラフである。このグラフは、コンデンサ構造（metal/La2O3/Si）のデバイスを測定したものである。この図３の結果より、酸化ランタン特有の性質を維持すれば、ＥＯＴ＝０．５ｎｍ程度でもリーク電流の抑制が可能であることが分かる。 FIG. 3 is a graph showing the film thickness (EOT conversion) versus leakage current characteristics of the lanthanum oxide insulating film. This graph is a measurement of a device with a capacitor structure (metal / La 2 O 3 / Si). From the results shown in FIG. 3, it can be seen that if the characteristic peculiar to lanthanum oxide is maintained, the leakage current can be suppressed even at EOT = 0.5 nm.

ゲート電極１３は、例えば金属あるいはポリシリコンから構成される。ポリシリコンの場合、例えばホウ素（Ｂ）等のアクセプタ不純物（第１不純物）の導入によりｐ型とされている。   The gate electrode 13 is made of, for example, metal or polysilicon. In the case of polysilicon, it is made p-type by introducing acceptor impurities (first impurities) such as boron (B).

ソース領域１４及びドレイン領域１５には、第２導電型（例えばｎ型）とするために、リン（Ｐ）、ヒ素（Ａｓ）等のドナー不純物が注入されている。   In the source region 14 and the drain region 15, donor impurities such as phosphorus (P) and arsenic (As) are implanted in order to obtain the second conductivity type (for example, n-type).

この半導体装置１０は、ゲート電極１３と半導体基板１１の間に印加する電圧をオン／オフすることによって、ソース領域１４とドレイン領域１５の間に「電流が流れる状態“１”」と「電流が流れない状態“０”」の切り替えを行う。具体的には、ソース領域１４とドレイン領域１５との間に電圧が印加された状態で、高誘電率絶縁膜１２を介して、ゲート電極１３と半導体基板１１との間に電圧が印加されたとき、半導体基板１１と高誘電率絶縁膜１２との界面に電荷が湧き、チャネルと呼ばれる抵抗の小さい層が形成される。これにより、半導体基板１１の抵抗が高いために流れていなかった電流がソース領域１４からドレイン領域１５に流れる。   In this semiconductor device 10, by turning on / off a voltage applied between the gate electrode 13 and the semiconductor substrate 11, “a state where current flows“ 1 ”” and “current flows between the source region 14 and the drain region 15. The non-flowing state “0” is switched. Specifically, a voltage was applied between the gate electrode 13 and the semiconductor substrate 11 via the high dielectric constant insulating film 12 in a state where a voltage was applied between the source region 14 and the drain region 15. In some cases, electric charges are generated at the interface between the semiconductor substrate 11 and the high dielectric constant insulating film 12, and a layer having a low resistance called a channel is formed. As a result, a current that has not flowed due to the high resistance of the semiconductor substrate 11 flows from the source region 14 to the drain region 15.

続いて、半導体装置１０の製造方法の概略について説明する。ソース／ドレインがゲートより先に形成されるのか、ゲートより後に形成されるのかによって、製造方法の順番が異なるが、どちらの方法を用いても半導体装置１０が製造可能である。ここでは例としてソース／ドレインがゲートより後に形成される方法について説明する。   Then, the outline of the manufacturing method of the semiconductor device 10 is demonstrated. Although the order of the manufacturing method differs depending on whether the source / drain is formed before the gate or after the gate, the semiconductor device 10 can be manufactured by using either method. Here, a method in which the source / drain is formed after the gate will be described as an example.

まず、半導体基板１１上に、ＬＯＣＯＳ（Local Oxidation of Silicon）法により、素子領域と、素子分離領域を形成した後、所望の閾値電圧が得られるようにチャネル形成領域に例えばホウ素（Ｂ）等のｐ型不純物を導入する。その後、ゲート絶縁膜として半導体基板１１表面に高誘電率絶縁膜１２を形成する。高誘電率絶縁膜１２は、例えば、酸化ランタンを主成分とする材料から、パルスレーザー蒸着法（ＰＬＤ法：Pulsed Laser Deposition）、電子ビーム蒸着法などの成膜方法により形成される。その後、例えば金属あるいはポリシリコンを堆積した後、レジストを塗布してパターニングでゲート電極１３を所望の長さに加工する。ソース／ドレイン領域へのｎ型不純物の導入は、ポリシリコンの堆積の際、ゲート電極１３側壁部に残したＰＳＧ膜（Ｐ含有シリコン酸化膜）のリンの固相拡散により行う。以上の工程により半導体装置１０が製造される。   First, an element region and an element isolation region are formed on the semiconductor substrate 11 by a LOCOS (Local Oxidation of Silicon) method, and then, for example, boron (B) or the like is formed in the channel formation region so as to obtain a desired threshold voltage. A p-type impurity is introduced. Thereafter, a high dielectric constant insulating film 12 is formed on the surface of the semiconductor substrate 11 as a gate insulating film. The high dielectric constant insulating film 12 is formed by a film forming method such as a pulse laser deposition method (PLD method: Pulsed Laser Deposition) or an electron beam deposition method from a material containing lanthanum oxide as a main component, for example. Thereafter, for example, after depositing metal or polysilicon, a resist is applied and the gate electrode 13 is processed to a desired length by patterning. The n-type impurity is introduced into the source / drain regions by solid phase diffusion of phosphorus in the PSG film (P-containing silicon oxide film) left on the side wall of the gate electrode 13 during the deposition of polysilicon. The semiconductor device 10 is manufactured through the above steps.

次に、本発明を適用したコンデンサについて説明する。図４は、本発明の一実施形態に係るコンデンサの構造の概略を示す断面図である。このコンデンサ２０は、誘電体層である高誘電率絶縁膜２２を介して一対の電極２１、２３を対向配置したキャパシタ構造となっている。電極２１、２３には、それぞれ端子２４、２５が接続されており、この端子２４、２５を介して回路に接続される。   Next, a capacitor to which the present invention is applied will be described. FIG. 4 is a sectional view schematically showing the structure of the capacitor according to one embodiment of the present invention. The capacitor 20 has a capacitor structure in which a pair of electrodes 21 and 23 are arranged to face each other via a high dielectric constant insulating film 22 which is a dielectric layer. Terminals 24 and 25 are connected to the electrodes 21 and 23, respectively, and are connected to the circuit via the terminals 24 and 25.

ＭＩＭ(Metal/Insulator/Metal）構造やＭＩＳ(Metal/Insulator/Semiconductor)構造のキャパシタに応じて、電極２１、２３には、Ｐｔ（白金）、Ｒｕ（ルビジウム）等の金属やシリコン、ポリシリコン等の半導体が用いられる。   Depending on the capacitor of MIM (Metal / Insulator / Metal) structure or MIS (Metal / Insulator / Semiconductor) structure, the electrodes 21 and 23 are made of metal such as Pt (platinum), Ru (rubidium), silicon, polysilicon, etc. These semiconductors are used.

なお、誘電体層である高誘電率絶縁膜２２は、ゲート絶縁膜の高誘電率絶縁膜１２と同様であり、ここでは説明を省略する。また、コンデンサ２０は、樹脂や絶縁ワニス等でモールド又はコーティングされていてもよく、絶縁油中に保持されていてもよい。   The high dielectric constant insulating film 22 that is a dielectric layer is the same as the high dielectric constant insulating film 12 that is a gate insulating film, and a description thereof is omitted here. The capacitor 20 may be molded or coated with resin, insulating varnish, or the like, or may be held in insulating oil.

続いて、コンデンサ２０の製造方法の概略について説明する。まず、表面が平滑な基板の上に、例えば、Ｐｔ薄膜を成膜して下部の電極２３を形成する。Ｐｔ電極は、例えば、Ｐｔターゲットと基板間の距離を所定の距離にし、ターゲットに高周波電力を投入するスパッタリングにより形成される。このようにして形成した電極２３の上に、酸化ランタンを主成分とする高誘電率絶縁膜２２を成膜する。高誘電率絶縁膜２２は、例えば、酸化ランタンを主成分とする材料から、パルスレーザー蒸着法、電子ビーム蒸着法などの成膜方法により形成される。このとき所望の形状の高誘電率絶縁膜２２を得る場合、例えば成膜時に耐熱性の金属マスクを基板に密着させて固定し、その上に高誘電率絶縁膜２２を形成すればよい。次に、高誘電率絶縁膜２２の上に、上部の電極２１を成膜する。上部の電極２１は、下部の電極２３と同様に、例えば、Ｐｔターゲットと基板を所定の距離とし、ターゲットに高周波電力を投入するスパッタリングにより形成される。以上の工程によりコンデンサ２０が製造される。   Then, the outline of the manufacturing method of the capacitor | condenser 20 is demonstrated. First, a lower electrode 23 is formed by, for example, forming a Pt thin film on a substrate having a smooth surface. The Pt electrode is formed by sputtering, for example, by setting the distance between the Pt target and the substrate to a predetermined distance and supplying high frequency power to the target. On the electrode 23 thus formed, a high dielectric constant insulating film 22 containing lanthanum oxide as a main component is formed. The high dielectric constant insulating film 22 is formed, for example, from a material containing lanthanum oxide as a main component by a film forming method such as a pulse laser deposition method or an electron beam deposition method. At this time, when obtaining the high dielectric constant insulating film 22 having a desired shape, for example, a heat-resistant metal mask may be adhered and fixed to the substrate during film formation, and the high dielectric constant insulating film 22 may be formed thereon. Next, the upper electrode 21 is formed on the high dielectric constant insulating film 22. Similar to the lower electrode 23, the upper electrode 21 is formed, for example, by sputtering in which a Pt target and a substrate are set at a predetermined distance and high frequency power is supplied to the target. The capacitor 20 is manufactured through the above steps.

以下、実施例により本発明をさらに詳細に説明する。
（耐湿性）
３元コンポジションスプレッド法を用いてＬａ２Ｏ３の耐湿性について調べた。３元コンポジションスプレッド法は、例えば、特許３７５２５３４号公報に記載されているように、３つの基礎物質からなる組成のすべての混合体を１回のプロセスで合成する方法であり、３元系、２元系、１元系のすべての相を形成することができる。 Hereinafter, the present invention will be described in more detail with reference to examples.
(Moisture resistance)
The moisture resistance of La 2 O 3 was examined using a ternary composition spread method. The ternary composition spread method is a method of synthesizing all mixtures of compositions composed of three basic substances in a single process, as described in, for example, Japanese Patent No. 375534, a ternary system, All phases of the binary system and the single system can be formed.

具体的には、材料蒸発機構と、マスク移動機構と、基板加熱装置と、基板回転機構とを有し、それらが全て自動制御される装置を用いて３元化合物を作製する。材料蒸発機構は、３種の材料を保持しており、そのうち１種の材料をエキシマレーザによって蒸発させる。マスク移動機構は、材料と基板の間で移動マスクをスライドさせて成長膜厚に傾斜をつける。基板加熱装置は、例えば、基板に対して均一に加熱する。基板回転機構は、基板を１２０度回転させ、材料毎に成長させる領域を変える。   Specifically, a ternary compound is produced using an apparatus that has a material evaporation mechanism, a mask moving mechanism, a substrate heating device, and a substrate rotation mechanism, all of which are automatically controlled. The material evaporation mechanism holds three types of materials, and one of the materials is evaporated by an excimer laser. The mask moving mechanism slides the moving mask between the material and the substrate to incline the growth film thickness. For example, the substrate heating device uniformly heats the substrate. The substrate rotation mechanism rotates the substrate by 120 degrees, and changes the growth region for each material.

この装置を用いて、まず、１種類目の材料を蒸発させ、マスク移動機構により移動マスクをスライドさせ、最大膜厚が１分子層になるように基板上に位置によって厚さの異なる膜を連続的に形成する。次に、基板回転機構により基板を１２０度回転させ、２種類目の材料を蒸発させ、マスク移動機構により移動マスクをスライドさせ、最大膜厚が１分子層になるように基板上に位置によって厚さの異なる膜を連続的に成長させる。次に、基板回転機構により基板を１２０度回転させ、３種類目の材料を蒸発させ、マスク移動機構により移動マスクをスライドさせ、最大膜厚が１分子層になるように基板上に位置によって厚さの異なる膜を連続的に成長させる。これにより、組成が連続的に異なる領域が形成される。ここで、材料を蒸発させるために、材料に対して照射するレーザとして、パルス出力が０．０６Ｊで、波長が２４８ｎｍのエキシマレーザ（ＫｒＦレーザ）を用いることができる。   Using this apparatus, first, the first type of material is evaporated, the moving mask is slid by the mask moving mechanism, and films having different thicknesses are continuously arranged on the substrate so that the maximum film thickness becomes one molecular layer. Form. Next, the substrate is rotated 120 degrees by the substrate rotating mechanism, the second type material is evaporated, the moving mask is slid by the mask moving mechanism, and the thickness is changed depending on the position on the substrate so that the maximum film thickness becomes one molecular layer. Continuously grow different thickness films. Next, the substrate is rotated by 120 degrees by the substrate rotating mechanism, the third type material is evaporated, the moving mask is slid by the mask moving mechanism, and the thickness is changed depending on the position on the substrate so that the maximum film thickness becomes one molecular layer. Continuously grow different thickness films. Thereby, the area | region from which a composition differs continuously is formed. Here, in order to evaporate the material, an excimer laser (KrF laser) having a pulse output of 0.06 J and a wavelength of 248 nm can be used as a laser with which the material is irradiated.

Ｌａ ２ Ｏ ３ −Ａｌ ２ Ｏ ３ −ＨｆＯ ２ の３元コンポジションスプレッド薄膜
３種類の材料として、Ｌａ２Ｏ３、Ａｌ２Ｏ３、及びＨｆＯ２を使用し、これらの材料を連続組成で混合させたＬａ２Ｏ３−Ａｌ２Ｏ３−ＨｆＯ２の３元コンポジションスプレッド薄膜を作製した。基板はシリコンで、堆積は基板温度３００℃で行った。３元混合領域及び単体膜領域の物理膜厚は、約１００ｎｍであった。 La 2 O 3 —Al 2 O 3 —HfO 2 ternary composition spread thin film Three types of materials are used: La 2 O 3 , Al 2 O 3 , and HfO 2 , and these materials are mixed in a continuous composition. A ternary composition spread thin film of La 2 O 3 —Al 2 O 3 —HfO 2 was prepared. The substrate was silicon and the deposition was performed at a substrate temperature of 300 ° C. The physical film thickness of the ternary mixed region and the single layer region was about 100 nm.

図５は、Ｌａ２Ｏ３−Ａｌ２Ｏ３−ＨｆＯ２の３元コンポジションスプレッド薄膜の３年経過後の写真を示すものであり、図６は、図５示す写真を模式的に示す図である。なお、薄膜は、作製後、室温で３年間放置した。 FIG. 5 shows a photograph of a ternary composition spread thin film of La 2 O 3 —Al 2 O 3 —HfO 2 after 3 years, and FIG. 6 is a diagram schematically showing the photograph shown in FIG. It is. The thin film was allowed to stand at room temperature for 3 years after production.

図５において、三角形ａｂｃはＬａ２Ｏ３−Ａｌ２Ｏ３−ＨｆＯ２の３元混合領域、三角形ａｂｄ、三角形ｂｃｅ、三角形ａｃｆは、それぞれＬａ２Ｏ３−ＨｆＯ２、Ａｌ２Ｏ３−ＨｆＯ２、Ｌａ２Ｏ３−Ａｌ２Ｏ３の２元混合領域を示している。例えば、線分ａｂにおいて、点ａはＬａ２Ｏ３が１００％であり、Ｌａ２Ｏ３が０％の点Ｂに近づくにつれて組成が徐々に減少する。 In FIG. 5, a triangle abc is a ternary mixed region of La 2 O 3 —Al 2 O 3 —HfO 2 , a triangle abd, a triangle bce, and a triangle acf are La 2 O 3 —HfO 2 and Al 2 O 3 —HfO, respectively. 2 shows a binary mixed region of La 2 O 3 —Al 2 O 3 . For example, in the line segment ab, La 2 O 3 is 100% at the point a, and the composition gradually decreases as it approaches the point B where La 2 O 3 is 0%.

このＬａ２Ｏ３−Ａｌ２Ｏ３−ＨｆＯ２の３元コンポジションスプレッド薄膜において、Ｌａ２Ｏ３の組成比が高い領域では、空気中の水分を吸収し、Ｌａ（ＯＨ）３粉末が形成されているのが観測できる。一方、Ａｌ２Ｏ３又はＨｆＯ２がアトミック比で２０％以上添加された領域では、粉末化がみられない。つまり、Ａｌ２Ｏ３又はＨｆＯ２がアトミック比で２０％添加された領域では、耐湿性が大きく改善されていることが分かる。 In this La 2 O 3 —Al 2 O 3 —HfO 2 ternary composition spread thin film, in the region where the composition ratio of La 2 O 3 is high, moisture in the air is absorbed and La (OH) 3 powder is formed. It can be observed. On the other hand, no powdering is observed in the region where Al 2 O 3 or HfO 2 is added in an atomic ratio of 20% or more. That is, it can be seen that the moisture resistance is greatly improved in a region where 20% Al 2 O 3 or HfO 2 is added at an atomic ratio.

しかし、図５に示したＬａ２Ｏ３−Ａｌ２Ｏ３−ＨｆＯ２の３元コンポジションスプレッド薄膜は、室温で３年間放置したものであり、実際のデバイス作成のときに、酸化ランタンを主成分とする高誘電率絶縁膜が大気に触れる時間はそんなに長くはない。つまり、酸化ランタンを主成分とする高誘電率絶縁膜は、作成プロセスの間だけ耐湿性を示せばよいので、他の金属の添加割合は２０％以下でも構わない。 However, the La 2 O 3 —Al 2 O 3 —HfO 2 ternary composition spread thin film shown in FIG. 5 was left at room temperature for 3 years. In actual device fabrication, lanthanum oxide was mainly used. The time that the high dielectric constant insulating film as a component is exposed to the atmosphere is not so long. In other words, the high dielectric constant insulating film containing lanthanum oxide as a main component only needs to show moisture resistance during the manufacturing process, so the addition ratio of other metals may be 20% or less.

以上、本発明を実施するための最良の形態について説明したが、本発明は上述した実施の形態のみに限定されるものではなく、本発明の要旨を逸脱しない範囲において種々の変更が可能であることは勿論である。   Although the best mode for carrying out the present invention has been described above, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. Of course.

本発明の一実施形態に係る半導体装置の構造の概略を示す断面図である。It is sectional drawing which shows the outline of the structure of the semiconductor device which concerns on one Embodiment of this invention. 高誘電率材料の誘電率ｋを示す図である。It is a figure which shows the dielectric constant k of a high dielectric constant material. 酸化ランタン絶縁膜の膜厚（EOT換算）対リーク電流特性を示すグラフである。It is a graph which shows the film thickness (EOT conversion) versus leakage current characteristic of a lanthanum oxide insulating film. 本発明の一実施形態に係るコンデンサの構造の概略を示す断面図である。It is sectional drawing which shows the outline of the structure of the capacitor | condenser which concerns on one Embodiment of this invention. Ｌａ２Ｏ３−Ａｌ２Ｏ３−ＨｆＯ２の３元コンポジションスプレッド薄膜の３年経過後の写真を示す図である。La is a diagram showing a photograph of three years after the 2 O 3 -Al 2 O 3 3-way composition spread thin -HfO 2. 図５に示す写真を模式的に示す図である。It is a figure which shows the photograph shown in FIG. 5 typically.

符号の説明Explanation of symbols

１０ 半導体装置、１１ 半導体基板、１２ 高誘電率絶縁膜、１３ ゲート電極、１４ ソース領域、１５ ドレイン領域、２０ コンデンサ、２１ 電極、２２ 高誘電率絶縁膜、２３ 電極、２４、２５ 端子   DESCRIPTION OF SYMBOLS 10 Semiconductor device, 11 Semiconductor substrate, 12 High dielectric constant insulating film, 13 Gate electrode, 14 Source region, 15 Drain region, 20 Capacitor, 21 Electrode, 22 High dielectric constant insulating film, 23 Electrode, 24, 25 terminal

Claims (2)

第１導電型の半導体基板と、
前記半導体基板上に形成された高誘電率絶縁膜と、
前記高誘電率絶縁膜上に形成されたゲート電極と、
前記半導体基板の前記ゲート電極下両側に形成され、第２導電型のソース／ドレイン領域とを備える半導体装置において、
前記高誘電率絶縁膜は、（Ｌａ１−ｘＭｘ）２Ｏ３（０．２≦ｘ≦０．３、ＭはＳｃ、Ｙ、Ｈｆ、Ｔｉの群から選ばれる１の金属）で表記される組成からなる
ことを特徴とする半導体装置。 A first conductivity type semiconductor substrate;
A high dielectric constant insulating film formed on the semiconductor substrate;
A gate electrode formed on the high dielectric constant insulating film;
In a semiconductor device comprising: a source / drain region of a second conductivity type formed on both sides of the semiconductor substrate below the gate electrode;
The high dielectric constant insulating film is represented by (La 1-x M x ) 2 O 3 ( 0.2 ≦ x ≦ 0.3, M is one metal selected from the group of Sc, Y, Hf, Ti) A semiconductor device comprising the following composition: 高誘電率絶縁膜を介して下部電極と上部電極とが対向形成されてなるコンデンサにおいて、
前記高誘電率絶縁膜は、（Ｌａ１−ｘＭｘ）２Ｏ３（０．２≦ｘ≦０．３、ＭはＳｃ、Ｙ、Ｈｆ、Ｔｉの群から選ばれる１の金属）で表記される組成からなる
ことを特徴とするコンデンサ。 In a capacitor in which a lower electrode and an upper electrode are formed to face each other through a high dielectric constant insulating film,
The high dielectric constant insulating film is represented by (La 1-x M x ) 2 O 3 ( 0.2 ≦ x ≦ 0.3, M is one metal selected from the group of Sc, Y, Hf, Ti) A capacitor comprising the following composition.
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