JP5121353B2 - オーバーモールドされたmcmicパッケージ及びその製造方法 - Google Patents
オーバーモールドされたmcmicパッケージ及びその製造方法 Download PDFInfo
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- JP5121353B2 JP5121353B2 JP2007212015A JP2007212015A JP5121353B2 JP 5121353 B2 JP5121353 B2 JP 5121353B2 JP 2007212015 A JP2007212015 A JP 2007212015A JP 2007212015 A JP2007212015 A JP 2007212015A JP 5121353 B2 JP5121353 B2 JP 5121353B2
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- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 239000004033 plastic Substances 0.000 description 9
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
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- 239000002322 conducting polymer Substances 0.000 description 2
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- 229920006332 epoxy adhesive Polymers 0.000 description 2
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- 229920000647 polyepoxide Polymers 0.000 description 1
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- 229910000679 solder Inorganic materials 0.000 description 1
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- 229920001187 thermosetting polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
ICデバイスのような電子デバイス用のパッケージングで広く用いられている形態は、プラスチック筐体である。典型的には、ICチップは基板に接着され、ポリマーがアセンブリの周囲を覆うように成形されてデバイスをオーバーモールドする。1つのオーバーモールドされたパッケージ内に2つ以上のICチップを組み込むことは一般的である。複数チップ・パッケージは、マルチ・チップ・モジュール(MCM)と称される。
本発明は、図面とともに考察することによって、より良く理解されるであろう。
Claims (10)
- a.基板と、
b.前記基板に取り付けられた、Nを少なくとも2とする、複数のN個の半導体ICデバイスと、
c.各ICデバイスに取り付けられ、上端と下端とを有し、前記下端を1つのICデバイスに取り付けられた複数のN個のヒート・シンクと、
d.前記N個の半導体ICデバイスおよび前記N個のヒート・シンクを封止し、露出された前記ヒート・シンクの前記上端とともに上部表面を形成するポリマー性のオーバーモールドと、
e.前記ヒート・シンクの前記露出された上端に選択的に付された第1のポリマー材料の複数のN個のプラグと、
f.第2のポリマー材料によって前記オーバーモールドに取り付けられた蓋と、
を具備するオーバーモールドされたMCM ICパッケージ。 - 前記第2のポリマー材料は、前記オーバーモールドおよび前記プラグの両方を覆うように付された接着性熱インターフェース材料(TIM)である、請求項1に記載のパッケージ。
- 前記プラグを覆うことなく前記オーバーモールドに選択的に付された接着性ポリマーをさらに含む、請求項1に記載のパッケージ。
- 前記第1のポリマー材料は、0.7W/mKを超える熱伝導率を有する、請求項1に記載のパッケージ。
- 前記第2のポリマー材料は、0.3W/mK未満の熱伝導率を有する、請求項4に記載のパッケージ。
- a.Nを少なくとも2とするN個の半導体ICデバイスを基板に取り付けること、
b.各ICデバイスに1つのヒート・シンクが設けられるように、1つのICデバイスに取り付けられる下端および上端を有するN個のヒート・シンクを前記ICデバイスに取り付けること、
c.前記ヒート・シンクの上端を露出させながら前記ICデバイスおよび前記ヒート・シンクを封止するオーバーモールドを成形すること、
d.第1のポリマー材料からなる複数のN個のプラグを選択的に前記ヒート・シンクの前記露出された上端に付すこと、
e.第2のポリマー材料を前記オーバーモールドの表面に付すこと、および
f.前記第2のポリマー材料に蓋を付すこと、
を含む、オーバーモールドされたMCM ICパッケージの製造方法。 - 前記第1および第2のポリマー材料が付され、前記蓋が付され、次いで前記第1および第2の材料が同じ硬化工程で硬化させられる、請求項6に記載の方法。
- 前記第2のポリマー材料は、前記オーバーモールドおよび前記第1のポリマー材料を覆うように付される、請求項6に記載の方法。
- 前記第1のポリマー材料は、0.7W/mKを超える熱伝導率を有する、請求項6に記載の方法。
- 前記第2のポリマー材料は、0.3W/mK未満の熱伝導率を有する、請求項9に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/505152 | 2006-08-16 | ||
US11/505,152 US7423341B2 (en) | 2006-08-16 | 2006-08-16 | Plastic overmolded packages with mechanically decoupled lid attach attachment |
Publications (3)
Publication Number | Publication Date |
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JP2008047918A JP2008047918A (ja) | 2008-02-28 |
JP2008047918A5 JP2008047918A5 (ja) | 2010-07-22 |
JP5121353B2 true JP5121353B2 (ja) | 2013-01-16 |
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Application Number | Title | Priority Date | Filing Date |
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JP2007212015A Active JP5121353B2 (ja) | 2006-08-16 | 2007-08-16 | オーバーモールドされたmcmicパッケージ及びその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7423341B2 (ja) |
JP (1) | JP5121353B2 (ja) |
KR (1) | KR101398404B1 (ja) |
CN (1) | CN101127349B (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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US7423341B2 (en) * | 2006-08-16 | 2008-09-09 | Agere Systems Inc. | Plastic overmolded packages with mechanically decoupled lid attach attachment |
KR101221807B1 (ko) * | 2006-12-29 | 2013-01-14 | 페어차일드코리아반도체 주식회사 | 전력 소자 패키지 |
US8459219B2 (en) | 2007-08-10 | 2013-06-11 | Nissan Motor Co., Ltd. | Variable valve device |
US7781682B2 (en) * | 2008-03-31 | 2010-08-24 | Intel Corporation | Methods of fabricating multichip packages and structures formed thereby |
US7829390B2 (en) * | 2008-11-20 | 2010-11-09 | Azurewave Technologies, Inc. | Packaging structure of SIP and a manufacturing method thereof |
US8362607B2 (en) * | 2009-06-03 | 2013-01-29 | Honeywell International Inc. | Integrated circuit package including a thermally and electrically conductive package lid |
FR2968126A1 (fr) * | 2010-11-29 | 2012-06-01 | St Microelectronics Grenoble 2 | Boitier semi-conducteur a via thermique et procédé de fabrication |
US9562534B2 (en) * | 2012-05-04 | 2017-02-07 | Ghsp, Inc. | In-line dual pump and motor with control device |
US9202772B2 (en) * | 2013-02-28 | 2015-12-01 | Altera Corporation | Heat pipe in overmolded flip chip package |
US20170356640A1 (en) | 2016-06-10 | 2017-12-14 | Innotec, Corp. | Illumination assembly including thermal energy management |
KR102617088B1 (ko) | 2019-09-18 | 2023-12-26 | 삼성전자주식회사 | 반도체 패키지 |
US20230137512A1 (en) * | 2021-11-03 | 2023-05-04 | Western Digital Technologies, Inc. | Stacked ssd semiconductor device |
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JPH06132425A (ja) * | 1992-10-22 | 1994-05-13 | Kyocera Corp | 半導体装置 |
JPH0758254A (ja) * | 1993-08-19 | 1995-03-03 | Fujitsu Ltd | マルチチップモジュール及びその製造方法 |
US5886408A (en) * | 1994-09-08 | 1999-03-23 | Fujitsu Limited | Multi-chip semiconductor device |
JPH0878618A (ja) * | 1994-09-08 | 1996-03-22 | Fujitsu Ltd | マルチチップモジュール及びその製造方法 |
US5610442A (en) * | 1995-03-27 | 1997-03-11 | Lsi Logic Corporation | Semiconductor device package fabrication method and apparatus |
JPH0964252A (ja) * | 1995-08-25 | 1997-03-07 | Hitachi Ltd | 半導体装置 |
US5587882A (en) * | 1995-08-30 | 1996-12-24 | Hewlett-Packard Company | Thermal interface for a heat sink and a plurality of integrated circuits mounted on a substrate |
US6238954B1 (en) * | 1999-09-28 | 2001-05-29 | Intel Corporation | COF packaged semiconductor |
US6535388B1 (en) * | 2001-10-04 | 2003-03-18 | Intel Corporation | Wirebonded microelectronic packages including heat dissipation devices for heat removal from active surfaces thereof |
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JP2004289059A (ja) | 2003-03-25 | 2004-10-14 | Denso Corp | 半導体装置 |
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EP1741136A2 (fr) * | 2004-04-13 | 2007-01-10 | SA Intexys | Procede de fabrication de circuits electroniques et optoelectroniques |
TWI246757B (en) * | 2004-10-27 | 2006-01-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with heat sink and fabrication method thereof |
US7332823B2 (en) * | 2005-12-15 | 2008-02-19 | Intel Corporation | Providing a metal layer in a semiconductor package |
US7332807B2 (en) * | 2005-12-30 | 2008-02-19 | Intel Corporation | Chip package thermal interface materials with dielectric obstructions for body-biasing, methods of using same, and systems containing same |
US7423341B2 (en) * | 2006-08-16 | 2008-09-09 | Agere Systems Inc. | Plastic overmolded packages with mechanically decoupled lid attach attachment |
-
2006
- 2006-08-16 US US11/505,152 patent/US7423341B2/en active Active
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2007
- 2007-06-21 CN CN2007101120369A patent/CN101127349B/zh active Active
- 2007-08-07 KR KR1020070079027A patent/KR101398404B1/ko active IP Right Grant
- 2007-08-16 JP JP2007212015A patent/JP5121353B2/ja active Active
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Also Published As
Publication number | Publication date |
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CN101127349B (zh) | 2011-11-16 |
JP2008047918A (ja) | 2008-02-28 |
US7423341B2 (en) | 2008-09-09 |
US7632717B2 (en) | 2009-12-15 |
US20080311700A1 (en) | 2008-12-18 |
KR101398404B1 (ko) | 2014-05-26 |
KR20080015725A (ko) | 2008-02-20 |
US20080042262A1 (en) | 2008-02-21 |
CN101127349A (zh) | 2008-02-20 |
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