JP5119756B2 - Wiring board - Google Patents

Wiring board Download PDF

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Publication number
JP5119756B2
JP5119756B2 JP2007157502A JP2007157502A JP5119756B2 JP 5119756 B2 JP5119756 B2 JP 5119756B2 JP 2007157502 A JP2007157502 A JP 2007157502A JP 2007157502 A JP2007157502 A JP 2007157502A JP 5119756 B2 JP5119756 B2 JP 5119756B2
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JP
Japan
Prior art keywords
wiring layer
insulating film
wiring
protective insulating
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007157502A
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Japanese (ja)
Other versions
JP2008034816A (en
Inventor
幸明 余郷
久則 与倉
秀哉 山寺
博文 船橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Toyota Central R&D Labs Inc
Original Assignee
Denso Corp
Toyota Central R&D Labs Inc
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Publication date
Application filed by Denso Corp, Toyota Central R&D Labs Inc filed Critical Denso Corp
Priority to JP2007157502A priority Critical patent/JP5119756B2/en
Priority to DE102007029873A priority patent/DE102007029873B4/en
Publication of JP2008034816A publication Critical patent/JP2008034816A/en
Application granted granted Critical
Publication of JP5119756B2 publication Critical patent/JP5119756B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P15/0802—Details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
    • G01L9/0041—Transmitting or indicating the displacement of flexible diaphragms
    • G01L9/0042—Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms
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Description

本発明は配線基板に係り、詳しくは、基板の表面上に配線層が多層に形成された多層構造の配線基板に関するものである。   The present invention relates to a wiring board, and more particularly to a wiring board having a multilayer structure in which wiring layers are formed in multiple layers on the surface of the board.

近年、半導体装置としてＭＥＭＳ（Micro Electro Mechanical Systems)技術を利用して作製された各種センサ（例えば、圧力センサ、加速度センサ、超音波センサなど）の需要がますます高まっている。
これらセンサは腐食性ガス（例えば、酸性ガスやアルカリ性ガスなど）の雰囲気中（腐食環境）で使用される場合がある。
例えば、圧力センサの用途には車両におけるエンジンの燃料噴射圧計測や排気圧計測などがあり、これらの計測では腐食性ガスである排気ガスの雰囲気中に圧力センサが晒される。 In recent years, the demand for various sensors (for example, pressure sensors, acceleration sensors, ultrasonic sensors, etc.) manufactured using MEMS (Micro Electro Mechanical Systems) technology as semiconductor devices is increasing.
These sensors may be used in an atmosphere (corrosive environment) of corrosive gas (for example, acid gas or alkaline gas).
For example, the application of the pressure sensor includes measurement of fuel injection pressure and exhaust pressure of an engine in a vehicle. In these measurements, the pressure sensor is exposed to an atmosphere of exhaust gas that is corrosive gas.

ところで、センサを構成する半導体チップの配線を外部へ引き出すための接続部材（ボンディングワイヤ、バンプ）は、半導体チップの配線層に形成された電極パッドに接続されている。
そのため、センサを腐食性ガス雰囲気中で使用する際に、センサ本体が腐食性ガスに直接晒される場合には、電極パッドも腐食性ガスに直接晒されることから、電極パッドが腐食に耐え切れずに断線不良を起こすおそれがある。 By the way, connecting members (bonding wires, bumps) for drawing the wiring of the semiconductor chip constituting the sensor to the outside are connected to electrode pads formed on the wiring layer of the semiconductor chip.
Therefore, when the sensor is used in a corrosive gas atmosphere, if the sensor body is directly exposed to corrosive gas, the electrode pad is also directly exposed to corrosive gas. May cause disconnection failure.

図２５（Ａ）は、センサを構成する従来の半導体チップ３００における電極パッドPadの近傍を示す要部概略縦断面図である。
半導体チップ３００は、半導体基板３０１、絶縁膜３０２，３０３、配線層３０４、電極パッドPadなどから構成されている。 FIG. 25A is a schematic vertical sectional view showing the main part of the vicinity of an electrode pad Pad in a conventional semiconductor chip 300 constituting the sensor.
The semiconductor chip 300 includes a semiconductor substrate 301, insulating films 302 and 303, a wiring layer 304, an electrode pad Pad, and the like.

半導体基板３０１の表面上には絶縁膜３０２が形成され、絶縁膜３０２の表面上には配線層３０４が形成され、絶縁膜３０２および配線層３０４の表面上には絶縁膜３０３が形成されている。そして、配線層３０４の表面の一部が絶縁膜３０３に開口形成された開口部３０３ａから露出し、その開口部３０３ａから露出した配線層３０４の表面によって電極パッドPadが形成されている。
尚、配線層３０４は、絶縁膜３０２に形成されたコンタクトホール（図示略）を介して半導体基板３０１に接続されている。 An insulating film 302 is formed on the surface of the semiconductor substrate 301, a wiring layer 304 is formed on the surface of the insulating film 302, and an insulating film 303 is formed on the surfaces of the insulating film 302 and the wiring layer 304. . A part of the surface of the wiring layer 304 is exposed from the opening 303a formed in the insulating film 303, and the electrode pad Pad is formed by the surface of the wiring layer 304 exposed from the opening 303a.
The wiring layer 304 is connected to the semiconductor substrate 301 via a contact hole (not shown) formed in the insulating film 302.

電極パッドPadには、半導体チップ３００の配線を外部へ引き出すための接続部材（図示略）が接続されている。尚、接続部材には、例えば、ワイヤボンディング（ボールボンディング）接続法で用いられるボンディングワイヤ（引出導線）や、フリップチップ（フェイスダウンボンディング）接続法で用いられるバンプなどがある。   A connection member (not shown) for drawing the wiring of the semiconductor chip 300 to the outside is connected to the electrode pad Pad. Examples of the connection member include a bonding wire (lead wire) used in a wire bonding (ball bonding) connection method and a bump used in a flip chip (face-down bonding) connection method.

半導体チップ３００が腐食性ガス雰囲気中に置かれると、電極パッドPadが腐食性ガスに直接晒される。
ここで、電極パッドPad（配線層３０４）が単層のアルミニウム系膜によって形成されている場合、アルミニウム系膜は腐食性ガスによって腐食され易いため、電極パッドPadが腐食に耐え切れずに断線不良を起こすおそれがある。
尚、アルミニウム系膜の形成材料としては、例えば、アルミニウム単体、アルミニウムにシリコンを添加したシリコンアルミニウム合金などがある。 When the semiconductor chip 300 is placed in a corrosive gas atmosphere, the electrode pad Pad is directly exposed to the corrosive gas.
Here, when the electrode pad Pad (wiring layer 304) is formed of a single layer aluminum-based film, the aluminum-based film is easily corroded by a corrosive gas. There is a risk of causing.
Examples of the material for forming the aluminum-based film include aluminum alone and a silicon aluminum alloy obtained by adding silicon to aluminum.

図２５（Ｂ）は、腐食性ガスに耐性がある保護配線層３１１，３１２で電極パッドPadを覆うようにした従来の半導体チップ３１０の要部概略縦断面図である。
半導体チップ３１０は、半導体基板３０１、絶縁膜３０２，３０３、配線層３０４、電極パッドPad、保護配線層３１１，３１２などから構成されている。
配線層３０４の表面上には各保護配線層３１１，３１２がこの順番で形成され、電極パッドPadの表面は２層の保護配線層３１１，３１２によって覆われている。 FIG. 25B is a schematic vertical cross-sectional view of a main part of a conventional semiconductor chip 310 in which the electrode pad Pad is covered with protective wiring layers 311 and 312 resistant to corrosive gas.
The semiconductor chip 310 includes a semiconductor substrate 301, insulating films 302 and 303, a wiring layer 304, an electrode pad Pad, protective wiring layers 311 and 312 and the like.
The protective wiring layers 311 and 312 are formed in this order on the surface of the wiring layer 304, and the surface of the electrode pad Pad is covered with the two protective wiring layers 311 and 312.

半導体チップ３１０では、保護配線層３１１，３１２が電極パッドPadを腐食性ガスから保護するバリア層として機能し、電極パッドPadが腐食性ガスに直接晒され無いため、電極パッドPadがアルミニウム系膜によって形成されている場合でも電極パッドPadの腐食をある程度まで防止できる。
ここで、保護配線層３１１の形成材料としては、例えば、各種高融点金属（ニッケル、チタン、タングステン、タンタルなど）の単体または合金（タングステンチタンなど）がある。
また、保護配線層３１２の形成材料としては、例えば金（Ａｕ）などがある。 In the semiconductor chip 310, the protective wiring layers 311 and 312 function as a barrier layer that protects the electrode pad Pad from a corrosive gas, and the electrode pad Pad is not directly exposed to the corrosive gas. Even when it is formed, corrosion of the electrode pad Pad can be prevented to some extent.
Here, as a forming material of the protective wiring layer 311, for example, there are single refractory metals (nickel, titanium, tungsten, tantalum, etc.) or alloys (tungsten titanium, etc.).
In addition, as a material for forming the protective wiring layer 312, for example, gold (Au) is used.

しかし、半導体チップ３１０が腐食性ガス雰囲気中に長時間晒された場合には、腐食性ガスが薄い各保護配線層３１１，３１２を透過して電極パッドPadを浸食するおそれがあり、耐食性に優れた各保護配線層３１１，３１２を用いても腐食性ガスから電極パッドPadを保護できないことがある。   However, when the semiconductor chip 310 is exposed to a corrosive gas atmosphere for a long time, the corrosive gas may permeate the thin protective wiring layers 311 and 312 and erode the electrode pad Pad, which is excellent in corrosion resistance. Further, even if each of the protective wiring layers 311 and 312 is used, the electrode pad Pad may not be protected from corrosive gas.

そこで、特許文献１に開示されるように、測定圧力を受圧するダイアフラムとケースとにより圧力検出室が区画形成されており、前記圧力検出室内には感圧部を有する半導体チップが設けられており、前記圧力検出室内には前記ダイアフラムが受圧した前記測定圧力を前記半導体チップに伝達する電気絶縁性の圧力伝達液体が封入された圧力センサが提案されている。   Therefore, as disclosed in Patent Document 1, a pressure detection chamber is defined by a diaphragm and a case for receiving a measurement pressure, and a semiconductor chip having a pressure sensing portion is provided in the pressure detection chamber. There has been proposed a pressure sensor in which an electrically insulating pressure transmission liquid for transmitting the measurement pressure received by the diaphragm to the semiconductor chip is enclosed in the pressure detection chamber.

また、特許文献２に開示されるように、ケースに配置されて圧力検出素子を有するセンサチップと、前記センサチップに形成された電極と、前記ケースに形成された外部出力用の端子を電気的に接続するフレキシブルプリント基板とを備え、前記電極および前記端子の接合部が熱可塑性樹脂により気密に封止された圧力センサが提案されている。
特開２００５−１８１０６６号公報（第１〜１１頁、図１） 特開２００５−２２７０３９号公報（第１〜１３頁、図１） Further, as disclosed in Patent Document 2, a sensor chip having a pressure detection element disposed in a case, an electrode formed on the sensor chip, and an external output terminal formed on the case are electrically connected. And a flexible printed circuit board connected to the pressure sensor, and a pressure sensor in which a joint between the electrode and the terminal is hermetically sealed with a thermoplastic resin has been proposed.
Japanese Patent Laying-Open No. 2005-181066 (pages 1 to 11, FIG. 1) Japanese Patent Laying-Open No. 2005-227039 (pages 1 to 13, FIG. 1)

特許文献１および特許文献２の技術には以下の問題点があった。
［問題点１］特許文献１の技術では、ダイアフラムおよび圧力伝達液体を介して半導体チップに圧力が伝達されるため、半導体チップに圧力を直接印加する場合に比べて、センサの感度が低下する。 The techniques of Patent Document 1 and Patent Document 2 have the following problems.
[Problem 1] In the technique of Patent Document 1, since the pressure is transmitted to the semiconductor chip via the diaphragm and the pressure transmission liquid, the sensitivity of the sensor is lower than when pressure is directly applied to the semiconductor chip.

［問題点２］特許文献１の技術では、ダイアフラムおよび圧力伝達液体を設ける分だけセンサの外形寸法が大きくなる。特許文献２の技術では、熱可塑性樹脂を設ける分だけセンサの外形寸法が大きくなる。   [Problem 2] In the technique of Patent Document 1, the outer dimensions of the sensor are increased by the provision of the diaphragm and the pressure transmission liquid. In the technique of Patent Document 2, the outer dimensions of the sensor are increased by the provision of the thermoplastic resin.

［問題点３］特許文献１の技術では、ダイアフラムおよび圧力伝達液体を設ける分だけセンサの製造コストが増大する。特許文献２の技術では、ケースおよび熱可塑性樹脂を設ける分だけセンサの製造コストが増大する。   [Problem 3] With the technique of Patent Document 1, the manufacturing cost of the sensor increases by providing the diaphragm and the pressure transmission liquid. In the technique of Patent Document 2, the manufacturing cost of the sensor increases by providing the case and the thermoplastic resin.

本発明は上記問題を解決するためになされたものであって、その目的は、腐食性ガス雰囲気中に置かれても電極パッドの腐食を防止可能であると共に、機能を阻害せずコンパクトな配線基板を低コストに提供することにある。   The present invention has been made in order to solve the above-described problems. The object of the present invention is to prevent the electrode pad from being corroded even when placed in a corrosive gas atmosphere, and to achieve a compact wiring without impairing the function. It is to provide a substrate at a low cost.

［課題を解決するための手段］および［発明の効果］に記載する（ ）内の符号等は、［発明を実施するための最良の形態］に記載する構成部材・構成要素の符号に対応したものである。   Reference numerals in parentheses described in [Means for Solving the Problems] and [Effects of the Invention] corresponded to reference numerals of components and components described in [Best Mode for Carrying Out the Invention]. Is.

請求項１に記載の発明は、
基板（１１）の表面上に形成された第１配線層（１５）と、
その第１配線層（１５）の上方に形成された第２配線層（１６）と、
その第２配線層（１６）を覆うように形成された保護絶縁膜（１４）と、
その保護絶縁膜（１４）に形成された開口部（１４ａ，１４ｂ）と、
その開口部（１４ａ，１４ｂ）に配置された電極パッド（Pad）と、
前記基板（１１）および前記第１配線層（１５）の表面上に形成された層間絶縁膜（１３）と、
その層間絶縁膜（１３）に形成されたビアホール（１３ａ）と、
前記第２配線層（１６）の下側全面および前記層間絶縁膜（１３）の表面上に形成された第３配線層（２１）と
を備えた配線基板（１０，２０，３０，４０，５０，６０，７０，８０，９０，１００，１１０，１２０，１３０，１４０，１５０，１６０，１７０，１８０，１９０，２００，２１０，２２０，２３０，２４０）であって、
前記保護絶縁膜（１４）の開口部（１４ａ，１４ｂ）と前記第１配線層（１５）とが基板（１１）の板厚方向にて重ならない位置に形成され、
前記第２配線層（１６）は前記第１配線層（１５）から離れた位置まで延出されて引き出され、その第２配線層（１６）における延出部分（１６ａ）は前記保護絶縁膜（１４）の開口部（１４ａ）から露出され、その開口部（１４ａ）から露出された第２配線層（１６）の延出部分（１６ａ）によって前記電極パッド（Pad）が形成され、
前記第２配線層（１６）は、前記層間絶縁膜（１３）の表面上および前記ビアホール（１３ａ）の内部に形成され、
前記保護絶縁膜（１４）は、前記層間絶縁膜（１３）および前記第２配線層（１６）の表面上に形成され、
前記第１配線層（１５）と前記第３配線層（２１）とは前記ビアホール（１３ａ）を介して接続され、
前記第１配線層（１５）と前記第２配線層（１６）とは、前記ビアホール（１３）の内部に充填された前記第３配線層（２１）を介して接続され、
前記第３配線層（２１）を介して前記層間絶縁膜（１３）と前記第２配線層（１６）が接着され、
前記ビアホール（１３ａ）の内部に前記第３配線層（２１）が充填されて埋め込まれていることを技術的特徴とする。
前記第２配線層（１６）は金から成り、
前記第３配線層（２１）はタンタルから成ることを技術的特徴とする。 The invention described in claim 1
A first wiring layer (15) formed on the surface of the substrate (11);
A second wiring layer (16) formed above the first wiring layer (15);
A protective insulating film (14) formed to cover the second wiring layer (16);
Openings (14a, 14b) formed in the protective insulating film (14);
An electrode pad (Pad) disposed in the opening (14a, 14b);
An interlayer insulating film (13) formed on the surfaces of the substrate (11) and the first wiring layer (15);
Via holes (13a) formed in the interlayer insulating film (13);
A wiring board (10, 20, 30, 40, 50) comprising a third wiring layer (21) formed on the entire lower surface of the second wiring layer (16) and on the surface of the interlayer insulating film (13). , 60, 70, 80, 90, 100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240),
The openings (14a, 14b) of the protective insulating film (14) and the first wiring layer (15) are formed at positions that do not overlap in the thickness direction of the substrate (11),
The second wiring layer (16) is extended to a position away from the first wiring layer (15), and the extended portion (16a) in the second wiring layer (16) is formed by the protective insulating film ( The electrode pad (Pad) is formed by the extended portion (16a) of the second wiring layer (16) exposed from the opening (14a) of 14) and exposed from the opening (14a),
The second wiring layer (16) is formed on the surface of the interlayer insulating film (13) and inside the via hole (13a),
The protective insulating film (14) is formed on the surface of the interlayer insulating film (13) and the second wiring layer (16),
The first wiring layer (15) and the third wiring layer (21) are connected via the via hole (13a),
The first wiring layer (15) and the second wiring layer (16) are connected via the third wiring layer (21) filled in the via hole (13),
The interlayer insulating film (13) and the second wiring layer (16) are bonded via the third wiring layer (21),
A technical feature is that the third wiring layer (21) is filled and buried in the via hole (13a).
The second wiring layer (16) is made of gold,
The third wiring layer (21) is technically characterized by being made of tantalum.

請求項２に記載の発明は、
請求項１に記載の配線基板において、
前記第２配線層（１６）の上側全面に形成された第４配線層（４１）を備え、
その第４配線層（４１）を介して前記第２配線層（１６）と前記保護絶縁膜（１４）が接着されることを技術的特徴とする。
The invention described in claim 2
The wiring board according to claim 1 ,
A fourth wiring layer (41) formed on the entire upper surface of the second wiring layer (16);
A technical feature is that the second wiring layer (16) and the protective insulating film (14) are bonded via the fourth wiring layer (41).

請求項３に記載の発明は、
請求項１に記載の配線基板において、
前記保護絶縁膜（１４）の開口部（１４ａ）の内部を除く前記第２配線層（１６）の上側に形成された第５配線層（９１）を備え、
その第５配線層（９１）を介して前記第２配線層（１６）と前記保護絶縁膜（１４）が接着され、
前記保護絶縁膜（１４）の開口部（１４ａ）の内周壁面に位置する前記第５配線層（９１）の端面（９１ａ）は前記保護絶縁膜（１４）によって覆われ、
前記保護絶縁膜（１４）の開口部（１４ａ）から前記第２配線層（１６）が直接露出していることを技術的特徴とする。
The invention according to claim 3
The wiring board according to claim 1 ,
A fifth wiring layer (91) formed above the second wiring layer (16) excluding the inside of the opening (14a) of the protective insulating film (14);
The second wiring layer (16) and the protective insulating film (14) are bonded via the fifth wiring layer (91),
The end surface (91a) of the fifth wiring layer (91) located on the inner peripheral wall surface of the opening (14a) of the protective insulating film (14) is covered with the protective insulating film (14),
A technical feature is that the second wiring layer (16) is directly exposed from the opening (14a) of the protective insulating film (14).

請求項４に記載の発明は、
請求項２に記載の配線基板において、
前記第２配線層（１６）は金から成り、
前記第４配線層（４１）はタンタルまたはタングステンチタンから成ることを技術的特徴とする。
The invention according to claim 4
The wiring board according to claim 2 ,
The second wiring layer (16) is made of gold,
The fourth wiring layer (41) is technically characterized by being made of tantalum or tungsten titanium.

請求項５に記載の発明は、
請求項３に記載の配線基板において、
前記第２配線層（１６）は金から成り、
前記第５配線層（９１）はタンタルまたはタングステンチタンから成ることを技術的特徴とする。
The invention described in claim 5
The wiring board according to claim 3 ,
The second wiring layer (16) is made of gold,
The fifth wiring layer (91) is technically characterized by being made of tantalum or tungsten titanium.

請求項６に記載の発明は、
請求項１のいずれか１項に記載の配線基板において、
前記保護絶縁膜（１４）の開口部の内部を除く前記第２配線層（１６）の上側に形成された第２接着層（６１）を備え、
その第２接着層（６１）を介して前記第２配線層（１６）と前記保護絶縁膜（１４）が接着され、
前記保護絶縁膜（１４）の開口部（１４ａ）から前記第２配線層（１６）が直接露出していることを技術的特徴とする。
The invention described in claim 6
The wiring board according to claim 1 ,
A second adhesive layer (61) formed on the upper side of the second wiring layer (16) excluding the inside of the opening of the protective insulating film (14);
The second wiring layer (16) and the protective insulating film (14) are bonded via the second adhesive layer (61),
A technical feature is that the second wiring layer (16) is directly exposed from the opening (14a) of the protective insulating film (14).

請求項７に記載の発明は、
請求項１〜６のいずれか１項に記載の配線基板において、
前記電極パッド（Pad）に対してワイヤボンディング接続法を用いて接続されたボンディングワイヤ（５１）を備えたことを技術的特徴とする。
The invention described in claim 7
In the wiring board according to any one of claims 1 to 6 ,
A technical feature is that a bonding wire (51) connected to the electrode pad (Pad) using a wire bonding connection method is provided.

請求項８に記載の発明は、
請求項１〜６のいずれか１項に記載の配線基板において、
前記電極パッド（Pad）に対してフリップチップ接続法を用いて接続されたバンプ（５２）を備えたことを技術的特徴とする。
The invention according to claim 8 provides:
In the wiring board according to any one of claims 1 to 6 ,
A technical feature is that a bump (52) connected to the electrode pad (Pad) using a flip chip connection method is provided.

請求項９に記載の発明は、
請求項１〜８のいずれか１項に記載の配線基板において、
前記配線基板（８０）はセンサ（１００，１１０）を構成することを技術的特徴とする。
The invention according to claim 9 is:
In the wiring board according to any one of claims 1 to 8 ,
The wiring board (80) constitutes a sensor (100, 110) as a technical feature.

請求項１０に記載の発明は、
請求項１〜８のいずれか１項に記載の配線基板において、
前記配線基板（１４０）はパワー素子（１８０，２００）を構成することを技術的特徴とする。
The invention according to claim 10 is:
In the wiring board according to any one of claims 1 to 8 ,
The wiring board (140) constitutes a power element (180, 200) as a technical feature.

＜請求項１＞
請求項１の発明では、第１配線層（１５）の表面が第２配線層（１６）および保護絶縁膜（１４）によって覆われており、第１配線層（１５）の表面が露出していない。
そのため、配線基板が腐食性ガス雰囲気中に置かれても、第１配線層（１５）が腐食性ガスに直接晒されることがなく、腐食性ガスによって腐食され易い材料（例えばアルミニウム系膜など）によって第１配線層（１５）を形成したとしても第１配線層は腐食されない。 <Claim 1>
In the invention of claim 1, the surface of the first wiring layer (15) is covered with the second wiring layer (16) and the protective insulating film (14), and the surface of the first wiring layer (15) is exposed. Absent.
Therefore, even when the wiring board is placed in a corrosive gas atmosphere, the first wiring layer (15) is not directly exposed to the corrosive gas, and is easily corroded by the corrosive gas (for example, an aluminum film). Even if the first wiring layer (15) is formed by the above, the first wiring layer is not corroded.

また、請求項１の発明では、第２配線層（１６）の一部が保護絶縁膜（１４）の開口部（１４ａ，１４ｂ）から露出して電極パッド（Pad）が形成されている。
そのため、配線基板が腐食性ガス雰囲気中に置かれると、電極パッド（Pad）が腐食性ガスに直接晒される。そこで、配線基板が置かれる腐食性ガス雰囲気に耐性のある導電材料で第２配線層（１６）を形成しておけば、電極パッド（Pad）は第２配線層（１６）の一部であるため、腐食性ガスにより電極パッドが腐食されることはなく、電極パッドの断線不良を防止できる。 According to the first aspect of the present invention, a part of the second wiring layer (16) is exposed from the openings (14a, 14b) of the protective insulating film (14) to form electrode pads (Pad).
Therefore, when the wiring board is placed in a corrosive gas atmosphere, the electrode pad (Pad) is directly exposed to the corrosive gas. Therefore, if the second wiring layer (16) is formed of a conductive material resistant to the corrosive gas atmosphere on which the wiring board is placed, the electrode pad (Pad) is a part of the second wiring layer (16). Therefore, the electrode pad is not corroded by the corrosive gas, and disconnection failure of the electrode pad can be prevented.

ここで、保護絶縁膜（１４）の開口部（１４ａ，１４ｂ）と第１配線層（１５）とが基板（１１）の板厚方向（上下方向）にて重なる場合には、配線基板が腐食性ガス雰囲気中に置かれたときに、腐食性ガスが保護絶縁膜（１４）の開口部（１４ａ，１４ｂ）から第２配線層（１６）を通って第１配線層（１５）に到達し、腐食性ガスによって第１配線層（１５）が腐食されるおそれがある。   Here, when the opening (14a, 14b) of the protective insulating film (14) and the first wiring layer (15) overlap in the thickness direction (vertical direction) of the substrate (11), the wiring substrate is corroded. When placed in a reactive gas atmosphere, corrosive gas reaches the first wiring layer (15) from the openings (14a, 14b) of the protective insulating film (14) through the second wiring layer (16). The first wiring layer (15) may be corroded by the corrosive gas.

しかし、請求項１の発明では、保護絶縁膜（１４）の開口部（１４ａ，１４ｂ）と第１配線層（１５）とが基板（１１）の板厚方向（上下方向）にて重ならない位置に形成されている。
従って、請求項１の発明によれば、配線基板が腐食性ガス雰囲気中に置かれたときに、腐食性ガスが保護絶縁膜（１４）の開口部（１４ａ，１４ｂ）から第２配線層（１６）を通って第１配線層（１５）に到達することがなく、その腐食性ガスによって第１配線層（１５）が腐食されるおそれもない。 However, in the first aspect of the invention, the opening (14a, 14b) of the protective insulating film (14) and the first wiring layer (15) do not overlap in the thickness direction (vertical direction) of the substrate (11). Is formed.
Therefore, according to the first aspect of the present invention, when the wiring board is placed in a corrosive gas atmosphere, the corrosive gas flows from the openings (14a, 14b) of the protective insulating film (14) to the second wiring layer (14a, 14b). 16), the first wiring layer (15) is not reached, and the corrosive gas does not cause the first wiring layer (15) to be corroded.

ところで、請求項１の配線基板を用いて圧力センサを構成した場合には、特許文献１のようにダイアフラムおよび圧力伝達液体を介して配線基板に形成された半導体チップに圧力を伝達させる必要が無く、腐食性ガス雰囲気中に置かれた配線基板に形成された半導体チップ（８０）に圧力を直接印加可能であるため、前記した［問題点１］を解決できる。
すなわち、請求項１の配線基板を用いて圧力センサを構成した場合には、圧力センサの機能であるセンサの感度の低下を防止可能になり、当該機能が阻害されない。 By the way, when the pressure sensor is configured using the wiring board according to claim 1, there is no need to transmit the pressure to the semiconductor chip formed on the wiring board via the diaphragm and the pressure transmission liquid as in Patent Document 1. Since the pressure can be directly applied to the semiconductor chip (80) formed on the wiring board placed in the corrosive gas atmosphere, the above [Problem 1] can be solved.
That is, when a pressure sensor is configured using the wiring board according to claim 1, it is possible to prevent a decrease in the sensitivity of the sensor, which is a function of the pressure sensor, and the function is not hindered.

また、請求項１の配線基板を用いて各種センサ（例えば、圧力センサ、加速度センサ、超音波センサなど）を構成した場合には、特許文献１のようにダイアフラムおよび圧力伝達液体を設ける必要や、特許文献２のように熱可塑性樹脂を設ける必要が無く、センサの外形寸法が大きくならないため、前記した［問題点２］を解決できる。   When various sensors (for example, a pressure sensor, an acceleration sensor, an ultrasonic sensor, etc.) are configured using the wiring board according to claim 1, it is necessary to provide a diaphragm and a pressure transmission liquid as in Patent Document 1, Since there is no need to provide a thermoplastic resin as in Patent Document 2 and the outer dimensions of the sensor do not increase, the above [Problem 2] can be solved.

さらに、請求項１の配線基板を用いて前記した各種センサを構成した場合には、特許文献１のようにダイアフラムおよび圧力伝達液体を設ける必要や、特許文献２のように熱可塑性樹脂を設ける必要が無く、センサの製造コストが増大しないため、前記した［問題点３］を解決できる。   Further, when the various sensors described above are configured using the wiring board according to claim 1, it is necessary to provide a diaphragm and a pressure transmission liquid as in Patent Document 1 or a thermoplastic resin as in Patent Document 2 Since the manufacturing cost of the sensor does not increase, the above [Problem 3] can be solved.

また、請求項１の発明では、第２配線層（１６）が第１配線層（１５）から離れた位置まで延出されて引き出され、その第２配線層の延出部分（１６ａ）の一部が保護絶縁膜（１４）の開口部（１４ａ）から露出して電極パッド（Pad）が形成されているため、保護絶縁膜（１４）の開口部（１４ａ）と第１配線層（１５）とが基板（１１）の板厚方向（上下方向）にて重なることはない（第１〜第１５，第２２実施形態に該当）。
 According to the first aspect of the present invention, the second wiring layer (16) is extended to a position distant from the first wiring layer (15) and is drawn out, and one extension portion (16a) of the second wiring layer is extracted. Since the electrode pad (Pad) is formed by exposing the portion from the opening (14a) of the protective insulating film (14), the opening (14a) of the protective insulating film (14) and the first wiring layer (15) Do not overlap in the thickness direction (vertical direction) of the substrate (11) ( corresponding to the first to fifteenth and twenty-second embodiments) .

また、請求項１の発明では、第２配線層（１６）が層間絶縁膜（１３）のビアホール（１３ａ）にて第１配線層（１５）と接続され、その第２配線層が第１配線層から離れた位置まで延出されて引き出され、その第２配線層の延出部分（１６ａ）の一部が保護絶縁膜（１４）の開口部（１４ａ）から露出して電極パッド（Pad）が形成されている（第１〜第１５実施形態に該当）。
そのため、請求項１の発明では、保護絶縁膜（１４）の開口部（１４ａ）とビアホール（１３ａ）および第１配線層（１５）とが基板（１１）の板厚方向（上下方向）にて重なることはない。
 In the invention of claim 1 , the second wiring layer (16) is connected to the first wiring layer (15) through the via hole (13a) of the interlayer insulating film (13), and the second wiring layer is connected to the first wiring layer. A part of the extension part (16a) of the second wiring layer is exposed from the opening part (14a) of the protective insulating film (14) and is extended to a position away from the layer, and is exposed to an electrode pad (Pad). (Corresponding to the first to fifteenth embodiments) .
Therefore, in the invention of claim 1 , the opening (14a) of the protective insulating film (14), the via hole (13a), and the first wiring layer (15) are arranged in the plate thickness direction (vertical direction) of the substrate (11). There is no overlap.

従って、請求項１の発明によれば、配線基板が腐食性ガス雰囲気中に置かれたときに、腐食性ガスが保護絶縁膜（１４）の開口部（１４ａ，１４ｂ）からビアホール（１３ａ）を通って第１配線層（１５）に到達することがなく、その腐食性ガスによって第１配線層（１５）が腐食されるおそれもない。
Therefore, according to the invention of claim 1 , when the wiring board is placed in a corrosive gas atmosphere, the corrosive gas passes through the via holes (13a) from the openings (14a, 14b) of the protective insulating film (14). There is no possibility that the first wiring layer (15) passes through and the first wiring layer (15) is not corroded by the corrosive gas.

また、請求項１の発明において、層間絶縁膜（１３）との密着性に優れると共に、各配線層（１５，１６）と確実に接続されて良好な導通が得られる導電材料を第３配線層（２１）の形成材料に用いれば、第２配線層（１６）の形成材料に層間絶縁膜との密着性が低い導電材料を用いた場合でも、第３配線層が第２配線層と層間絶縁膜を接着する接着層（密着層）として機能する。
In the first aspect of the invention, a conductive material that is excellent in adhesion to the interlayer insulating film (13) and that is reliably connected to each wiring layer (15, 16) to obtain good conduction is provided in the third wiring layer. When used as the forming material of (21), even when a conductive material having low adhesion to the interlayer insulating film is used as the forming material of the second wiring layer (16), the third wiring layer is insulated from the second wiring layer and the interlayer insulation. It functions as an adhesive layer (adhesion layer) for adhering the film .

また、請求項１の発明では、ビアホール（１３ａ）の内部に第３配線層（２１）が充填されて埋め込まれているため、ビアホール１３ａの上方における第３配線層（２１）の表面が略平坦になり、第３配線層（２１）の上側に形成する第２配線層（１６）によってビアホール（１３ａ）を充填する必要が無くなる（第１０実施形態に該当）。
従って、請求項１の発明によれば、第２配線層（１６）の形成材料や形成方法として段差被覆性が低いものを使用した場合でも、第３配線層（２１）を介して第１配線層（１５）と第２配線層（１６）との良好な導通が得られる。
 In the invention of claim 1 , since the third wiring layer (21) is filled and buried inside the via hole (13a), the surface of the third wiring layer (21) above the via hole 13a is substantially flat. Thus, it is not necessary to fill the via hole (13a) with the second wiring layer (16) formed above the third wiring layer (21) (corresponding to the tenth embodiment) .
Therefore, according to the first aspect of the present invention, even when a material having a low step coverage is used as the forming material or forming method of the second wiring layer (16), the first wiring is interposed via the third wiring layer (21). Good conduction between the layer (15) and the second wiring layer (16) is obtained.

ところで、第２配線層（１６）の形成材料として金を用いた場合、金は導電性に優れるもの層間絶縁膜（１３）との密着性に劣るという欠点がある。
そこで、請求項１の発明では、第３配線層（２１）の形成材料としてタンタルを用いる（第２，第４，第６，第１０，第１１実施形態に該当）。
タンタルは、金に対して電気抵抗が大きいという欠点があるが、層間絶縁膜（１３）との密着性に優れ、第２配線層（１６）の形成材料である金と確実に接続されて良好な導通が得られる上に、耐腐食性に優れているため、第３配線層（２１）の形成材料として好適である。
 By the way, when gold is used as the forming material of the second wiring layer (16), there is a disadvantage that gold is inferior in adhesion with the interlayer insulating film (13) although it is excellent in conductivity.
Therefore, in the first aspect of the invention, tantalum is used as the material for forming the third wiring layer (21) (corresponding to the second, fourth, sixth, tenth and eleventh embodiments) .
Tantalum has a drawback that it has a large electric resistance with respect to gold, but it has excellent adhesion to the interlayer insulating film (13) and is well connected to gold as a material for forming the second wiring layer (16). It is suitable as a material for forming the third wiring layer (21) because it provides excellent conduction and is excellent in corrosion resistance.

＜請求項２：第４，第５，第８，第９実施形態に該当＞
請求項２の発明において、保護絶縁膜（１４）との密着性に優れると共に、第２配線層（１６）と確実に接続されて良好な導通が得られる導電材料を第４配線層（４１）の形成材料に用いれば、第２配線層の形成材料に保護絶縁膜との密着性が低い導電材料を用いた場合でも、第４配線層が第２配線層と保護絶縁膜を接着する接着層（密着層）として機能するため、請求項１の発明の前記作用・効果と同様の作用・効果が得られる。
< Claim 2 : Corresponds to the fourth, fifth, eighth, and ninth embodiments>
In the invention of claim 2 , a conductive material that has excellent adhesion to the protective insulating film (14) and is reliably connected to the second wiring layer (16) to obtain good conduction is provided in the fourth wiring layer (41). If the conductive material having low adhesion to the protective insulating film is used as the second wiring layer forming material, the fourth wiring layer adheres the second wiring layer and the protective insulating film. Since it functions as an (adhesion layer), the same function / effect as the function / effect of the invention of claim 1 can be obtained.

＜請求項３：第１１実施形態に該当＞
請求項３の発明において、保護絶縁膜（１４）との密着性に優れると共に、第２配線層（１６）と確実に接続されて良好な導通が得られる導電材料を第５配線層（９１）の形成材料に用いれば、第２配線層の形成材料に保護絶縁膜との密着性が低い導電材料を用いた場合でも、第５配線層が第２配線層と保護絶縁膜を接着する接着層（密着層）として機能するため、請求項２の発明の前記作用・効果と同様の作用・効果が得られる。
< Claim 3 : Corresponds to the eleventh embodiment>
In the invention of claim 3 , a conductive material that is excellent in adhesion to the protective insulating film (14) and that is reliably connected to the second wiring layer (16) to obtain good conduction is provided in the fifth wiring layer (91). If the conductive material having a low adhesion to the protective insulating film is used as the second wiring layer forming material, the fifth wiring layer adheres the second wiring layer and the protective insulating film. Since it functions as an (adhesion layer), the same functions and effects as those of the invention of claim 2 can be obtained.

そして、請求項３の発明では、第５配線層（９１）は、保護絶縁膜（１４）の開口部（１４ａ）の内部を除く第２配線層（１６）の上側に形成されている。また、保護絶縁膜（１４）の開口部（１４ａ）の内周壁面に位置する第５配線層（９１）の端面（９１ａ）は、保護絶縁膜（１４）によって覆われている。
従って、請求項３の発明によれば、第５配線層（９１）が露出せず、第５配線層（９１）が腐食性ガスに晒されるおそれが無いため、第５配線層の形成材料に耐腐食性が低いものを使用可能になる。
In the invention of claim 3 , the fifth wiring layer (91) is formed above the second wiring layer (16) excluding the inside of the opening (14a) of the protective insulating film (14). The end surface (91a) of the fifth wiring layer (91) located on the inner peripheral wall surface of the opening (14a) of the protective insulating film (14) is covered with the protective insulating film (14).
Therefore, according to the invention of claim 3 , the fifth wiring layer (91) is not exposed and the fifth wiring layer (91) is not exposed to corrosive gas. The one with low corrosion resistance can be used.

＜請求項４：第４，第５，第８，第９実施形態に該当＞
第２配線層（１６）の形成材料として金を用いた場合、金は導電性に優れるもの保護絶縁膜（１４）との密着性に劣るという欠点がある。
そこで、請求項４の発明では、第４配線層（４１）の形成材料としてタンタルまたはタングステンチタンを用いる。
タンタルまたはタングステンチタンは、金に対して電気抵抗が大きいという欠点があるが、保護絶縁膜（１４）との密着性に優れ、第２配線層（１６）の形成材料である金と確実に接続されて良好な導通が得られる上に、耐腐食性に優れているため、第４配線層（４１）の形成材料として好適である。
< Claim 4 : Corresponding to Fourth, Fifth, Eighth and Ninth Embodiments>
When gold is used as the material for forming the second wiring layer (16), the gold has a drawback that it is excellent in conductivity but inferior in adhesion to the protective insulating film (14).
Accordingly, in the invention of claim 4 , tantalum or tungsten titanium is used as a material for forming the fourth wiring layer (41).
Tantalum or tungsten titanium has a drawback that it has a large electric resistance with respect to gold, but has excellent adhesion to the protective insulating film (14) and is reliably connected to gold, which is a material for forming the second wiring layer (16). As a result, good conduction is obtained and the corrosion resistance is excellent, so that it is suitable as a material for forming the fourth wiring layer (41).

＜請求項５：第１１実施形態に該当＞
第２配線層（１６）の形成材料として金を用いた場合、金は導電性に優れるもの保護絶縁膜（１４）との密着性に劣るという欠点がある。
そこで、請求項５の発明では、第５配線層（９１）の形成材料としてタンタルまたはタングステンチタンを用いる。
タンタルまたはタングステンチタンは、金に対して電気抵抗が大きいという欠点があるが、保護絶縁膜（１４）との密着性に優れ、第２配線層（１６）の形成材料である金と確実に接続されて良好な導通が得られる上に、耐腐食性に優れているため、第５配線層（９１）の形成材料として好適である。
< Claim 5 : Corresponds to the eleventh embodiment>
When gold is used as the material for forming the second wiring layer (16), the gold has a drawback that it is excellent in conductivity but inferior in adhesion to the protective insulating film (14).
Therefore, in the invention of claim 5 , tantalum or tungsten titanium is used as a material for forming the fifth wiring layer (91).
Tantalum or tungsten titanium has a drawback that it has a large electric resistance with respect to gold, but has excellent adhesion to the protective insulating film (14) and is reliably connected to gold, which is a material for forming the second wiring layer (16). In addition to being able to obtain good conduction, and being excellent in corrosion resistance, it is suitable as a material for forming the fifth wiring layer (91).

＜請求項６：第６，第７実施形態に該当＞
請求項６の発明において、保護絶縁膜（１４）および第２配線層（１６）との密着性に優れた材料を用いて第２接着層（６１）を形成すれば、第２配線層（１６）の形成材料に保護絶縁膜との密着性が低い導電材料を用いた場合でも、第２配線層と保護絶縁膜が第２接着層によって接着されるため、請求項１の発明の前記作用・効果と同様の作用・効果が得られる。
< Claim 6 : Corresponds to sixth and seventh embodiments>
In the invention of claim 6 , if the second adhesive layer (61) is formed using a material having excellent adhesion to the protective insulating film (14) and the second wiring layer (16), the second wiring layer (16 Even if a conductive material having low adhesion to the protective insulating film is used as the forming material of (), the second wiring layer and the protective insulating film are bonded together by the second adhesive layer. The same action and effect as the effect can be obtained.

ところで、請求項２の発明では、電極パッド（Pad）の表面が第４配線層（４１）によって形成されている。それに対して、請求項３または請求項６の発明では、電極パッドの表面が第２配線層によって形成されている。
従って、請求項３または請求項６の発明では、電極パッドに接続される接続部材（ボンディングワイヤ、バンプ）が第２配線層に直接接触することから、請求項２の発明における第４配線層を設けた場合に比べて、接続部材と第２配線層の接触抵抗が低くなり、接続部材と第２配線層の接続部分の面積を小さくすることが可能になるため、基板（１１）の表面上における電極パッドの占有面積を縮小して配線基板を小型化できる。
By the way, in the invention of claim 2 , the surface of the electrode pad (Pad) is formed by the fourth wiring layer (41). On the other hand, in the invention of claim 3 or claim 6 , the surface of the electrode pad is formed by the second wiring layer.
Therefore, in the invention of claim 3 or claim 6 , since the connection member (bonding wire, bump) connected to the electrode pad is in direct contact with the second wiring layer, the fourth wiring layer in the invention of claim 2 is provided. Since the contact resistance between the connection member and the second wiring layer is lower than that in the case where the connection member is provided, the area of the connection portion between the connection member and the second wiring layer can be reduced. The area occupied by the electrode pads can be reduced to reduce the size of the wiring board.

＜請求項７：第８実施形態に該当＞
請求項７の発明では、電極パッド（Pad）に対してワイヤボンディング接続法を用いて接続されたボンディングワイヤ（５１）を備えた配線基板を実現できる。
< Claim 7 : Corresponds to the eighth embodiment>
In the invention of claim 7 , it is possible to realize a wiring board provided with bonding wires (51) connected to the electrode pads (Pad) using the wire bonding connection method.

＜請求項８：第９実施形態に該当＞
請求項８の発明では、電極パッド（Pad）に対してフリップチップ接続法を用いて接続されたバンプ（５２）を備えた配線基板を実現できる。
< Claim 8 : Corresponds to the ninth embodiment>
According to the invention of claim 8 , it is possible to realize a wiring board including bumps (52) connected to the electrode pads (Pad) by using a flip chip connection method.

＜請求項９：第１２，第１３実施形態に該当＞
ＭＥＭＳ技術を利用して作製された各種センサ（例えば、圧力センサ、加速度センサ、超音波センサなど）は腐食性ガス（例えば、酸性ガスやアルカリ性ガスなど）の雰囲気中（腐食環境）で使用される場合がある。
そして、センサを構成する半導体チップの配線を外部へ引き出すための接続部材（ボンディングワイヤ、バンプ）は、半導体チップの配線層に形成された電極パッドに接続されている。
< Claim 9 : Corresponds to the twelfth and thirteenth embodiments>
Various sensors (for example, a pressure sensor, an acceleration sensor, and an ultrasonic sensor) manufactured by using MEMS technology are used in an atmosphere (corrosive environment) of a corrosive gas (for example, an acid gas or an alkaline gas). There is a case.
Then, connection members (bonding wires, bumps) for drawing the wiring of the semiconductor chip constituting the sensor to the outside are connected to electrode pads formed on the wiring layer of the semiconductor chip.

そのため、センサを腐食性ガス雰囲気中で使用する際に、センサ本体が腐食性ガスに直接晒される場合には、電極パッドも腐食性ガスに直接晒されることから、電極パッドが腐食に耐え切れずに断線不良を起こすおそれがある。
しかし、請求項９の発明では、請求項１〜８のいずれか１項に記載の配線基板によってセンサを構成することにより、腐食性ガス雰囲気中に置かれても電極パッドの腐食を防止可能であると共に、機能を阻害せずコンパクトなセンサ（１００，１１０）を実現できる。
Therefore, when the sensor is used in a corrosive gas atmosphere, if the sensor body is directly exposed to corrosive gas, the electrode pad is also directly exposed to corrosive gas. May cause disconnection failure.
However, in the invention of claim 9 , by constituting the sensor with the wiring board according to any one of claims 1 to 8 , corrosion of the electrode pad can be prevented even when placed in a corrosive gas atmosphere. In addition, a compact sensor (100, 110) can be realized without impairing the function.

＜請求項１０：第２０，第２１実施形態に該当＞
パワー素子（１８０，１９０，２００）を使用した電子回路を腐食性ガスの雰囲気中で使用する際に、パワー素子が腐食性ガスに直接晒される場合には、パワー素子の電極も腐食性ガスに直接晒される。
そのため、従来のパワー素子（１９０）では電極（１９１，１９２）が腐食に耐え切れずに断線不良を起こすおそれがある。
< Claim 10 : Corresponds to 20th and 21st embodiments>
When an electronic circuit using a power element (180, 190, 200) is used in an atmosphere of corrosive gas, if the power element is directly exposed to corrosive gas, the electrode of the power element is also exposed to corrosive gas. Directly exposed.
For this reason, in the conventional power element (190), the electrodes (191, 192) may not withstand corrosion and may cause a disconnection failure.

しかし、請求項１０の発明では、請求項１〜８のいずれか１項に記載の配線基板によってパワー素子を構成することにより、腐食性ガス雰囲気中に置かれても電極（１５，１６，Pad）の腐食を防止可能であると共に、機能を阻害せずコンパクトなパワー素子（１８０，２００）を実現できる。

However, in the invention of the tenth aspect, the power element is constituted by the wiring board according to any one of the first to eighth aspects, so that the electrode (15, 16, Pad) is placed even in a corrosive gas atmosphere. ) Can be prevented, and a compact power element (180, 200) can be realized without impairing the function.

以下、本発明を具体化した各実施形態について図面を参照しながら説明する。尚、各実施形態において、同一の構成部材および構成要素については符号を等しくすると共に、同一内容の箇所については重複説明を省略してある。   Hereinafter, embodiments embodying the present invention will be described with reference to the drawings. In each embodiment, the same constituent members and constituent elements are denoted by the same reference numerals, and redundant description of the same content is omitted.

＜第１実施形態＞
図１（Ａ）は、センサを構成する第１実施形態の半導体チップ１０における電極パッドPadの近傍を示す要部概略平面図である。
図１（Ｂ）は、第１実施形態の半導体チップ１０における電極パッドPadの近傍を示す要部概略縦断面図であり、図１（Ａ）に示すＸ−Ｘ線断面図である。
半導体チップ（配線基板）１０は、シリコン基板（半導体基板）１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPadなどから構成されている。 <First Embodiment>
FIG. 1A is a main part schematic plan view showing the vicinity of the electrode pad Pad in the semiconductor chip 10 of the first embodiment constituting the sensor.
FIG. 1B is a main part schematic longitudinal sectional view showing the vicinity of the electrode pad Pad in the semiconductor chip 10 of the first embodiment, and is a sectional view taken along line XX shown in FIG.
The semiconductor chip (wiring substrate) 10 includes a silicon substrate (semiconductor substrate) 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, and the like. ing.

シリコン基板１１の表面上には絶縁膜１２が形成され、絶縁膜１２の表面上には矩形状の第１配線層１５が形成され、絶縁膜１２および第１配線層１５の表面上には層間絶縁膜１３が形成され、層間絶縁膜１３の表面上には矩形状の第２配線層１６が形成されている。層間絶縁膜１３および第２配線層１６の表面上には、これらを覆うように保護絶縁膜１４が形成されている。   An insulating film 12 is formed on the surface of the silicon substrate 11, a rectangular first wiring layer 15 is formed on the surface of the insulating film 12, and an interlayer is formed on the surfaces of the insulating film 12 and the first wiring layer 15. An insulating film 13 is formed, and a rectangular second wiring layer 16 is formed on the surface of the interlayer insulating film 13. A protective insulating film 14 is formed on the surfaces of the interlayer insulating film 13 and the second wiring layer 16 so as to cover them.

第１配線層１５は配線層１７に接続され、配線層１７は絶縁膜１２に形成されたコンタクトホール（図示略）を介してシリコン基板１１に接続されている。尚、配線層１７は第１配線層１５と同一工程にて作成され、各配線層１５，１７は一体化されている。   The first wiring layer 15 is connected to the wiring layer 17, and the wiring layer 17 is connected to the silicon substrate 11 through a contact hole (not shown) formed in the insulating film 12. The wiring layer 17 is formed in the same process as the first wiring layer 15, and the wiring layers 15 and 17 are integrated.

各配線層１５，１６は、層間絶縁膜１３に形成された矩形状のビアホール１３ａを介して接続されている。つまり、第１配線層１５の上方の層間絶縁膜１３にはビアホール１３ａが形成され、そのビアホール１３ａの内部には第２配線層１６が充填され、ビアホール１３ａの底面から露出した第１配線層１５の上面と、ビアホール１３ａの内部に充填された第２配線層１６の下面とが接続されている。   Each wiring layer 15, 16 is connected through a rectangular via hole 13 a formed in the interlayer insulating film 13. That is, a via hole 13a is formed in the interlayer insulating film 13 above the first wiring layer 15, the second wiring layer 16 is filled in the via hole 13a, and the first wiring layer 15 exposed from the bottom surface of the via hole 13a. Are connected to the lower surface of the second wiring layer 16 filled in the via hole 13a.

第２配線層１６は、第１配線層１５の上方から層間絶縁膜１３の表面上にて横方向（シリコン基板１１の表面に対して水平方向）へ延出されている。その第２配線層１６における延出部分１６ａの表面の一部は、保護絶縁膜１４に開口形成された矩形状の開口部１４ａから露出されている。そして、保護絶縁膜１４の開口部１４ａから露出した延出部分１６ａの表面によって電極パッドPadが形成されている。   The second wiring layer 16 extends in the lateral direction (horizontal with respect to the surface of the silicon substrate 11) on the surface of the interlayer insulating film 13 from above the first wiring layer 15. A part of the surface of the extended portion 16 a in the second wiring layer 16 is exposed from a rectangular opening 14 a formed in the protective insulating film 14. An electrode pad Pad is formed by the surface of the extended portion 16 a exposed from the opening 14 a of the protective insulating film 14.

電極パッドPadには、半導体チップ１０の配線を外部へ引き出すための接続部材（図示略）が接続されている。尚、接続部材には、例えば、ワイヤボンディング（ボールボンディング）接続法で用いられるボンディングワイヤ（引出導線）や、フリップチップ（フェイスダウンボンディング）接続法で用いられるバンプなどがある。   A connection member (not shown) for drawing the wiring of the semiconductor chip 10 to the outside is connected to the electrode pad Pad. Examples of the connection member include a bonding wire (lead wire) used in a wire bonding (ball bonding) connection method and a bump used in a flip chip (face-down bonding) connection method.

ここで、各絶縁膜１２〜１４の形成材料には、密着性および絶縁性に優れるならば、どのような絶縁材料を用いてもよい。
その絶縁材料としては、例えば、ＣＶＤ（Chemical Vapor Deposition）法によって形成された酸化シリコン，窒化シリコン，ＰＳＧ（Phosphor Silicate Glass），ＢＳＧ（Boron Silicate Glass），ＢＰＳＧ（Boron Phosphor Silicate Glass）や、ＳＯＧ（Spin On Glass），ポリイミド，メチルシロキサン系ポリマーなどの塗布絶縁膜、ＴＥＯＳ（Tetra Ethyl Orso Silicate）などがある。
但し、保護絶縁膜１４については、半導体チップ１０が置かれる腐食性ガス（例えば、酸性ガスやアルカリ性ガスなど）の雰囲気に耐性がある絶縁材料を用いる必要がある。 Here, any insulating material may be used as a material for forming each of the insulating films 12 to 14 as long as it has excellent adhesion and insulating properties.
As the insulating material, for example, silicon oxide, silicon nitride, PSG (Phosphor Silicate Glass), BSG (Boron Silicate Glass), BPSG (Boron Phosphor Silicate Glass) formed by CVD (Chemical Vapor Deposition) method, SOG ( Spin On Glass), coating insulating films such as polyimide and methylsiloxane polymer, and TEOS (Tetra Ethyl Orso Silicate).
However, for the protective insulating film 14, it is necessary to use an insulating material that is resistant to an atmosphere of corrosive gas (for example, acid gas or alkaline gas) on which the semiconductor chip 10 is placed.

また、第１配線層１５および配線層１７は単層のアルミニウム系膜によって形成され、そのアルミニウム系膜の形成材料としては、例えば、アルミニウム単体、アルミニウムにシリコンを添加したシリコンアルミニウム合金などがあり、その形成方法にはＰＶＤ（Physical Vapor Deposition）法が用いられる。   Further, the first wiring layer 15 and the wiring layer 17 are formed of a single layer aluminum-based film. Examples of the material for forming the aluminum-based film include aluminum alone, a silicon aluminum alloy in which silicon is added to aluminum, and the like. As the formation method, a PVD (Physical Vapor Deposition) method is used.

また、第２配線層１６の形成材料には、半導体チップ１０が置かれる腐食性ガス雰囲気に耐性があり、各絶縁膜１３，１４との密着性に優れ、第１配線層１５と確実に接続されて良好な導通が得られるならば、どのような導電材料を用いてもよい。
その導電材料としては、例えば、金（Ａｕ）、各種高融点金属（ニッケル、モリブデン、タングステン、タンタル、ハフニウム、ジルコニウム、ニオブ、チタン、バナジウム、レニウム、クロム、プラチナ、イリジウム、オスミウム、ロジウムなど）の単体または合金（タングステンチタン、窒化チタンなど）があり、その形成方法にはＣＶＤ法やＰＶＤ法が用いられる。 Further, the forming material of the second wiring layer 16 is resistant to the corrosive gas atmosphere where the semiconductor chip 10 is placed, has excellent adhesion to the insulating films 13 and 14, and is reliably connected to the first wiring layer 15. Any conductive material may be used as long as good conduction is obtained.
As the conductive material, for example, gold (Au), various high melting point metals (nickel, molybdenum, tungsten, tantalum, hafnium, zirconium, niobium, titanium, vanadium, rhenium, chromium, platinum, iridium, osmium, rhodium, etc.) There is a single substance or an alloy (tungsten titanium, titanium nitride, etc.), and a CVD method or a PVD method is used for the formation method.

［第１実施形態の作用・効果］
第１実施形態によれば、以下の作用・効果を得ることができる。 [Operations and effects of the first embodiment]
According to the first embodiment, the following actions and effects can be obtained.

［１−１］第１実施形態の半導体チップ１０では、第１配線層１５の表面が各絶縁膜１３，１４および第２配線層１６によって覆われており、第１配線層１５の表面が露出していない。
そのため、半導体チップ１０が腐食性ガス雰囲気中に置かれても、第１配線層１５が腐食性ガスに直接晒されることがなく、腐食性ガスによって腐食され易いアルミニウム系膜によって形成されているにも関わらず第１配線層１５は腐食されない。 [1-1] In the semiconductor chip 10 of the first embodiment, the surface of the first wiring layer 15 is covered with the insulating films 13 and 14 and the second wiring layer 16, and the surface of the first wiring layer 15 is exposed. Not done.
Therefore, even if the semiconductor chip 10 is placed in a corrosive gas atmosphere, the first wiring layer 15 is not directly exposed to the corrosive gas, and is formed of an aluminum-based film that is easily corroded by the corrosive gas. Nevertheless, the first wiring layer 15 is not corroded.

そして、半導体チップ１０では、第２配線層１６が層間絶縁膜１３のビアホール１３ａにて第１配線層１５と接続され、その第２配線層１６が第１配線層１５から離れた位置まで延出されて引き出され、その第２配線層１６の延出部分１６ａの一部が保護絶縁膜１４の開口部１４ａから露出して電極パッドPadが形成されている。
そのため、半導体チップ１０が腐食性ガス雰囲気中に置かれると、電極パッドPadが腐食性ガスに直接晒される。しかし、電極パッドPadは腐食性ガスに耐性のある形成材料を用いた第２配線層１６の一部であるため、腐食性ガスにより電極パッドPadが腐食されることはなく、電極パッドPadの断線不良を防止できる。 In the semiconductor chip 10, the second wiring layer 16 is connected to the first wiring layer 15 through the via hole 13 a of the interlayer insulating film 13, and the second wiring layer 16 extends to a position away from the first wiring layer 15. As a result, a part of the extended portion 16a of the second wiring layer 16 is exposed from the opening 14a of the protective insulating film 14 to form an electrode pad Pad.
Therefore, when the semiconductor chip 10 is placed in a corrosive gas atmosphere, the electrode pad Pad is directly exposed to the corrosive gas. However, since the electrode pad Pad is a part of the second wiring layer 16 using a forming material resistant to corrosive gas, the electrode pad Pad is not corroded by the corrosive gas, and the electrode pad Pad is disconnected. Defects can be prevented.

［１−２］保護絶縁膜１４の開口部１４ａとビアホール１３ａおよび第１配線層１５とが上下方向に重なる場合には、半導体チップ１０が腐食性ガス雰囲気中に置かれたときに、腐食性ガスが保護絶縁膜１４の開口部１４ａからビアホール１３ａを通って第１配線層１５に到達し、その腐食性ガスによって第１配線層１５が腐食されるおそれがある。
尚、上下方向とは、シリコン基板１１の板厚方向を指す。 [1-2] When the opening 14a of the protective insulating film 14, the via hole 13a, and the first wiring layer 15 overlap in the vertical direction, when the semiconductor chip 10 is placed in a corrosive gas atmosphere, it is corrosive. The gas may reach the first wiring layer 15 from the opening 14a of the protective insulating film 14 through the via hole 13a, and the corrosive gas may corrode the first wiring layer 15.
The vertical direction refers to the thickness direction of the silicon substrate 11.

しかし、第１実施形態では、第２配線層１６が第１配線層１５から離れた位置まで延出されて引き出され、その第２配線層における延出部分１６ａが保護絶縁膜１４の開口部１４ａから露出されているため、保護絶縁膜１４の開口部１４ａとビアホール１３ａおよび第１配線層１５とが上下方向に重なることはない。換言すると、開口部１４ａとビアホール１３ａおよび第１配線層１５とが上下方向に重ならない位置に形成されている。
従って、第１実施形態によれば、半導体チップ１０が腐食性ガス雰囲気中に置かれたときに、腐食性ガスが保護絶縁膜１４の開口部１４ａからビアホール１３ａを通って第１配線層１５に到達することがなく、その腐食性ガスによって第１配線層１５が腐食されるおそれもない。 However, in the first embodiment, the second wiring layer 16 is extended to a position away from the first wiring layer 15, and the extended portion 16 a in the second wiring layer is an opening 14 a of the protective insulating film 14. Therefore, the opening 14a of the protective insulating film 14, the via hole 13a, and the first wiring layer 15 do not overlap in the vertical direction. In other words, the opening 14a, the via hole 13a, and the first wiring layer 15 are formed at positions that do not overlap in the vertical direction.
Therefore, according to the first embodiment, when the semiconductor chip 10 is placed in a corrosive gas atmosphere, the corrosive gas passes from the opening 14a of the protective insulating film 14 to the first wiring layer 15 through the via hole 13a. There is no possibility that the first wiring layer 15 is corroded by the corrosive gas.

［１−３］第１実施形態の半導体チップ１０を用いて圧力センサを構成した場合には、特許文献１のようにダイアフラムおよび圧力伝達液体を介して半導体チップに圧力を伝達させる必要が無く、腐食性ガス雰囲気中に置かれた半導体チップ１０に圧力を直接印加可能であるため、前記した［問題点１］を解決できる。
すなわち、第１実施形態の半導体チップ１０を用いて圧力センサを構成した場合には、圧力センサの機能であるセンサの感度の低下を防止可能になり、当該機能が阻害されない。 [1-3] When the pressure sensor is configured using the semiconductor chip 10 of the first embodiment, there is no need to transmit pressure to the semiconductor chip via the diaphragm and the pressure transmission liquid as in Patent Document 1, Since the pressure can be directly applied to the semiconductor chip 10 placed in the corrosive gas atmosphere, the above [Problem 1] can be solved.
That is, when a pressure sensor is configured using the semiconductor chip 10 of the first embodiment, it is possible to prevent a decrease in sensor sensitivity, which is a function of the pressure sensor, and the function is not hindered.

［１−４］第１実施形態の半導体チップ１０を用いて各種センサ（例えば、圧力センサ、加速度センサ、超音波センサなど）を構成した場合には、特許文献１のようにダイアフラムおよび圧力伝達液体を設ける必要や、特許文献２のように熱可塑性樹脂を設ける必要が無く、センサの外形寸法が大きくならないため、前記した［問題点２］を解決できる。   [1-4] When various sensors (for example, a pressure sensor, an acceleration sensor, an ultrasonic sensor, etc.) are configured using the semiconductor chip 10 of the first embodiment, a diaphragm and a pressure transmission liquid as in Patent Document 1. It is not necessary to provide a thermoplastic resin as in Patent Document 2, and the outer dimensions of the sensor do not increase, so that [Problem 2] described above can be solved.

［１−５］第１実施形態の半導体チップ１０を用いて前記した各種センサを構成した場合には、特許文献１のようにダイアフラムおよび圧力伝達液体を設ける必要や、特許文献２のように熱可塑性樹脂を設ける必要が無く、センサの製造コストが増大しないため、前記した［問題点３］を解決できる。   [1-5] When the above-described various sensors are configured using the semiconductor chip 10 of the first embodiment, it is necessary to provide a diaphragm and a pressure transmission liquid as in Patent Document 1, or heat as in Patent Document 2. Since there is no need to provide a plastic resin and the manufacturing cost of the sensor does not increase, the above [Problem 3] can be solved.

＜第２実施形態＞
図２（Ａ）は、センサを構成する第２実施形態の半導体チップ２０における電極パッドPadの近傍を示す要部概略縦断面図である。
半導体チップ（配線基板）２０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPad、第３配線層２１などから構成されている。 Second Embodiment
FIG. 2A is a schematic vertical sectional view showing the main part of the vicinity of the electrode pad Pad in the semiconductor chip 20 of the second embodiment that constitutes the sensor.
The semiconductor chip (wiring substrate) 20 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, a third wiring layer 21, and the like. It is configured.

第２実施形態の半導体チップ２０において、第１実施形態の半導体チップ１０と異なるのは、第２配線層１６の下側全面に第３配線層２１が形成され、各配線層２１，１６が積層されている点だけである。
ここで、第３配線層２１の形成材料には、層間絶縁膜１３との密着性に優れ、各配線層１５，１６と確実に接続されて良好な導通が得られるならば、どのような導電材料を用いてもよい。 The semiconductor chip 20 of the second embodiment is different from the semiconductor chip 10 of the first embodiment in that a third wiring layer 21 is formed on the entire lower surface of the second wiring layer 16, and the wiring layers 21 and 16 are laminated. It is only a point that has been done.
Here, the material for forming the third wiring layer 21 may be any conductive material as long as it has excellent adhesion to the interlayer insulating film 13 and is reliably connected to the wiring layers 15 and 16 to obtain good conduction. Materials may be used.

第２実施形態によれば、第２配線層１６の形成材料に層間絶縁膜１３との密着性が低い導電材料を用いた場合でも、第３配線層２１が第２配線層１６と層間絶縁膜１３を接着する接着層（密着層）として機能するため、第１実施形態の前記作用・効果と同様の作用・効果が得られる。   According to the second embodiment, even when a conductive material having low adhesion to the interlayer insulating film 13 is used as a material for forming the second wiring layer 16, the third wiring layer 21 is connected to the second wiring layer 16 and the interlayer insulating film. Since it functions as an adhesive layer (adhesion layer) for adhering 13, the same functions and effects as those of the first embodiment can be obtained.

例えば、第２配線層１６の形成材料として金を用いた場合、金は導電性に優れるものの絶縁膜との密着性に劣るという欠点がある。
そこで、第３配線層２１の形成材料として、層間絶縁膜１３との密着性に優れ、第２配線層１６の形成材料である金および第１配線層１５の形成材料であるアルミニウム系膜と確実に接続されて良好な導通が得られると共に、耐腐食性に優れた導電材料を用いればよく、その形成材料には、例えば、タンタルやタングステンチタンなどがある。
すなわち、タンタルやタングステンチタンは、金に対して電気抵抗が大きいという欠点があるが、層間絶縁膜１３との密着性に優れ、第２配線層１６の形成材料である金と確実に接続されて良好な導通が得られる上に、耐腐食性に優れているため、第３配線層２１の形成材料として好適である。 For example, when gold is used as a material for forming the second wiring layer 16, there is a drawback that gold is inferior in adhesion to the insulating film, although it is excellent in conductivity.
Therefore, as a material for forming the third wiring layer 21, it has excellent adhesion to the interlayer insulating film 13, and it is reliable to use gold as the material for forming the second wiring layer 16 and an aluminum-based film as the material for forming the first wiring layer 15. It is only necessary to use a conductive material that is connected to the substrate and has good electrical conductivity and is excellent in corrosion resistance. Examples of the forming material include tantalum and tungsten titanium.
That is, tantalum and tungsten titanium have a drawback that they have a large electrical resistance to gold, but have excellent adhesion to the interlayer insulating film 13 and are securely connected to gold, which is a material for forming the second wiring layer 16. It is suitable as a material for forming the third wiring layer 21 because good conduction is obtained and corrosion resistance is excellent.

＜第３実施形態＞
図２（Ｂ）は、センサを構成する第３実施形態の半導体チップ３０における電極パッドPadの近傍を示す要部概略縦断面図である。
半導体チップ（配線基板）３０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPad、第１接着層３１などから構成されている。 <Third Embodiment>
FIG. 2B is a schematic vertical sectional view showing the main part of the vicinity of the electrode pad Pad in the semiconductor chip 30 according to the third embodiment constituting the sensor.
The semiconductor chip (wiring substrate) 30 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, a first adhesive layer 31, and the like. It is configured.

第３実施形態の半導体チップ３０において、第１実施形態の半導体チップ１０と異なるのは、第１接着層３１が設けられている点だけである。
第１接着層３１は、ビアホール１３ａの内部を除く第２配線層１６の下側に形成されている。そして、ビアホール１３ａの内部では各配線層１５，１６が直接接触している。
ここで、第１接着層３１の形成材料には、層間絶縁膜１３および第２配線層１６との密着性に優れるならば、導電材料に限らずどのような材料を用いてもよい。 The semiconductor chip 30 of the third embodiment is different from the semiconductor chip 10 of the first embodiment only in that the first adhesive layer 31 is provided.
The first adhesive layer 31 is formed below the second wiring layer 16 excluding the inside of the via hole 13a. The wiring layers 15 and 16 are in direct contact with each other inside the via hole 13a.
Here, the material for forming the first adhesive layer 31 is not limited to the conductive material, and any material may be used as long as the adhesiveness between the interlayer insulating film 13 and the second wiring layer 16 is excellent.

第３実施形態によれば、第２配線層１６の形成材料に層間絶縁膜１３との密着性が低い導電材料を用いた場合でも、第２配線層１６と層間絶縁膜１３が第１接着層３１によって接着されるため、第１実施形態の前記作用・効果と同様の作用・効果が得られる。   According to the third embodiment, even when a conductive material having low adhesion to the interlayer insulating film 13 is used as a material for forming the second wiring layer 16, the second wiring layer 16 and the interlayer insulating film 13 are formed of the first adhesive layer. Since it adhere | attaches by 31, the effect | action and effect similar to the said effect | action and effect of 1st Embodiment are obtained.

加えて、第３実施形態では、各配線層１５，１６が直接接触することから、第２実施形態の第３配線層２１を設けた場合に比べて、各配線層１５，１６間の接触抵抗が低くなり、各配線層１５，１６の接触部分の面積を小さくすることが可能になるため、シリコン基板１１の表面上におけるビアホール１３ａの占有面積を縮小して半導体チップ３０を小型化できる。   In addition, in the third embodiment, since the wiring layers 15 and 16 are in direct contact with each other, the contact resistance between the wiring layers 15 and 16 is compared with the case where the third wiring layer 21 of the second embodiment is provided. Since the contact area between the wiring layers 15 and 16 can be reduced, the area occupied by the via hole 13a on the surface of the silicon substrate 11 can be reduced to reduce the size of the semiconductor chip 30.

＜第４実施形態＞
図３（Ａ）は、センサを構成する第４実施形態の半導体チップ４０における電極パッドPadの近傍を示す要部概略縦断面図である。
半導体チップ（配線基板）４０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPad、第３配線層２１、第４配線層４１などから構成されている。 <Fourth embodiment>
FIG. 3A is a schematic vertical sectional view showing the main part of the vicinity of the electrode pad Pad in the semiconductor chip 40 of the fourth embodiment constituting the sensor.
The semiconductor chip (wiring substrate) 40 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, a third wiring layer 21, 4 wiring layers 41 and the like.

第４実施形態の半導体チップ４０において、第２実施形態の半導体チップ２０と異なるのは、第２配線層１６の上側全面に第４配線層４１が形成され、各配線層２１，１６，４１が積層されている点だけである。
ここで、第４配線層４１の形成材料には、半導体チップ４０が置かれる腐食性ガス雰囲気に耐性があり、保護絶縁膜１４との密着性に優れ、第２配線層１６と確実に接続されて良好な導通が得られるならば、どのような導電材料を用いてもよい。 The semiconductor chip 40 of the fourth embodiment is different from the semiconductor chip 20 of the second embodiment in that a fourth wiring layer 41 is formed on the entire upper surface of the second wiring layer 16, and each wiring layer 21, 16, 41 is It is only the point where it is laminated.
Here, the forming material of the fourth wiring layer 41 is resistant to a corrosive gas atmosphere in which the semiconductor chip 40 is placed, has excellent adhesion to the protective insulating film 14, and is reliably connected to the second wiring layer 16. Any conductive material may be used as long as good conduction can be obtained.

第４実施形態によれば、第２配線層１６の形成材料に保護絶縁膜１４との密着性が低い導電材料を用いた場合でも、第４配線層４１が第２配線層１６と保護絶縁膜１４を接着する接着層として機能するため、第２実施形態の前記作用・効果と同様の作用・効果が得られる。   According to the fourth embodiment, even when a conductive material having low adhesion to the protective insulating film 14 is used as a material for forming the second wiring layer 16, the fourth wiring layer 41 is connected to the second wiring layer 16 and the protective insulating film. Since it functions as an adhesive layer for adhering 14, the same functions and effects as those of the second embodiment can be obtained.

ちなみに、第２配線層１６の形成材料として金を用いた場合には、第４配線層４１の形成材料として、保護絶縁膜１４との密着性に優れ、第２配線層１６の形成材料である金と確実に接続されて良好な導通が得られると共に、耐腐食性に優れた導電材料を用いればよく、その形成材料には、例えば、タンタルやタングステンチタンなどがある。
すなわち、タンタルやタングステンチタンは、金に対して電気抵抗が大きいという欠点があるが、保護絶縁膜１４との密着性に優れ、第２配線層１６の形成材料である金と確実に接続されて良好な導通が得られる上に、耐腐食性に優れているため、第４配線層４１の形成材料として好適である。 Incidentally, when gold is used as the forming material of the second wiring layer 16, the forming material of the fourth wiring layer 41 is excellent in adhesion with the protective insulating film 14, and is a forming material of the second wiring layer 16. A conductive material that is reliably connected to gold and has good electrical conductivity and has excellent corrosion resistance may be used, and examples of the forming material include tantalum and tungsten titanium.
That is, tantalum and tungsten titanium have a drawback that they have a large electric resistance with respect to gold, but have excellent adhesion to the protective insulating film 14 and are securely connected to gold as a material for forming the second wiring layer 16. It is suitable as a material for forming the fourth wiring layer 41 because good conduction is obtained and corrosion resistance is excellent.

＜第５実施形態＞
図３（Ｂ）は、センサを構成する第５実施形態の半導体チップ５０における電極パッドPadの近傍を示す要部概略縦断面図である。
半導体チップ（配線基板）５０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPad、接着層３１、第４配線層４１などから構成されている。 <Fifth Embodiment>
FIG. 3B is a schematic vertical sectional view showing the main part of the vicinity of the electrode pad Pad in the semiconductor chip 50 according to the fifth embodiment constituting the sensor.
The semiconductor chip (wiring substrate) 50 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, an adhesive layer 31, and a fourth wiring. It is composed of the layer 41 and the like.

第５実施形態の半導体チップ５０において、第３実施形態の半導体チップ３０と異なるのは、第２配線層１６の上側全面に第４配線層４１が形成され、各配線層１６，４１が積層されている点だけである。
従って、第５実施形態によれば、第２配線層１６の形成材料に保護絶縁膜１４との密着性が低い導電材料を用いた場合でも、第４配線層４１が第２配線層１６と保護絶縁膜１４を接着する接着層として機能するため、第３実施形態の前記作用・効果と同様の作用・効果が得られる。 The semiconductor chip 50 of the fifth embodiment is different from the semiconductor chip 30 of the third embodiment in that a fourth wiring layer 41 is formed on the entire upper surface of the second wiring layer 16 and the wiring layers 16 and 41 are laminated. It is only a point.
Therefore, according to the fifth embodiment, even when a conductive material having low adhesion to the protective insulating film 14 is used as a material for forming the second wiring layer 16, the fourth wiring layer 41 is protected from the second wiring layer 16. Since it functions as an adhesive layer that adheres the insulating film 14, the same functions and effects as those of the third embodiment can be obtained.

＜第６実施形態＞
図４（Ａ）は、センサを構成する第６実施形態の半導体チップ６０における電極パッドPadの近傍を示す要部概略縦断面図である。
半導体チップ（配線基板）６０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPad、第３配線層２１、第２接着層６１などから構成されている。 <Sixth Embodiment>
FIG. 4A is a schematic vertical sectional view showing a main part of the vicinity of the electrode pad Pad in the semiconductor chip 60 of the sixth embodiment constituting the sensor.
The semiconductor chip (wiring substrate) 60 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, a third wiring layer 21, 2 adhesive layers 61 and the like.

第６実施形態の半導体チップ６０において、第２実施形態の半導体チップ２０と異なるのは、第２接着層６１が設けられている点だけである。
第２接着層６１は、保護絶縁膜１４の開口部１４ａの内部を除く第２配線層１６の上側に形成されている。そして、保護絶縁膜１４の開口部１４ａからは第２配線層１６が直接露出している。
ここで、第２接着層６１の形成材料には、保護絶縁膜１４および第２配線層１６との密着性に優れるならば、導電材料に限らずどのような材料を用いてもよい。 The semiconductor chip 60 of the sixth embodiment is different from the semiconductor chip 20 of the second embodiment only in that a second adhesive layer 61 is provided.
The second adhesive layer 61 is formed on the second wiring layer 16 excluding the inside of the opening 14 a of the protective insulating film 14. The second wiring layer 16 is directly exposed from the opening 14 a of the protective insulating film 14.
Here, the material for forming the second adhesive layer 61 is not limited to the conductive material, and any material may be used as long as the adhesiveness between the protective insulating film 14 and the second wiring layer 16 is excellent.

第６実施形態によれば、第２配線層１６の形成材料に保護絶縁膜１４との密着性が低い導電材料を用いた場合でも、第２配線層１６と保護絶縁膜１４が第２接着層６１によって接着されるため、第２実施形態の前記作用・効果と同様の作用・効果が得られる。   According to the sixth embodiment, even when a conductive material having low adhesion to the protective insulating film 14 is used as a material for forming the second wiring layer 16, the second wiring layer 16 and the protective insulating film 14 are formed from the second adhesive layer. Since it adhere | attaches by 61, the effect | action and effect similar to the said effect | action and effect of 2nd Embodiment are acquired.

ところで、第４実施形態の半導体チップ４０では、電極パッドPadの表面が第４配線層４１によって形成されている。それに対して、第６実施形態の半導体チップ６０では、電極パッドPadの表面が第２配線層１６によって形成されている。
従って、第６実施形態では、電極パッドPadに接続される接続部材（図示略）が第２配線層１６に直接接触することから、第４実施形態の第４配線層４１を設けた場合に比べて、接続部材と第２配線層１６の接触抵抗が低くなり、接続部材と第２配線層１６の接続部分の面積を小さくすることが可能になるため、シリコン基板１１の表面上における電極パッドPadの占有面積を縮小して半導体チップ６０を小型化できる。 By the way, in the semiconductor chip 40 of the fourth embodiment, the surface of the electrode pad Pad is formed by the fourth wiring layer 41. On the other hand, in the semiconductor chip 60 of the sixth embodiment, the surface of the electrode pad Pad is formed by the second wiring layer 16.
Therefore, in the sixth embodiment, since the connection member (not shown) connected to the electrode pad Pad is in direct contact with the second wiring layer 16, compared to the case where the fourth wiring layer 41 of the fourth embodiment is provided. As a result, the contact resistance between the connection member and the second wiring layer 16 is reduced, and the area of the connection portion between the connection member and the second wiring layer 16 can be reduced. Therefore, the electrode pad Pad on the surface of the silicon substrate 11 can be reduced. The semiconductor chip 60 can be reduced in size by reducing the occupied area.

＜第７実施形態＞
図４（Ｂ）は、センサを構成する第７実施形態の半導体チップ７０における電極パッドPadの近傍を示す要部概略縦断面図である。
半導体チップ（配線基板）７０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPad、第１接着層３１、第２接着層６１などから構成されている。
すなわち、第７実施形態は、第６実施形態の第３配線層２１を第３実施形態の第１接着層３１に置き換えたものである。そのため、第７実施形態によれば、第３実施形態の作用・効果に加えて、第６実施形態の第２接着層６１に関する作用・効果が得られる。 <Seventh embodiment>
FIG. 4B is a schematic vertical sectional view showing the main part of the vicinity of the electrode pad Pad in the semiconductor chip 70 of the seventh embodiment constituting the sensor.
The semiconductor chip (wiring substrate) 70 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, a first adhesive layer 31, a first 2 adhesive layers 61 and the like.
That is, in the seventh embodiment, the third wiring layer 21 of the sixth embodiment is replaced with the first adhesive layer 31 of the third embodiment. Therefore, according to the seventh embodiment, in addition to the operations and effects of the third embodiment, the operations and effects relating to the second adhesive layer 61 of the sixth embodiment can be obtained.

＜第８実施形態＞
図５は、第５実施形態の半導体チップ５０の電極パッドPadに対して、ワイヤボンディング接続法を用いてボンディングワイヤ５１が接続された状態を示す第８実施形態の要部概略縦断面図である。
尚、電極パッドPadの表面を形成する第４配線層４１の形成材料には、ボンディングワイヤ５１と確実に接続されて良好な導通が得られる金が好適である。 <Eighth Embodiment>
FIG. 5 is a schematic vertical sectional view of a main part of the eighth embodiment showing a state in which the bonding wire 51 is connected to the electrode pad Pad of the semiconductor chip 50 of the fifth embodiment by using the wire bonding connection method. .
In addition, as a material for forming the fourth wiring layer 41 that forms the surface of the electrode pad Pad, gold that can be reliably connected to the bonding wire 51 to obtain good conduction is preferable.

＜第９実施形態＞
図６は、第５実施形態の半導体チップ５０の電極パッドPadに対して、フリップチップ接続法を用いてバンプ５２が接続された状態を示す第９実施形態の要部概略縦断面図である。
パッケージ化されていないベアチップ（ダイ）である半導体チップ５０は、裏返された状態（フェイスダウン）で実装基板５３に直接搭載されている。そして、半導体チップ５０の電極パッドPadと実装基板５３の表面上に形成された配線層５４とが、バンプ５２によって接続されている。 <Ninth Embodiment>
FIG. 6 is a schematic vertical sectional view of a main part of the ninth embodiment showing a state in which the bumps 52 are connected to the electrode pads Pad of the semiconductor chip 50 of the fifth embodiment by using a flip chip connection method.
The semiconductor chip 50 that is an unpackaged bare chip (die) is directly mounted on the mounting substrate 53 in an inverted state (face-down). The electrode pads Pad of the semiconductor chip 50 and the wiring layer 54 formed on the surface of the mounting substrate 53 are connected by bumps 52.

尚、バンプ５２は、各種導電材料（例えば、ハンダ，金，銅，ニッケルなどの金属、導電性接着剤など）を用いて適宜な方法（例えば、メッキ法、スタッド法など）により形成すればよい。
また、電極パッドPadの表面を形成する第４配線層４１の形成材料には、バンプ５２と確実に接続されて良好な導通が得られる金が好適である。 The bump 52 may be formed by an appropriate method (for example, a plating method, a stud method, or the like) using various conductive materials (for example, metals such as solder, gold, copper, nickel, or conductive adhesive). .
The material for forming the fourth wiring layer 41 that forms the surface of the electrode pad Pad is preferably gold that can be reliably connected to the bumps 52 to obtain good conduction.

＜第１０実施形態＞
図７は、センサを構成する第１０実施形態の半導体チップ８０における電極パッドPadの近傍を示す要部概略縦断面図である。
半導体チップ（配線基板）８０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPad、第３配線層２１などから構成されている。 <Tenth Embodiment>
FIG. 7 is a schematic vertical cross-sectional view of the main part showing the vicinity of the electrode pad Pad in the semiconductor chip 80 of the tenth embodiment constituting the sensor.
The semiconductor chip (wiring substrate) 80 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, a third wiring layer 21, and the like. It is configured.

第１０実施形態の半導体チップ８０において、第２実施形態の半導体チップ２０と異なるのは、ビアホール１３ａの内部に第３配線層２１が充填されて埋め込まれ、ビアホール１３ａの上方における第３配線層２１の表面が略平坦になっている点だけである。
第１０実施形態では、第３配線層２１の上側に形成する第２配線層１６によってビアホール１３ａを充填する必要が無くなるため、第２配線層１６の形成材料や形成方法として段差被覆性が低いものを使用した場合でも、第３配線層２１を介して第１配線層１５と第２配線層１６との良好な導通が得られる。
従って、第１０実施形態によれば、第２実施形態の前記作用・効果と同様の作用・効果が得られる。 The semiconductor chip 80 of the tenth embodiment is different from the semiconductor chip 20 of the second embodiment in that the third wiring layer 21 is filled and embedded in the via hole 13a, and the third wiring layer 21 above the via hole 13a. It is only the point that the surface of is substantially flat.
In the tenth embodiment, it is not necessary to fill the via hole 13a with the second wiring layer 16 formed on the upper side of the third wiring layer 21, so that the step wiring coverage is low as the forming material and the forming method of the second wiring layer 16 Even when the first wiring layer 15 is used, good conduction between the first wiring layer 15 and the second wiring layer 16 can be obtained through the third wiring layer 21.
Therefore, according to the tenth embodiment, the same operations and effects as those of the second embodiment can be obtained.

＜第１１実施形態＞
図８は、センサを構成する第１１実施形態の半導体チップ９０における電極パッドPadの近傍を示す要部概略縦断面図である。
半導体チップ（配線基板）９０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPad、第３配線層２１、第５配線層９１などから構成されている。 <Eleventh embodiment>
FIG. 8 is a schematic vertical cross-sectional view of the main part showing the vicinity of the electrode pad Pad in the semiconductor chip 90 of the eleventh embodiment constituting the sensor.
The semiconductor chip (wiring substrate) 90 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, a third wiring layer 21, 5 wiring layers 91 and the like.

第１１実施形態の半導体チップ９０において、第４実施形態の半導体チップ４０と異なるのは、第４配線層４１が第５配線層９１に置き換えられている点だけである。
第５配線層９１は、保護絶縁膜１４の開口部１４ａの内部を除く第２配線層１６の上側に形成されている。また、保護絶縁膜１４の開口部１４ａの内周壁面に位置する第５配線層９１の端面９１ａは、保護絶縁膜１４によって覆われている。
そして、保護絶縁膜１４の開口部１４ａからは第２配線層１６が直接露出している。
ここで、第５配線層９１の形成材料には、保護絶縁膜１４との密着性に優れ、第２配線層１６と確実に接続されて良好な導通が得られるならば、どのような導電材料を用いてもよい。 The semiconductor chip 90 of the eleventh embodiment is different from the semiconductor chip 40 of the fourth embodiment only in that the fourth wiring layer 41 is replaced with a fifth wiring layer 91.
The fifth wiring layer 91 is formed above the second wiring layer 16 except for the inside of the opening 14 a of the protective insulating film 14. The end surface 91 a of the fifth wiring layer 91 located on the inner peripheral wall surface of the opening 14 a of the protective insulating film 14 is covered with the protective insulating film 14.
The second wiring layer 16 is directly exposed from the opening 14 a of the protective insulating film 14.
Here, as a material for forming the fifth wiring layer 91, any conductive material can be used as long as it has excellent adhesion to the protective insulating film 14 and is reliably connected to the second wiring layer 16 to obtain good conduction. May be used.

第１１実施形態によれば、第２配線層１６の形成材料に保護絶縁膜１４との密着性が低い導電材料を用いた場合でも、第５配線層９１が第２配線層１６と保護絶縁膜１４を接着する接着層として機能するため、第４実施形態の前記作用・効果と同様の作用・効果が得られる。
そして、第１１実施形態によれば、第５配線層９１が保護絶縁膜１４に覆われて露出せず、第５配線層９１が腐食性ガスに晒されるおそれが無いため、第５配線層９１の形成材料に耐腐食性が低いものを使用可能になる。 According to the eleventh embodiment, even when a conductive material having low adhesion to the protective insulating film 14 is used as a material for forming the second wiring layer 16, the fifth wiring layer 91 is formed of the second wiring layer 16 and the protective insulating film. Since it functions as an adhesive layer for adhering 14, the same functions and effects as those of the fourth embodiment can be obtained.
According to the eleventh embodiment, the fifth wiring layer 91 is covered with the protective insulating film 14 and is not exposed, and the fifth wiring layer 91 is not exposed to corrosive gas. A material having low corrosion resistance can be used as the forming material.

ちなみに、第２配線層１６の形成材料として金を用いた場合には、第４配線層４１と同様に、第５配線層９１の形成材料として、例えば、タンタルやタングステンチタンなどを用いればよい。   Incidentally, when gold is used as the forming material of the second wiring layer 16, as in the fourth wiring layer 41, for example, tantalum, tungsten titanium, or the like may be used as the forming material of the fifth wiring layer 91.

＜第１２実施形態＞
図９は、第１０実施形態の半導体チップ８０によって構成された第１２実施形態の圧力センサ１００の概略構造を示す要部概略縦断面図である。
半導体チップ８０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPad、第３配線層２１などから構成されている。 <Twelfth embodiment>
FIG. 9 is a schematic vertical cross-sectional view of a main part showing a schematic structure of the pressure sensor 100 of the twelfth embodiment configured by the semiconductor chip 80 of the tenth embodiment.
The semiconductor chip 80 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, a third wiring layer 21, and the like. .

シリコン基板１１の裏面側（背面側）には、開口部から底部へ向かって横断面積が小さくなる縦断面台形状の凹部１１ａが形成されている。
凹部１１ａの上方に位置するシリコン基板１１の表面側には、ピエゾ抵抗素子１０１が形成されている。
尚、凹部１１ａが設けられているのは、ピエゾ抵抗素子１０１が形成されている部分におけるシリコン基板１１の板厚を薄くすることにより、ピエゾ抵抗素子１０１の結晶格子に歪みを生じやすくするためである。 On the back surface side (back surface side) of the silicon substrate 11, a concave portion 11a having a trapezoidal cross section with a cross-sectional area that decreases from the opening toward the bottom is formed.
A piezoresistive element 101 is formed on the surface side of the silicon substrate 11 located above the recess 11a.
The reason why the recess 11a is provided is that the crystal lattice of the piezoresistive element 101 is easily distorted by reducing the thickness of the silicon substrate 11 in the portion where the piezoresistive element 101 is formed. is there.

ｐ型単結晶シリコン基板１１の表面側には、複数の不純物領域（ｎ型埋込不純物領域、低濃度のｎ型不純物領域、高濃度のｎ型不純物領域、低濃度のｐ型不純物領域、高濃度のｐ型不純物領域など）１０２が形成されている。
各不純物領域１０２の表面上には絶縁膜１２が形成され、絶縁膜１２の表面上には複数の配線層１０３が形成されている。尚、各配線層１０３は、第１配線層１５と同一工程にて作成されている。 On the surface side of the p-type single crystal silicon substrate 11, a plurality of impurity regions (n-type buried impurity region, low-concentration n-type impurity region, high-concentration n-type impurity region, low-concentration p-type impurity region, high-concentration region) A p-type impurity region or the like) 102 is formed.
An insulating film 12 is formed on the surface of each impurity region 102, and a plurality of wiring layers 103 are formed on the surface of the insulating film 12. Each wiring layer 103 is created in the same process as the first wiring layer 15.

各配線層１０３は、絶縁膜１２に形成されたコンタクトホールを介してピエゾ抵抗素子１０１および各不純物領域１０２に接続されている。
そして、ピエゾ抵抗素子１０１および各不純物領域１０２が各配線層１０３によって接続されることにより、ピエゾ抵抗式の圧力センサ１００を構成する電子回路が作成されている。 Each wiring layer 103 is connected to the piezoresistive element 101 and each impurity region 102 through a contact hole formed in the insulating film 12.
The piezoresistive element 101 and each impurity region 102 are connected by each wiring layer 103, whereby an electronic circuit constituting the piezoresistive pressure sensor 100 is created.

第１配線層１５は、絶縁膜１２に形成されたコンタクトホールを介して、シリコン基板１１に形成された高濃度のｎ型不純物領域に接続されている。
また、第１配線層１５は、第３配線層２１を介して第２配線層１６に接続されている。
そして、第２配線層１６は層間絶縁膜１３の表面上にて第１配線層１５から離れた位置まで延出され、保護絶縁膜１４の開口部１４ａから露出された第２配線層１６の延出部分１６ａによって電極パッドPadが形成されている。 The first wiring layer 15 is connected to a high-concentration n-type impurity region formed in the silicon substrate 11 through a contact hole formed in the insulating film 12.
The first wiring layer 15 is connected to the second wiring layer 16 through the third wiring layer 21.
Then, the second wiring layer 16 extends to a position away from the first wiring layer 15 on the surface of the interlayer insulating film 13, and the extension of the second wiring layer 16 exposed from the opening 14 a of the protective insulating film 14. An electrode pad Pad is formed by the protruding portion 16a.

ピエゾ抵抗素子１０１が形成されている部分のシリコン基板１１に圧力が印加されると、ピエゾ抵抗素子１０１の結晶格子に歪みを生じて抵抗値が変化する。
そのピエゾ抵抗素子１０１の抵抗値の変化は、各不純物領域１０２および各配線層１０３によって構成された電子回路によって電気信号に変換され、その電気信号は電極パッドPadから圧力センサ１００の外部へ出力される。 When pressure is applied to the portion of the silicon substrate 11 where the piezoresistive element 101 is formed, the crystal lattice of the piezoresistive element 101 is distorted and the resistance value changes.
The change in the resistance value of the piezoresistive element 101 is converted into an electric signal by an electronic circuit constituted by each impurity region 102 and each wiring layer 103, and the electric signal is output from the electrode pad Pad to the outside of the pressure sensor 100. The

圧力センサ１００を腐食性ガスの雰囲気中で使用する際に、センサ本体が腐食性ガスに直接晒される場合には、電極パッドPadも腐食性ガスに直接晒される。
しかし、第１２実施形態によれば、第１０実施形態の前記作用・効果により、圧力センサ１００が腐食性ガス雰囲気中に置かれても電極パッドPadの腐食を防止可能であると共に、機能を阻害せずコンパクトな圧力センサ１００を実現できる。
尚、圧力センサ１００は、加速度センサとしても使用できる。 When the pressure sensor 100 is used in an atmosphere of corrosive gas, when the sensor body is directly exposed to the corrosive gas, the electrode pad Pad is also directly exposed to the corrosive gas.
However, according to the twelfth embodiment, the action and effect of the tenth embodiment can prevent the electrode pad Pad from being corroded even if the pressure sensor 100 is placed in a corrosive gas atmosphere, and inhibit the function. Thus, a compact pressure sensor 100 can be realized.
The pressure sensor 100 can also be used as an acceleration sensor.

＜第１３実施形態＞
図１０は、第１０実施形態の半導体チップ８０によって構成された第１３実施形態の圧力センサ１１０の概略構造を示す要部概略縦断面図である。
半導体チップ８０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPad、第３配線層２１などから構成されている。 <13th Embodiment>
FIG. 10 is a schematic vertical sectional view showing a main part of a schematic structure of the pressure sensor 110 according to the thirteenth embodiment, which is constituted by the semiconductor chip 80 according to the tenth embodiment.
The semiconductor chip 80 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, a third wiring layer 21, and the like. .

貼り合わせＳＯＩ（Silicon On Insulator）構造のセンサ本体１１１は、単結晶シリコン基板１１２、埋込酸化（ＢＯＸ：Buried OXide ）層１１３、単結晶シリコン基板１１が下方から上方に向けてこの順番で積層されて形成され、絶縁層である埋込酸化層１１３の上にＳＯＩ層であるシリコン基板１１が形成されたＳＯＩ構造を成している。
ここで、貼り合わせＳＯＩ構造のセンサ本体１１１は、例えば、貼り合わせる面（鏡面）を熱酸化して酸化膜を形成した２枚のウェハ同士を、その酸化膜を介して張り合わせた後、片側のウェハを所望の厚さになるように研削することで得られ、研磨したウェハがシリコン基板１１になり、研磨していないウェハがシリコン基板１１２になり、前記酸化膜が埋込酸化層１１３になる。 A sensor body 111 having a bonded SOI (Silicon On Insulator) structure is formed by laminating a single crystal silicon substrate 112, a buried oxide (BOX) layer 113, and a single crystal silicon substrate 11 in this order from the bottom to the top. Thus, an SOI structure is formed in which a silicon substrate 11 as an SOI layer is formed on a buried oxide layer 113 as an insulating layer.
Here, the sensor body 111 having a bonded SOI structure is formed, for example, by bonding two wafers on which the bonded surfaces (mirror surfaces) are thermally oxidized to form an oxide film through the oxide film, Obtained by grinding the wafer to a desired thickness, the polished wafer becomes the silicon substrate 11, the unpolished wafer becomes the silicon substrate 112, and the oxide film becomes the buried oxide layer 113. .

ＭＥＭＳ技術を利用して作成された可動部材１１４は、高濃度に不純物が拡散されたシリコン基板１１によって形成されている。
可動部材１１４は、櫛歯状を成す２つの部分（図示略）によって構成され、各部分は櫛歯が噛み合うように互いに離間して配置されている。
可動部材１１４の周囲にはトレンチ１１５が形成され、可動部材１１４の各部分はトレンチ１１５によって可動可能に独立されている。 The movable member 114 created using the MEMS technology is formed by the silicon substrate 11 in which impurities are diffused at a high concentration.
The movable member 114 is constituted by two parts (not shown) having a comb-teeth shape, and each part is arranged so as to be separated from each other so that the comb teeth are engaged with each other.
A trench 115 is formed around the movable member 114, and each part of the movable member 114 is movably independent by the trench 115.

各種（多結晶、非晶質、単結晶）シリコンのバルク材から成るキャップ１１６は、可動部材１１４を覆って保護するために設けられており、絶縁膜１２の表面上に接着されている。尚、可動部材１１４の動きを妨げないように、キャップ１１６の内壁面と可動部材１１４との間には空隙が設けられている。   A cap 116 made of various (polycrystalline, amorphous, single crystal) silicon bulk material is provided to cover and protect the movable member 114, and is bonded onto the surface of the insulating film 12. A gap is provided between the inner wall surface of the cap 116 and the movable member 114 so as not to hinder the movement of the movable member 114.

ｐ型単結晶シリコン基板１１の表面側には、複数の不純物領域（低濃度のｎ型不純物領域、高濃度のｎ型不純物領域、低濃度のｐ型不純物領域、高濃度のｐ型不純物領域など）１０２が形成され、各不純物領域によって静電容量式の圧力センサ１１０を構成する電子回路が作成されている。   On the surface side of the p-type single crystal silicon substrate 11, a plurality of impurity regions (low-concentration n-type impurity region, high-concentration n-type impurity region, low-concentration p-type impurity region, high-concentration p-type impurity region, etc.) ) 102 is formed, and an electronic circuit constituting the capacitive pressure sensor 110 is created by each impurity region.

第１配線層１５は、絶縁膜１２に形成されたコンタクトホールを介して、シリコン基板１１に形成された高濃度のｎ型不純物領域に接続されている。
また、第１配線層１５は、第３配線層２１を介して第２配線層１６に接続されている。
そして、第２配線層１６は層間絶縁膜１３の表面上にて第１配線層１５から離れた位置まで延出され、保護絶縁膜１４の開口部１４ａから露出された第２配線層１６の延出部分１６ａによって電極パッドPadが形成されている。 The first wiring layer 15 is connected to a high-concentration n-type impurity region formed in the silicon substrate 11 through a contact hole formed in the insulating film 12.
The first wiring layer 15 is connected to the second wiring layer 16 through the third wiring layer 21.
Then, the second wiring layer 16 extends to a position away from the first wiring layer 15 on the surface of the interlayer insulating film 13, and the extension of the second wiring layer 16 exposed from the opening 14 a of the protective insulating film 14. An electrode pad Pad is formed by the protruding portion 16a.

シリコン基板１１に圧力が印加されると、可動部材１１４の各部分が動き、各部分間の距離が変化して静電容量値も変化する。
その可動部材１１４の各部分の静電容量値の変化は、各不純物領域１０２によって構成された電子回路によって電気信号に変換され、その電気信号は電極パッドPadから圧力センサ１１０の外部へ出力される。 When pressure is applied to the silicon substrate 11, each part of the movable member 114 moves, the distance between the parts changes, and the capacitance value also changes.
The change in the capacitance value of each part of the movable member 114 is converted into an electric signal by an electronic circuit constituted by each impurity region 102, and the electric signal is output from the electrode pad Pad to the outside of the pressure sensor 110. .

圧力センサ１１０を腐食性ガスの雰囲気中で使用する際に、センサ本体が腐食性ガスに直接晒される場合には、電極パッドPadも腐食性ガスに直接晒される。
しかし、第１３実施形態によれば、第１０実施形態の前記作用・効果により、圧力センサ１１０が腐食性ガス雰囲気中に置かれても電極パッドPadの腐食を防止可能であると共に、機能を阻害せずコンパクトな圧力センサ１１０を実現できる。
尚、圧力センサ１１０は、加速度センサとしても使用できる。 When the pressure sensor 110 is used in an atmosphere of corrosive gas, when the sensor body is directly exposed to the corrosive gas, the electrode pad Pad is also directly exposed to the corrosive gas.
However, according to the thirteenth embodiment, the action and effect of the tenth embodiment can prevent the electrode pad Pad from being corroded even if the pressure sensor 110 is placed in a corrosive gas atmosphere, and the function is hindered. Therefore, the compact pressure sensor 110 can be realized.
The pressure sensor 110 can also be used as an acceleration sensor.

＜第１４実施形態＞
図１１は、第１０実施形態の半導体チップ８０によって構成された第１４実施形態の半導体装置１２０の概略構造を示す要部概略縦断面図である。
半導体チップ８０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPad、第３配線層２１などから構成されている。 <Fourteenth embodiment>
FIG. 11 is a main part schematic longitudinal sectional view showing a schematic structure of the semiconductor device 120 of the fourteenth embodiment constituted by the semiconductor chip 80 of the tenth embodiment.
The semiconductor chip 80 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, a third wiring layer 21, and the like. .

ｐ型単結晶シリコン基板１１の表面側には、複数の不純物領域（ｎ型埋込不純物領域、低濃度のｎ型不純物領域、高濃度のｎ型不純物領域、低濃度のｐ型不純物領域、高濃度のｐ型不純物領域など）１２１が形成されている。
各不純物領域１２１の表面上には絶縁膜１２２が形成され、絶縁膜１２２の表面上には複数の配線層１２３が形成されている。
絶縁膜１２２および各配線層１２３の表面上には保護絶縁膜１２４が形成され、シリコン基板１１の表面側は保護絶縁膜１２４によって完全に覆われている。 On the surface side of the p-type single crystal silicon substrate 11, a plurality of impurity regions (n-type buried impurity region, low-concentration n-type impurity region, high-concentration n-type impurity region, low-concentration p-type impurity region, high-concentration region) 121 of a p-type impurity region, etc.).
An insulating film 122 is formed on the surface of each impurity region 121, and a plurality of wiring layers 123 are formed on the surface of the insulating film 122.
A protective insulating film 124 is formed on the surfaces of the insulating film 122 and each wiring layer 123, and the surface side of the silicon substrate 11 is completely covered with the protective insulating film 124.

各配線層１２３は、絶縁膜１２２に形成されたコンタクトホールを介して各不純物領域１２１に接続されている。
そして、各不純物領域１２１が各配線層１２３によって接続されることにより、半導体装置１２０を構成する電子回路が作成されている。 Each wiring layer 123 is connected to each impurity region 121 through a contact hole formed in the insulating film 122.
Each impurity region 121 is connected by each wiring layer 123, whereby an electronic circuit constituting the semiconductor device 120 is created.

シリコン基板１１の裏面側にはトレンチ１１ｂが形成され、シリコン基板１１の表面側に形成された低濃度のｎ型不純物領域がトレンチ１１ｂの底部から露出している。
トレンチ１１ｂの内部には配線層１２５が充填されて埋め込まれ、配線層１２５は低濃度のｎ型不純物領域に接続されている。
トレンチ１１ｂの内周壁面と配線層１２５との間には絶縁膜１２６が形成されており、シリコン基板１１と配線層１２５とは絶縁膜１２６によって絶縁されている。 A trench 11b is formed on the back side of the silicon substrate 11, and a low-concentration n-type impurity region formed on the front side of the silicon substrate 11 is exposed from the bottom of the trench 11b.
The trench 11b is filled and filled with a wiring layer 125, and the wiring layer 125 is connected to the low-concentration n-type impurity region.
An insulating film 126 is formed between the inner peripheral wall surface of the trench 11 b and the wiring layer 125, and the silicon substrate 11 and the wiring layer 125 are insulated by the insulating film 126.

そして、シリコン基板１１のトレンチ１１ｂと配線層１２５および絶縁膜１２６によって貫通電極１２７が構成されている。
ここで、配線層１２５の形成材料には、例えば、銅、タングステンなどが用いられ、その形成方法にはＣＶＤ法やＰＶＤ法が用いられる。
また、絶縁膜１２６の形成材料には、例えば、ＣＶＤ法によって形成された酸化シリコン、窒化シリコンなどが用いられる。 A through electrode 127 is configured by the trench 11 b of the silicon substrate 11, the wiring layer 125, and the insulating film 126.
Here, for example, copper, tungsten, or the like is used as a forming material of the wiring layer 125, and a CVD method or a PVD method is used as a forming method thereof.
In addition, as a material for forming the insulating film 126, for example, silicon oxide or silicon nitride formed by a CVD method is used.

絶縁膜１２は、シリコン基板１１の裏面側の表面上に形成されている。
第１配線層１５は、絶縁膜１２に形成されたビアホールを介して、貫通電極１２７の配線層１２５に接続されている。
また、第１配線層１５は、第３配線層２１を介して第２配線層１６に接続されている。
そして、第２配線層１６は層間絶縁膜１３の表面上にて第１配線層１５から離れた位置まで延出され、保護絶縁膜１４の開口部１４ａから露出された第２配線層１６の延出部分１６ａによって電極パッドPadが形成されている。 The insulating film 12 is formed on the back surface of the silicon substrate 11.
The first wiring layer 15 is connected to the wiring layer 125 of the through electrode 127 through a via hole formed in the insulating film 12.
The first wiring layer 15 is connected to the second wiring layer 16 through the third wiring layer 21.
Then, the second wiring layer 16 extends to a position away from the first wiring layer 15 on the surface of the interlayer insulating film 13, and the extension of the second wiring layer 16 exposed from the opening 14 a of the protective insulating film 14. An electrode pad Pad is formed by the protruding portion 16a.

第１４実施形態の半導体装置１２０では、シリコン基板１１の表面側に形成された不純物領域１２１と、シリコン基板１１の裏面側に形成された電極パッドPadとが、各配線層１５，２１，１６および貫通電極１２７を介して接続されている。
そして、各不純物領域１２１と絶縁膜１２２および各配線層１２３が形成されたシリコン基板１１の表面側は、保護絶縁膜１２４によって完全に覆われている。 In the semiconductor device 120 according to the fourteenth embodiment, the impurity region 121 formed on the front surface side of the silicon substrate 11 and the electrode pad Pad formed on the back surface side of the silicon substrate 11 include the wiring layers 15, 21, 16 and They are connected through the through electrode 127.
The surface side of the silicon substrate 11 on which the impurity regions 121, the insulating film 122, and the wiring layers 123 are formed is completely covered with the protective insulating film 124.

従って、第１４実施形態によれば、第１０実施形態の前記作用・効果に加えて、半導体装置１２０の電極パッドPadをシリコン基板１１の裏面側のみに設け、シリコン基板１１の表面側を保護絶縁膜１２４によって完全に覆うことが可能になるため、シリコン基板１１の表面側が腐食性ガスに直接晒された場合でも、シリコン基板１１の表面側に形成された電子回路の機能が阻害されるのを確実に防止できる。   Therefore, according to the fourteenth embodiment, in addition to the operations and effects of the tenth embodiment, the electrode pad Pad of the semiconductor device 120 is provided only on the back surface side of the silicon substrate 11, and the surface side of the silicon substrate 11 is protected and insulated. Since the film 124 can be completely covered, even when the surface side of the silicon substrate 11 is directly exposed to the corrosive gas, the function of the electronic circuit formed on the surface side of the silicon substrate 11 is hindered. It can be surely prevented.

＜第１５実施形態＞
図１２は、第１０実施形態の半導体チップ８０によって構成された第１５実施形態の半導体装置１３０の概略構造を示す要部概略縦断面図である。
第１５実施形態の半導体装置１３０において、第１４実施形態の半導体装置１２０と異なるのは、シリコン基板１１の裏面側に各絶縁膜１２〜１４と各配線層１５，２１，１６および電極Padが設けられていることに加え、シリコン基板１１の表面側にも各絶縁膜１２〜１４と各配線層１５，２１，１６および電極Padが設けられている点だけである。 <Fifteenth embodiment>
FIG. 12 is a main part schematic longitudinal sectional view showing a schematic structure of the semiconductor device 130 of the fifteenth embodiment constituted by the semiconductor chip 80 of the tenth embodiment.
The semiconductor device 130 according to the fifteenth embodiment is different from the semiconductor device 120 according to the fourteenth embodiment in that the insulating films 12 to 14, the wiring layers 15, 21, 16 and the electrode Pad are provided on the back side of the silicon substrate 11. In addition, the insulating films 12 to 14, the wiring layers 15, 21, 16 and the electrode Pad are also provided on the surface side of the silicon substrate 11.

すなわち、半導体装置１３０では、シリコン基板１１の表面側に各不純物領域１２１が形成され、各不純物領域１２１の表面上には絶縁膜１２が形成され、絶縁膜１２の表面上には第１配線層１５および各配線層１２３が形成され、絶縁膜１２および各配線層１５，１２３の表面上には層間絶縁膜１３が形成され、層間絶縁膜１３の表面上には第２配線層１６が形成され、層間絶縁膜１３および第２配線層１６の表面上には保護絶縁膜１４が形成されている。
各配線層１２３は、絶縁膜１２に形成されたコンタクトホールを介して各不純物領域１２１に接続されている。 That is, in the semiconductor device 130, each impurity region 121 is formed on the surface side of the silicon substrate 11, the insulating film 12 is formed on the surface of each impurity region 121, and the first wiring layer is formed on the surface of the insulating film 12. 15 and each wiring layer 123 are formed, an interlayer insulating film 13 is formed on the surface of the insulating film 12 and each wiring layer 15, 123, and a second wiring layer 16 is formed on the surface of the interlayer insulating film 13. A protective insulating film 14 is formed on the surfaces of the interlayer insulating film 13 and the second wiring layer 16.
Each wiring layer 123 is connected to each impurity region 121 through a contact hole formed in the insulating film 12.

そして、半導体装置１３０では、シリコン基板１１の表面側に形成された不純物領域１２１と、シリコン基板１１の裏面側に形成された電極パッドPadとが、各配線層１５，２１，１６および貫通電極１２７を介して接続されている。
加えて、半導体装置１３０では、シリコン基板１１の表面側において、不純物領域１２１と電極パッドPadとが各配線層１５，２１，１６を介して接続されている。
従って、第１５実施形態によれば、第１０実施形態の前記作用・効果に加えて、シリコン基板１１の表裏両面側に電極パッドPadを設けた半導体装置１３０を実現できる。 In the semiconductor device 130, the impurity region 121 formed on the front surface side of the silicon substrate 11 and the electrode pad Pad formed on the back surface side of the silicon substrate 11 include the wiring layers 15, 21, 16 and the through electrode 127. Connected through.
In addition, in the semiconductor device 130, the impurity region 121 and the electrode pad Pad are connected via the wiring layers 15, 21, and 16 on the surface side of the silicon substrate 11.
Therefore, according to the fifteenth embodiment, in addition to the operations and effects of the tenth embodiment, the semiconductor device 130 in which the electrode pads Pad are provided on both front and back sides of the silicon substrate 11 can be realized.

＜第１６実施形態＞
図１３（Ａ）は、センサを構成する第１６実施形態の半導体チップ１４０における電極パッドPadの近傍を示す要部概略平面図である。
図１３（Ｂ）は、第１６実施形態の半導体チップ１４０における電極パッドPadの近傍を示す要部概略縦断面図であり、図１３（Ａ）に示すＸ−Ｘ線断面図である。
半導体チップ（配線基板）１４０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPadなどから構成されている。 <Sixteenth Embodiment>
FIG. 13A is a main part schematic plan view showing the vicinity of the electrode pad Pad in the semiconductor chip 140 of the sixteenth embodiment constituting the sensor.
FIG. 13B is a main part schematic longitudinal sectional view showing the vicinity of the electrode pad Pad in the semiconductor chip 140 of the sixteenth embodiment, and is a sectional view taken along line XX shown in FIG.
The semiconductor chip (wiring substrate) 140 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, and the like.

第１６実施形態の半導体チップ１４０において、第１実施形態の半導体チップ１０と異なるのは以下の点である。   The semiconductor chip 140 of the sixteenth embodiment differs from the semiconductor chip 10 of the first embodiment in the following points.

［ａ］第１配線層１５は、矩形リング状に形成されている。   [A] The first wiring layer 15 is formed in a rectangular ring shape.

［ｂ］層間絶縁膜１３において、第１配線層１５を覆う部分は全て除去されている。そして、層間絶縁膜１３に開口形成された矩形状の開口部１３ｂから第１配線層１５が完全に露出されている。   [B] In the interlayer insulating film 13, all portions covering the first wiring layer 15 are removed. The first wiring layer 15 is completely exposed from the rectangular opening 13 b formed in the interlayer insulating film 13.

［ｃ］第２配線層１６は、層間絶縁膜１３の開口部１３ｂ全体を覆うことにより、第１配線層１５の底面を除く全ての部分（上面および側壁面）を覆うように形成されている。そして、第１配線層１５の上面および側壁面と、これらを覆う第２配線層１６とが接続されている。   [C] The second wiring layer 16 is formed so as to cover all the openings (upper surface and side wall surfaces) except the bottom surface of the first wiring layer 15 by covering the entire opening 13 b of the interlayer insulating film 13. . And the upper surface and side wall surface of the 1st wiring layer 15 and the 2nd wiring layer 16 which covers these are connected.

［ｄ］第２配線層１６の中央部分は、保護絶縁膜１４に開口形成された矩形状の開口部１４ｂから露出されている。そして、保護絶縁膜１４の開口部１４ｂから露出した第２配線層１６の中央部分の表面によって電極パッドPadが形成されている。   [D] A central portion of the second wiring layer 16 is exposed from a rectangular opening 14 b formed in the protective insulating film 14. An electrode pad Pad is formed by the surface of the central portion of the second wiring layer 16 exposed from the opening 14 b of the protective insulating film 14.

［ｅ］保護絶縁膜１４の開口部１４ｂは、第１配線層１５の上面の上方部分を除く部分に形成されている。すなわち、第１配線層１５の上面の上方部分は保護絶縁膜１４によって覆われており、保護絶縁膜１４の開口部１４ｂと第１配線層１５とが上下方向に重なることはない。換言すると、保護絶縁膜１４の開口部１４ｂは、第１配線層１５の矩形リング状の内側の上方部分に開口されている。   [E] The opening 14 b of the protective insulating film 14 is formed in a portion excluding the upper portion of the upper surface of the first wiring layer 15. That is, the upper part of the upper surface of the first wiring layer 15 is covered with the protective insulating film 14, and the opening 14b of the protective insulating film 14 and the first wiring layer 15 do not overlap in the vertical direction. In other words, the opening 14 b of the protective insulating film 14 is opened in the upper portion inside the rectangular ring shape of the first wiring layer 15.

［第１６実施形態の作用・効果］
第１６実施形態によれば、第１実施形態の前記［１−３］〜［１−５］の作用・効果に加えて、以下の作用・効果を得ることができる。 [Operations and effects of the sixteenth embodiment]
According to the sixteenth embodiment, in addition to the operations and effects of [1-3] to [1-5] of the first embodiment, the following operations and effects can be obtained.

［１６−１］第１６実施形態の半導体チップ１４０では、第１配線層１５の表面が第２配線層１６によって覆われており、第１配線層１５の表面が露出していない。
そのため、半導体チップ１０が腐食性ガス雰囲気中に置かれても、第１配線層１５が腐食性ガスに直接晒されることがなく、腐食性ガスによって腐食され易いアルミニウム系膜によって形成されているにも関わらず第１配線層１５は腐食されない。 [16-1] In the semiconductor chip 140 of the sixteenth embodiment, the surface of the first wiring layer 15 is covered with the second wiring layer 16, and the surface of the first wiring layer 15 is not exposed.
Therefore, even if the semiconductor chip 10 is placed in a corrosive gas atmosphere, the first wiring layer 15 is not directly exposed to the corrosive gas, and is formed of an aluminum-based film that is easily corroded by the corrosive gas. Nevertheless, the first wiring layer 15 is not corroded.

そして、半導体チップ１４０では、第２配線層１６が第１配線層１５の上面および側壁面を覆い、第２配線層１６の中央部分が保護絶縁膜１４の開口部１４ｂから露出して電極パッドPadが形成されている。
そのため、半導体チップ１４０が腐食性ガス雰囲気中に置かれると、電極パッドPadが腐食性ガスに直接晒される。しかし、電極パッドPadは腐食性ガスに耐性のある形成材料を用いた第２配線層１６の一部であるため、腐食性ガスにより電極パッドPadが腐食されることはなく、電極パッドPadの断線不良を防止できる。 In the semiconductor chip 140, the second wiring layer 16 covers the upper surface and the side wall surface of the first wiring layer 15, and the central portion of the second wiring layer 16 is exposed from the opening 14 b of the protective insulating film 14 to be exposed to the electrode pad Pad. Is formed.
Therefore, when the semiconductor chip 140 is placed in a corrosive gas atmosphere, the electrode pad Pad is directly exposed to the corrosive gas. However, since the electrode pad Pad is a part of the second wiring layer 16 using a forming material resistant to corrosive gas, the electrode pad Pad is not corroded by the corrosive gas, and the electrode pad Pad is disconnected. Defects can be prevented.

［１６−２］保護絶縁膜１４の開口部１４ｂと第１配線層１５とが上下方向に重なる場合には、半導体チップ１４０が腐食性ガス雰囲気中に置かれたときに、腐食性ガスが保護絶縁膜１４の開口部１４ｂから第２配線層１６を通って第１配線層１５に到達し、その腐食性ガスによって第１配線層１５が腐食されるおそれがある。   [16-2] When the opening 14b of the protective insulating film 14 and the first wiring layer 15 overlap vertically, the corrosive gas is protected when the semiconductor chip 140 is placed in a corrosive gas atmosphere. The opening 14b of the insulating film 14 may reach the first wiring layer 15 through the second wiring layer 16, and the corrosive gas may corrode the first wiring layer 15.

しかし、第１６実施形態では、第１配線層１５の上面の上方部分は保護絶縁膜１４によって覆われているため、保護絶縁膜１４の開口部１４ｂと第１配線層１５とが上下方向に重なることはない。換言すると、開口部１４ｂと第１配線層１５とが上下方向に重ならない位置に形成されている。
従って、第１６実施形態によれば、半導体チップ１４０が腐食性ガス雰囲気中に置かれたときに、腐食性ガスが保護絶縁膜１４の開口部１４ｂから第２配線層１６を通って第１配線層１５に到達することがなく、その腐食性ガスによって第１配線層１５が腐食されるおそれもない。 However, in the sixteenth embodiment, since the upper part of the upper surface of the first wiring layer 15 is covered with the protective insulating film 14, the opening 14b of the protective insulating film 14 and the first wiring layer 15 overlap in the vertical direction. There is nothing. In other words, the opening 14b and the first wiring layer 15 are formed at positions that do not overlap in the vertical direction.
Therefore, according to the sixteenth embodiment, when the semiconductor chip 140 is placed in a corrosive gas atmosphere, the corrosive gas passes through the second wiring layer 16 from the opening 14b of the protective insulating film 14 and the first wiring. There is no possibility that the first wiring layer 15 is corroded by the corrosive gas without reaching the layer 15.

［１６−３］第１実施形態では、第２配線層１６が第１配線層１５から離れた位置まで延出されて引き出され、その第２配線層１６における延出部分１６ａが保護絶縁膜１４の開口部１４ａから露出され、その開口部１４ａから露出された第２配線層１６の延出部分１６ａによって電極パッドPadが形成されている。
そのため、第１実施形態では、シリコン基板１１の表面上における各配線層１５，１６の占有面積が第２配線層１６の延出部分１６ａの面積分だけ増大し、半導体チップ１０の大型化を招くおそれがある。 [16-3] In the first embodiment, the second wiring layer 16 is extended to a position away from the first wiring layer 15, and the extended portion 16a in the second wiring layer 16 is the protective insulating film 14. The electrode pad Pad is formed by the extended portion 16a of the second wiring layer 16 exposed from the opening 14a.
Therefore, in the first embodiment, the occupied area of each wiring layer 15, 16 on the surface of the silicon substrate 11 is increased by the area of the extended portion 16 a of the second wiring layer 16, leading to an increase in the size of the semiconductor chip 10. There is a fear.

それに対して、第１６実施形態では、第１配線層１５が矩形リング状に形成され、第１配線層１５を覆う第２配線層１６の中央部分（第１配線層１５の矩形リング状の内側の上方部分）が保護絶縁膜１４の開口部１４ｂから露出され、その開口部１４ｂから露出された第２配線層１６の中央部分によって電極パッドPadが形成されている。
そのため、電極パッドPadの面積が同じであれば、第１実施形態に比べて、第１６実施形態では、シリコン基板１１の表面上における各配線層１５，１６の占有面積を縮小して半導体チップ１４０を小型化できる。 In contrast, in the sixteenth embodiment, the first wiring layer 15 is formed in a rectangular ring shape, and the central portion of the second wiring layer 16 that covers the first wiring layer 15 (the inner side of the rectangular ring shape of the first wiring layer 15). Is exposed from the opening 14b of the protective insulating film 14, and an electrode pad Pad is formed by the central portion of the second wiring layer 16 exposed from the opening 14b.
Therefore, if the area of the electrode pad Pad is the same, in the sixteenth embodiment, the area occupied by the wiring layers 15 and 16 on the surface of the silicon substrate 11 is reduced as compared with the first embodiment, thereby reducing the semiconductor chip 140. Can be miniaturized.

［１６−４］第１実施形態では、ビアホール１３ａの底面から露出した第１配線層１５の上面と、ビアホール１３ａの内部に充填された第２配線層１６の下面とが接続されているだけであるため、各配線層１５，１６の接触抵抗（接続抵抗）が大きい上に、各配線層１５，１６間には電流が一方向にしか流れないことから、各配線層１５，１６間の電気抵抗が増大する。
それに対して、第１６実施形態では、第１配線層１５が矩形リング状に形成され、第１配線層１５の上面および側壁面が第２配線層１６によって覆われているため、第１実施形態に比べて、各配線層１５，１６の接触面積を増大させて接触抵抗を低減できる上に、各配線層１５，１６間で電流を四方に広げて流すことができることから、各配線層１５，１６間の電気抵抗を低減できる。 [16-4] In the first embodiment, only the upper surface of the first wiring layer 15 exposed from the bottom surface of the via hole 13a and the lower surface of the second wiring layer 16 filled in the via hole 13a are connected. Therefore, since the contact resistance (connection resistance) of each wiring layer 15 and 16 is large and current flows between the wiring layers 15 and 16 only in one direction, the electric current between the wiring layers 15 and 16 can be reduced. Resistance increases.
On the other hand, in the sixteenth embodiment, the first wiring layer 15 is formed in a rectangular ring shape, and the upper surface and the side wall surface of the first wiring layer 15 are covered with the second wiring layer 16. In comparison with this, the contact area of each wiring layer 15, 16 can be increased and the contact resistance can be reduced, and the current can be spread in all directions between each wiring layer 15, 16. The electrical resistance between 16 can be reduced.

また、第１実施形態では、第１配線層１５と電極パッドPadとが第２配線層１６の延出部分１６ａを介して接続されているため、第１配線層１５と電極パッドPadとの間の電気抵抗が、延出部分１６ａの配線抵抗の抵抗分だけ増大する。
それに対して、第１６実施形態では、第２配線層１６に延出部分１６ａが設けられていないため、第１実施形態に比べて、第１配線層１５と電極パッドPadとの間の電気抵抗を低減できる。 In the first embodiment, since the first wiring layer 15 and the electrode pad Pad are connected via the extended portion 16a of the second wiring layer 16, the first wiring layer 15 and the electrode pad Pad are not connected. Is increased by the resistance of the wiring resistance of the extended portion 16a.
On the other hand, in the sixteenth embodiment, since the extended portion 16a is not provided in the second wiring layer 16, the electrical resistance between the first wiring layer 15 and the electrode pad Pad is smaller than that in the first embodiment. Can be reduced.

＜第１７実施形態＞
図１４（Ａ）は、センサを構成する第１７実施形態の半導体チップ１５０における電極パッドPadの近傍を示す要部概略平面図である。
図１４（Ｂ）は、第１７実施形態の半導体チップ１５０における電極パッドPadの近傍を示す要部概略縦断面図であり、図１４（Ａ）に示すＸ−Ｘ線断面図である。
半導体チップ（配線基板）１５０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPadなどから構成されている。 <Seventeenth Embodiment>
FIG. 14A is a main part schematic plan view showing the vicinity of the electrode pad Pad in the semiconductor chip 150 of the seventeenth embodiment constituting the sensor.
FIG. 14B is a main part schematic longitudinal sectional view showing the vicinity of the electrode pad Pad in the semiconductor chip 150 of the seventeenth embodiment, and is a sectional view taken along line XX shown in FIG.
The semiconductor chip (wiring substrate) 150 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, and the like.

第１７実施形態の半導体チップ１５０において、第１６実施形態の半導体チップ１４０と異なるのは、第１配線層１５が略Ｕ字状に形成されている点である。
従って、第１７実施形態では、第１配線層１５が矩形リング状に形成されている第１６実施形態に比べて、各配線層１５，１６の接触面積が減少して接触抵抗が増大するものの、第１実施形態に比べれば各配線層１５，１６の接触抵抗を低減できるため、第１６実施形態の前記作用・効果と同様の作用・効果が得られる。 The semiconductor chip 150 of the seventeenth embodiment is different from the semiconductor chip 140 of the sixteenth embodiment in that the first wiring layer 15 is formed in a substantially U shape.
Therefore, in the seventeenth embodiment, although the contact area of each wiring layer 15 and 16 is reduced and the contact resistance is increased compared to the sixteenth embodiment in which the first wiring layer 15 is formed in a rectangular ring shape, Since the contact resistance of each of the wiring layers 15 and 16 can be reduced as compared with the first embodiment, the same operations and effects as those of the sixteenth embodiment can be obtained.

＜第１８実施形態＞
図１５（Ａ）は、センサを構成する第１８実施形態の半導体チップ１６０における電極パッドPadの近傍を示す要部概略平面図である。
図１５（Ｂ）は、第１８実施形態の半導体チップ１６０における電極パッドPadの近傍を示す要部概略縦断面図であり、図１５（Ａ）に示すＸ−Ｘ線断面図である。
半導体チップ（配線基板）１６０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPadなどから構成されている。 <Eighteenth embodiment>
FIG. 15A is a main part schematic plan view showing the vicinity of the electrode pad Pad in the semiconductor chip 160 of the eighteenth embodiment constituting the sensor.
FIG. 15B is a main part schematic longitudinal sectional view showing the vicinity of the electrode pad Pad in the semiconductor chip 160 of the eighteenth embodiment, and is a sectional view taken along line XX shown in FIG.
The semiconductor chip (wiring substrate) 160 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, and the like.

第１８実施形態の半導体チップ１６０において、第１６実施形態の半導体チップ１４０と異なるのは、第１配線層１５が略Ｉ字状に形成されている点である。
従って、第１８実施形態では、第１配線層１５が矩形リング状に形成されている第１６実施形態に比べて、各配線層１５，１６の接触面積が減少して接触抵抗が増大するものの、第１実施形態に比べれば各配線層１５，１６の接触抵抗を低減できるため、第１６実施形態の前記作用・効果と同様の作用・効果が得られる。 The semiconductor chip 160 of the eighteenth embodiment is different from the semiconductor chip 140 of the sixteenth embodiment in that the first wiring layer 15 is formed in a substantially I shape.
Therefore, in the eighteenth embodiment, although the contact area of each wiring layer 15 and 16 is reduced and the contact resistance is increased compared to the sixteenth embodiment in which the first wiring layer 15 is formed in a rectangular ring shape, Since the contact resistance of each of the wiring layers 15 and 16 can be reduced as compared with the first embodiment, the same operations and effects as those of the sixteenth embodiment can be obtained.

＜第１９実施形態＞
図１６（Ａ）は、センサを構成する第１９実施形態の半導体チップ１７０における電極パッドPadの近傍を示す要部概略平面図である。
図１６（Ｂ）は、第１９実施形態の半導体チップ１７０における電極パッドPadの近傍を示す要部概略縦断面図であり、図１６（Ａ）に示すＸ−Ｘ線断面図である。
半導体チップ（配線基板）１７０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPadなどから構成されている。 <Nineteenth embodiment>
FIG. 16A is a main part schematic plan view showing the vicinity of the electrode pad Pad in the semiconductor chip 170 of the nineteenth embodiment constituting the sensor.
FIG. 16B is a main part schematic longitudinal sectional view showing the vicinity of the electrode pad Pad in the semiconductor chip 170 of the nineteenth embodiment, and is a sectional view taken along line XX shown in FIG.
The semiconductor chip (wiring substrate) 170 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, and the like.

第１９実施形態の半導体チップ１７０において、第１６実施形態の半導体チップ１４０と異なるのは、第１配線層１５が略Ｌ字状に形成されている点である。
従って、第１９実施形態では、第１配線層１５が矩形リング状に形成されている第１６実施形態に比べて、各配線層１５，１６の接触面積が減少して接触抵抗が増大するものの、第１実施形態に比べれば各配線層１５，１６の接触抵抗を低減できるため、第１６実施形態の前記作用・効果と同様の作用・効果が得られる。 The semiconductor chip 170 of the nineteenth embodiment is different from the semiconductor chip 140 of the sixteenth embodiment in that the first wiring layer 15 is formed in a substantially L shape.
Therefore, in the nineteenth embodiment, compared to the sixteenth embodiment in which the first wiring layer 15 is formed in a rectangular ring shape, the contact area of each of the wiring layers 15 and 16 is reduced and the contact resistance is increased. Since the contact resistance of each of the wiring layers 15 and 16 can be reduced as compared with the first embodiment, the same operations and effects as those of the sixteenth embodiment can be obtained.

＜第２０実施形態＞
図１７は、第１６実施形態の半導体チップ１４０によって構成された第２０実施形態のパワーＭＯＳトランジスタ１８０の概略構造を示す要部概略縦断面図であり、図１８に示すＸ−Ｘ線断面図である。
図１８（Ａ）は、第２０実施形態のパワーＭＯＳトランジスタ１８０の要部概略平面図である。
図１８（Ｂ）は、第２０実施形態のパワーＭＯＳトランジスタ１８０の要部概略底面図である。
半導体チップ１４０は、シリコン基板１１、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPadなどから構成されている。 <20th Embodiment>
FIG. 17 is a main part schematic longitudinal sectional view showing a schematic structure of the power MOS transistor 180 of the twentieth embodiment constituted by the semiconductor chip 140 of the sixteenth embodiment, and is a sectional view taken along line XX shown in FIG. is there.
FIG. 18A is a schematic plan view of a main part of a power MOS transistor 180 according to the twentieth embodiment.
FIG. 18B is a schematic bottom view of the main part of the power MOS transistor 180 of the twentieth embodiment.
The semiconductor chip 140 includes a silicon substrate 11, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, and the like.

シリコン基板１１には、高濃度のｐ型不純物領域１８１、低濃度のｐ型不純物領域１８２、ｎ型不純物領域１８３が板厚方向に下方から上方に向けてこの順番で形成されている。
各不純物領域１８２，１８３には、トレンチ１８４が形成されている。
トレンチ１８４の内部には配線層１８５が充填されて埋め込まれている。
トレンチ１８４の内周壁面と配線層１８５との間には絶縁膜１８６が形成されており、各不純物領域１８２，１８３と配線層１８５とは絶縁膜１８６によって絶縁されている。 In the silicon substrate 11, a high concentration p-type impurity region 181, a low concentration p-type impurity region 182, and an n-type impurity region 183 are formed in this order from the bottom to the top in the thickness direction.
A trench 184 is formed in each of the impurity regions 182 and 183.
The trench 184 is filled and filled with a wiring layer 185.
An insulating film 186 is formed between the inner peripheral wall surface of the trench 184 and the wiring layer 185, and the impurity regions 182 and 183 and the wiring layer 185 are insulated from each other by the insulating film 186.

ｎ型不純物領域１８３の表面には、トレンチ１８４および絶縁膜１８６を囲むように高濃度のｐ型不純物領域１８７が形成されている。
絶縁膜１８６は、トレンチ１８４を囲むｐ型不純物領域１８７の表面上にも形成されている。
ｐ型不純物領域１８７とトレンチ１８４および絶縁膜１８６の表面上には絶縁膜１８８が形成されている。 A high-concentration p-type impurity region 187 is formed on the surface of the n-type impurity region 183 so as to surround the trench 184 and the insulating film 186.
The insulating film 186 is also formed on the surface of the p-type impurity region 187 surrounding the trench 184.
An insulating film 188 is formed on the surfaces of p-type impurity region 187, trench 184, and insulating film 186.

そして、ｐチャネルパワーＭＯＳトランジスタ１８０では、配線層１８５によってゲート電極が形成され、絶縁膜１８６によってゲート絶縁膜が形成され、ｐ型不純物領域１８７によってソース領域が形成され、ｐ型不純物領域１８１によってドレイン領域が形成されている。
ここで、配線層１８５の形成材料には、例えば、ＣＶＤ法によって形成された多結晶シリコンが用いられる。 In the p-channel power MOS transistor 180, the gate electrode is formed by the wiring layer 185, the gate insulating film is formed by the insulating film 186, the source region is formed by the p-type impurity region 187, and the drain is formed by the p-type impurity region 181. A region is formed.
Here, as a material for forming the wiring layer 185, for example, polycrystalline silicon formed by a CVD method is used.

第２０実施形態では、シリコン基板１１の表裏両面側にそれぞれ各配線層１５，１６、保護絶縁膜１４、電極パッドPadが形成されている。
そこで、シリコン基板１１の表面側に形成された部材には符号の末尾に「α」を付し、シリコン基板１１の裏面側に形成された部材には符号の末尾に「β」を付すことにより、表面側の部材と裏面側の部材とを区別する。 In the twentieth embodiment, the wiring layers 15 and 16, the protective insulating film 14, and the electrode pad Pad are formed on the front and back surfaces of the silicon substrate 11, respectively.
Therefore, a member formed on the front surface side of the silicon substrate 11 is marked with “α” at the end of the symbol, and a member formed on the back surface side of the silicon substrate 11 is marked with “β” at the end of the symbol. A front side member and a back side member are distinguished.

第１配線層１５αは、絶縁膜１８８に形成されたコンタクトホールを介してｐ型不純物領域１８７に接続されている。
また、第１配線層１５αを覆う第２配線層１６αの中央部分は保護絶縁膜１４αの開口部１４ｂから露出され、その開口部１４ｂから露出された第２配線層１６αの中央部分によって電極パッドPadαが形成されている。
そして、各配線層１５α，１６αによってパワーＭＯＳ（Metal Oxide Semiconductor）トランジスタ１８０のソース電極が形成されている。 The first wiring layer 15α is connected to the p-type impurity region 187 through a contact hole formed in the insulating film 188.
The central portion of the second wiring layer 16α covering the first wiring layer 15α is exposed from the opening 14b of the protective insulating film 14α, and the electrode pad Padα is exposed by the central portion of the second wiring layer 16α exposed from the opening 14b. Is formed.
A source electrode of a power MOS (Metal Oxide Semiconductor) transistor 180 is formed by the wiring layers 15α and 16α.

第１配線層１５βは、ｐ型不純物領域１８１の表面上に形成されてｐ型不純物領域１８１に接続されている。
また、第１配線層１５βを覆う第２配線層１６βの中央部分は保護絶縁膜１４βの開口部１４ｂから露出され、その開口部１４ｂから露出された第２配線層１６βの中央部分によって電極パッドPadβが形成されている。
そして、各配線層１５β，１６βによってパワーＭＯＳトランジスタ１８０のドレイン電極が形成されている。 The first wiring layer 15β is formed on the surface of the p-type impurity region 181 and connected to the p-type impurity region 181.
Further, the central portion of the second wiring layer 16β covering the first wiring layer 15β is exposed from the opening 14b of the protective insulating film 14β, and the electrode pad Padβ is exposed by the central portion of the second wiring layer 16β exposed from the opening 14b. Is formed.
The drain electrode of the power MOS transistor 180 is formed by the wiring layers 15β and 16β.

図１９（Ｂ）は、従来のパワーＭＯＳトランジスタ１９０の概略構造を示す要部概略縦断面図であり、図１９（Ａ）（Ｃ）に示すＸ−Ｘ線断面図である。
図１９（Ａ）は、従来のパワーＭＯＳトランジスタ１９０の要部概略平面図である。
図１９（Ｃ）は、従来のパワーＭＯＳトランジスタ１９０の要部概略底面図である。 FIG. 19B is a main part schematic longitudinal sectional view showing a schematic structure of a conventional power MOS transistor 190, and is a sectional view taken along the line XX shown in FIGS. 19A and 19C.
FIG. 19A is a schematic plan view of a main part of a conventional power MOS transistor 190.
FIG. 19C is a schematic bottom view of a main part of a conventional power MOS transistor 190.

従来のパワーＭＯＳトランジスタ１９０において、第２０実施形態のパワーＭＯＳトランジスタ１８０と異なるのは、各不純物領域１８３，１８７の表面上に形成された配線層１９１によってソース電極が形成され、ｐ型不純物領域１８１の表面上に形成された配線層１９２によってドレイン電極が形成されている点だけである。   The conventional power MOS transistor 190 is different from the power MOS transistor 180 of the twentieth embodiment in that the source electrode is formed by the wiring layer 191 formed on the surface of each impurity region 183 and 187, and the p-type impurity region 181. The only point is that the drain electrode is formed by the wiring layer 192 formed on the surface.

パワーＭＯＳトランジスタ１８０，１９０を使用した電子回路を腐食性ガスの雰囲気中で使用する際に、パワーＭＯＳトランジスタ１８０，１９０が腐食性ガスに直接晒される場合には、ソース電極およびドレイン電極も腐食性ガスに直接晒される。
従来のパワーＭＯＳトランジスタ１９０では、ソース電極を形成する配線層１９１とドレイン電極を形成する配線層１９２とが腐食に耐え切れずに断線不良を起こすおそれがある。 When an electronic circuit using the power MOS transistors 180 and 190 is used in an atmosphere of corrosive gas, if the power MOS transistors 180 and 190 are directly exposed to the corrosive gas, the source electrode and the drain electrode are also corrosive. Direct exposure to gas.
In the conventional power MOS transistor 190, the wiring layer 191 that forms the source electrode and the wiring layer 192 that forms the drain electrode cannot withstand corrosion and may cause a disconnection failure.

しかし、第２０実施形態によれば、第１６実施形態の前記作用・効果により、パワーＭＯＳトランジスタ１９０が腐食性ガス雰囲気中に置かれてもソース電極およびドレイン電極を形成する各電極パッドPadα，Padβの腐食を確実に防止可能であると共に、機能を阻害せずコンパクトなパワーＭＯＳトランジスタ１８０を実現できる。   However, according to the twentieth embodiment, due to the operation and effect of the sixteenth embodiment, each electrode pad Padα, Padβ that forms the source electrode and the drain electrode even when the power MOS transistor 190 is placed in a corrosive gas atmosphere. Thus, the compact power MOS transistor 180 can be realized without impairing the function.

＜第２１実施形態＞
図２０は、第１６実施形態の半導体チップ１４０によって構成された第２１実施形態のパワーＭＯＳトランジスタ２００の概略構造を示す要部概略縦断面図である。 <Twenty-first embodiment>
FIG. 20 is a schematic vertical sectional view showing a main part of a schematic structure of a power MOS transistor 200 according to the twenty-first embodiment constituted by the semiconductor chip 140 according to the sixteenth embodiment.

第２１実施形態のパワーＭＯＳトランジスタ２００において、第２０実施形態のパワーＭＯＳトランジスタ１８０と異なるのは、第２配線層１６αが２層の配線層２０１，２０２によって形成され、第１配線層１５βが３層の配線層２０３〜２０５によって形成され、第２配線層１６βが２層の配線層２０６，２０７によって形成されている点だけである。
従って、第２１実施形態においても、第２０実施形態の前記作用・効果と同様の作用・効果が得られる。 The power MOS transistor 200 of the twenty-first embodiment differs from the power MOS transistor 180 of the twentieth embodiment in that the second wiring layer 16α is formed by two wiring layers 201 and 202, and the first wiring layer 15β is three. The second wiring layer 16 </ b> β is formed only by the two wiring layers 206 and 207.
Therefore, also in the twenty-first embodiment, the same actions and effects as those in the twentieth embodiment are obtained.

第１配線層１５αを覆うように配線層２０１が形成され、配線層２０１の表面上には配線層２０２が形成されている。
例えば、第１配線層１５αはアルミニウム系膜によって形成され、配線層２０１はタンタルによって形成され、配線層２０２は金によって形成されている。
ｐ型不純物領域１８１の表面上には配線層２０３が形成され、配線層２０３の表面上には配線層２０４が形成され、配線層２０４の表面上には配線層２０５が形成されている。
例えば、配線層２０３はチタンによって形成され、配線層２０４はニッケルによって形成され、配線層２０２は金によって形成されている。
第１配線層１５βを覆うように配線層２０６が形成され、配線層２０６の表面上には配線層２０７が形成されている。
例えば、配線層２０６はタンタルによって形成され、配線層２０７は金によって形成されている。 A wiring layer 201 is formed so as to cover the first wiring layer 15α, and a wiring layer 202 is formed on the surface of the wiring layer 201.
For example, the first wiring layer 15α is formed of an aluminum film, the wiring layer 201 is formed of tantalum, and the wiring layer 202 is formed of gold.
A wiring layer 203 is formed on the surface of the p-type impurity region 181, a wiring layer 204 is formed on the surface of the wiring layer 203, and a wiring layer 205 is formed on the surface of the wiring layer 204.
For example, the wiring layer 203 is made of titanium, the wiring layer 204 is made of nickel, and the wiring layer 202 is made of gold.
A wiring layer 206 is formed so as to cover the first wiring layer 15β, and a wiring layer 207 is formed on the surface of the wiring layer 206.
For example, the wiring layer 206 is made of tantalum, and the wiring layer 207 is made of gold.

＜第２２実施形態＞
図２１（Ａ）は、センサを構成する第２２実施形態の半導体チップ２１０における電極パッドPadの近傍を示す要部概略平面図である。
図２１（Ｂ）は、第２２実施形態の半導体チップ２１０における電極パッドPadの近傍を示す要部概略縦断面図であり、図２１（Ａ）に示すＸ−Ｘ線断面図である。
半導体チップ（配線基板）２１０は、シリコン基板１１、絶縁膜１２、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPadなどから構成されている。 <Twenty-second embodiment>
FIG. 21A is a main part schematic plan view showing the vicinity of the electrode pad Pad in the semiconductor chip 210 of the twenty-second embodiment constituting the sensor.
FIG. 21B is a main part schematic longitudinal sectional view showing the vicinity of the electrode pad Pad in the semiconductor chip 210 of the twenty-second embodiment, and is a sectional view taken along line XX shown in FIG.
The semiconductor chip (wiring substrate) 210 includes a silicon substrate 11, an insulating film 12, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, and the like.

第２２実施形態の半導体チップ２１０において、第１実施形態の半導体チップ１０と異なるのは、層間絶縁膜１３が省かれ、第１配線層１５の表面上に第２配線層１６が形成され、各配線層１５，１６がビアホールを介すことなく直接接続されている点だけである。
従って、第２２実施形態においても、第１実施形態の前記作用・効果と同様の作用・効果が得られる。 The semiconductor chip 210 of the twenty-second embodiment differs from the semiconductor chip 10 of the first embodiment in that the interlayer insulating film 13 is omitted and the second wiring layer 16 is formed on the surface of the first wiring layer 15. The only point is that the wiring layers 15 and 16 are directly connected without via holes.
Therefore, also in the twenty-second embodiment, the same actions and effects as those in the first embodiment can be obtained.

＜第２３実施形態＞
図２２（Ａ）は、センサを構成する第２３実施形態の半導体チップ２２０における電極パッドPadの近傍を示す要部概略平面図である。
図２２（Ｂ）は、第２３実施形態の半導体チップ２２０における電極パッドPadの近傍を示す要部概略縦断面図であり、図２２（Ａ）に示すＸ−Ｘ線断面図である。
半導体チップ（配線基板）２２０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPad、第４配線層４１などから構成されている。 <23rd Embodiment>
FIG. 22A is a main part schematic plan view showing the vicinity of the electrode pad Pad in the semiconductor chip 220 of the twenty-third embodiment constituting the sensor.
FIG. 22B is a main part schematic longitudinal sectional view showing the vicinity of the electrode pad Pad in the semiconductor chip 220 of the twenty-third embodiment, and is a sectional view taken along line XX shown in FIG.
The semiconductor chip (wiring substrate) 220 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, a fourth wiring layer 41, and the like. It is configured.

第２３実施形態の半導体チップ２２０において、第１６実施形態の半導体チップ１４０と異なるのは、第２配線層１６の上側全面に第４配線層４１が形成され、各配線層１６，４１が積層されている点だけである。
従って、第２３実施形態によれば、第１６実施形態の前記作用・効果に加えて、第４実施形態の前記作用・効果と同様の作用・効果が得られる。 The semiconductor chip 220 of the twenty-third embodiment differs from the semiconductor chip 140 of the sixteenth embodiment in that a fourth wiring layer 41 is formed on the entire upper surface of the second wiring layer 16 and the wiring layers 16 and 41 are laminated. It is only a point.
Therefore, according to the twenty-third embodiment, in addition to the actions and effects of the sixteenth embodiment, the actions and effects similar to the actions and effects of the fourth embodiment are obtained.

＜第２４実施形態＞
図２３（Ａ）は、センサを構成する第２４実施形態の半導体チップ２３０における電極パッドPadの近傍を示す要部概略平面図である。
図２３（Ｂ）は、第２４実施形態の半導体チップ２３０における電極パッドPadの近傍を示す要部概略縦断面図であり、図２３（Ａ）に示すＸ−Ｘ線断面図である。
半導体チップ（配線基板）２３０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPad、第２接着層６１などから構成されている。 <24th Embodiment>
FIG. 23A is a main part schematic plan view showing the vicinity of the electrode pad Pad in the semiconductor chip 230 of the twenty-fourth embodiment constituting the sensor.
FIG. 23B is a schematic vertical cross-sectional view of the main part showing the vicinity of the electrode pad Pad in the semiconductor chip 230 of the twenty-fourth embodiment, and is a cross-sectional view taken along line XX shown in FIG.
The semiconductor chip (wiring substrate) 230 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, a second adhesive layer 61, and the like. It is configured.

第２４実施形態の半導体チップ２３０において、第１６実施形態の半導体チップ１４０と異なるのは、第２接着層６１が設けられている点だけである。
第２接着層６１は、保護絶縁膜１４の開口部１４ｂの内部を除く第２配線層１６の上側に形成されている。そして、保護絶縁膜１４の開口部１４ｂからは第２配線層１６が直接露出している。
従って、第２４実施形態によれば、第１６実施形態の前記作用・効果に加えて、第６実施形態の前記作用・効果と同様の作用・効果が得られる。 The semiconductor chip 230 according to the twenty-fourth embodiment is different from the semiconductor chip 140 according to the sixteenth embodiment only in that the second adhesive layer 61 is provided.
The second adhesive layer 61 is formed on the second wiring layer 16 excluding the inside of the opening 14 b of the protective insulating film 14. The second wiring layer 16 is directly exposed from the opening 14 b of the protective insulating film 14.
Therefore, according to the twenty-fourth embodiment, in addition to the actions and effects of the sixteenth embodiment, the same actions and effects as the actions and effects of the sixth embodiment are obtained.

＜第２５実施形態＞
図２４（Ａ）は、センサを構成する第２５実施形態の半導体チップ２４０における電極パッドPadの近傍を示す要部概略平面図である。
図２４（Ｂ）は、第２５実施形態の半導体チップ２４０における電極パッドPadの近傍を示す要部概略縦断面図であり、図２４（Ａ）に示すＸ−Ｘ線断面図である。
半導体チップ（配線基板）２４０は、シリコン基板１１、絶縁膜１２、層間絶縁膜１３、保護絶縁膜１４、第１配線層１５、第２配線層１６、電極パッドPad、第５配線層９１などから構成されている。 <25th Embodiment>
FIG. 24A is a main part schematic plan view showing the vicinity of the electrode pad Pad in the semiconductor chip 240 of the twenty-fifth embodiment constituting the sensor.
FIG. 24B is a main part schematic longitudinal sectional view showing the vicinity of the electrode pad Pad in the semiconductor chip 240 of the twenty-fifth embodiment, and is a sectional view taken along line XX shown in FIG.
The semiconductor chip (wiring substrate) 240 includes a silicon substrate 11, an insulating film 12, an interlayer insulating film 13, a protective insulating film 14, a first wiring layer 15, a second wiring layer 16, an electrode pad Pad, a fifth wiring layer 91, and the like. It is configured.

第２５実施形態の半導体チップ２４０において、第１６実施形態の半導体チップ１４０と異なるのは、第５配線層９１が設けられている点だけである。
第５配線層９１は、保護絶縁膜１４の開口部１４ｂの内部を除く第２配線層１６の上側に形成されている。また、保護絶縁膜１４の開口部１４ｂの内周壁面に位置する第５配線層９１の端面９１ａは、保護絶縁膜１４によって覆われている。
そして、保護絶縁膜１４の開口部１４ｂからは第２配線層１６が直接露出している。
従って、第２５実施形態によれば、第１６実施形態の前記作用・効果に加えて、第１１実施形態の前記作用・効果と同様の作用・効果が得られる。 The semiconductor chip 240 of the 25th embodiment is different from the semiconductor chip 140 of the 16th embodiment only in that a fifth wiring layer 91 is provided.
The fifth wiring layer 91 is formed above the second wiring layer 16 excluding the inside of the opening 14 b of the protective insulating film 14. The end surface 91 a of the fifth wiring layer 91 located on the inner peripheral wall surface of the opening 14 b of the protective insulating film 14 is covered with the protective insulating film 14.
The second wiring layer 16 is directly exposed from the opening 14 b of the protective insulating film 14.
Therefore, according to the 25th embodiment, in addition to the operation / effect of the 16th embodiment, the same operation / effect as the operation / effect of the 11th embodiment can be obtained.

＜別の実施形態＞
本発明は上記各実施形態に限定されるものではなく、以下のように具体化してもよく、その場合でも、上記各実施形態と同等の作用・効果を得ることができる。 <Another embodiment>
The present invention is not limited to the above embodiments, and may be embodied as follows. Even in this case, the same operations and effects as those of the above embodiments can be obtained.

［１］第４，第６，第１１実施形態において第３配線層２１を省いてもよい。   [1] The third wiring layer 21 may be omitted in the fourth, sixth, and eleventh embodiments.

［２］第５，第７，第８，第９実施形態において第１接着層３１を省いてもよい。   [2] In the fifth, seventh, eighth, and ninth embodiments, the first adhesive layer 31 may be omitted.

［３］第１６〜第１９，第２３〜第２５実施形態において層間絶縁膜１３を省いてもよい。   [3] In the sixteenth to nineteenth and twenty-third to twenty-fifth embodiments, the interlayer insulating film 13 may be omitted.

［４］第１２〜第１５実施形態は、第１０実施形態の半導体チップ８０によって構成されている。しかし、第１〜第７，第１１実施形態の半導体チップ１０，２０，３０，４０，５０，６０，７０，９０によって第１２〜第１５実施形態を構成してもよい。   [4] The twelfth to fifteenth embodiments are constituted by the semiconductor chip 80 of the tenth embodiment. However, the twelfth to fifteenth embodiments may be constituted by the semiconductor chips 10, 20, 30, 40, 50, 60, 70, 90 of the first to seventh and eleventh embodiments.

［５］第１２，第１３実施形態は圧力センサまたは加速度センサに適用しているが、本発明は、どのようなセンサに適用してもよく、例えば、超音波センサ、角速度センサ、エアフローセンサなどに適用してもよい。   [5] Although the twelfth and thirteenth embodiments are applied to a pressure sensor or an acceleration sensor, the present invention may be applied to any sensor, for example, an ultrasonic sensor, an angular velocity sensor, an air flow sensor, etc. You may apply to.

［６］第１６実施形態において、第１配線層１５は矩形リング状に形成されている。しかし、第１６実施形態の第１配線層１５は、どのような形状に形成してもよく、例えば、略Ｓ字状、略Ｅ字状などの形状に形成してもよい。   [6] In the sixteenth embodiment, the first wiring layer 15 is formed in a rectangular ring shape. However, the first wiring layer 15 of the sixteenth embodiment may be formed in any shape, for example, may be formed in a shape such as a substantially S shape or a substantially E shape.

［７］第２０，第２１実施形態は、第１６実施形態の半導体チップ１４０によって構成されている。しかし、第１〜第９，第１７〜第１９，第２３〜第２５実施形態の半導体チップ１０，２０，３０，４０，５０，６０，７０，８０，９０，１５０，１６０，１７０，２２０，２３０，２４０によって第２０，第２１実施形態を構成してもよい。   [7] The twentieth and twenty-first embodiments are constituted by the semiconductor chip 140 of the sixteenth embodiment. However, the semiconductor chips 10, 20, 30, 40, 50, 60, 70, 80, 90, 150, 160, 170, 220, of the first to ninth, 17th to 19th, and 23rd to 25th embodiments are provided. The twentieth and twenty-first embodiments may be configured by 230 and 240.

［８］第２０，第２１実施形態はパワーＭＯＳトランジスタの電極構造に適用したものであるが、本発明は、どのようなパワー素子の電極構造に適用してもよく、例えば、バイポーラトランジスタ、ＩＧＢＴ（Insulated Gate Bipolar Transistor）、ＳＩＴ（Static Induction Transistor）、サイリスタなどの電極構造に適用してもよい。   [8] Although the twentieth and twenty-first embodiments are applied to the electrode structure of a power MOS transistor, the present invention may be applied to any electrode structure of a power element, for example, a bipolar transistor, an IGBT. You may apply to electrode structures, such as (Insulated Gate Bipolar Transistor), SIT (Static Induction Transistor), and a thyristor.

［９］上記各実施形態はシリコン基板１１上に作成したデバイスに適用したものであるが、その他の半導体基板（例えば、ガリウム・ヒ素基板、インジウム・ガリウム・ヒ素基板など）やＳＯＩ（Silicon On Insulator）基板の上に作成したデバイスに適用してもよい。
また、本発明は、半導体基板に限らず、どのような材質の配線基板に適用してもよく、例えば、プリント配線基板やハイブリッドＩＣ（Integrated Circuit）の実装基板などに適用してもよい。そして、基板の表面が絶縁性の場合には、絶縁膜１２を省いてもよい。 [9] Each of the above embodiments is applied to a device formed on the silicon substrate 11, but other semiconductor substrates (for example, gallium arsenide substrate, indium gallium arsenide substrate, etc.) or SOI (Silicon On Insulator) ) It may be applied to a device created on a substrate.
The present invention is not limited to a semiconductor substrate, and may be applied to a wiring substrate of any material, for example, a printed wiring substrate or a mounting substrate of a hybrid IC (Integrated Circuit). If the surface of the substrate is insulating, the insulating film 12 may be omitted.

図１（Ａ）は、本発明を具体化した第１実施形態の半導体チップ１０における電極パッドPadの近傍を示す要部概略平面図。図１（Ｂ）は、第１実施形態の半導体チップ１０における電極パッドPadの近傍を示す要部概略縦断面図であり、図１（Ａ）に示すＸ−Ｘ線断面図。FIG. 1A is a main part schematic plan view showing the vicinity of an electrode pad Pad in a semiconductor chip 10 according to a first embodiment embodying the present invention. FIG. 1B is a main part schematic longitudinal sectional view showing the vicinity of the electrode pad Pad in the semiconductor chip 10 of the first embodiment, and is a sectional view taken along line XX shown in FIG. 図２（Ａ）は、本発明を具体化した第２実施形態の半導体チップ２０における電極パッドPadの近傍を示す要部概略縦断面図。図２（Ｂ）は、本発明を具体化した第３実施形態の半導体チップ３０における電極パッドPadの近傍を示す要部概略縦断面図。FIG. 2A is a schematic vertical sectional view showing the main part of the vicinity of the electrode pad Pad in the semiconductor chip 20 of the second embodiment embodying the present invention. FIG. 2B is a schematic vertical sectional view showing the main part of the vicinity of the electrode pad Pad in the semiconductor chip 30 of the third embodiment embodying the present invention. 図３（Ａ）は、本発明を具体化した第４実施形態の半導体チップ４０における電極パッドPadの近傍を示す要部概略縦断面図。図３（Ｂ）は、本発明を具体化した第５実施形態の半導体チップ５０における電極パッドPadの近傍を示す要部概略縦断面図。FIG. 3A is a schematic vertical sectional view showing the main part of the vicinity of the electrode pad Pad in the semiconductor chip 40 of the fourth embodiment embodying the present invention. FIG. 3B is a schematic vertical sectional view showing the main part of the vicinity of the electrode pad Pad in the semiconductor chip 50 according to the fifth embodiment embodying the present invention. 図４（Ａ）は、本発明を具体化した第６実施形態の半導体チップ６０における電極パッドPadの近傍を示す要部概略縦断面図。図４（Ｂ）は、本発明を具体化した第７実施形態の半導体チップ７０における電極パッドPadの近傍を示す要部概略縦断面図。FIG. 4A is a schematic vertical sectional view showing the main part of the vicinity of the electrode pad Pad in the semiconductor chip 60 of the sixth embodiment embodying the present invention. FIG. 4B is a schematic vertical sectional view showing the main part of the vicinity of the electrode pad Pad in the semiconductor chip 70 of the seventh embodiment embodying the present invention. 本発明を具体化した第８実施形態の要部概略縦断面図。The principal part schematic longitudinal cross-sectional view of 8th Embodiment which actualized this invention. 本発明を具体化した第９実施形態の要部概略縦断面図。The principal part schematic longitudinal cross-sectional view of 9th Embodiment which actualized this invention. 本発明を具体化した第１０実施形態の半導体チップ８０における電極パッドPadの近傍を示す要部概略縦断面図。The principal part schematic longitudinal cross-sectional view which shows the vicinity of the electrode pad Pad in the semiconductor chip 80 of 10th Embodiment which actualized this invention. 本発明を具体化した第１１実施形態の半導体チップ９０における電極パッドPadの近傍を示す要部概略縦断面図。The principal part schematic longitudinal cross-sectional view which shows the vicinity of the electrode pad Pad in the semiconductor chip 90 of 11th Embodiment which actualized this invention. 本発明を具体化した第１２実施形態の圧力センサ１００の概略構造を示す要部概略縦断面図。The principal part schematic longitudinal cross-sectional view which shows schematic structure of the pressure sensor 100 of 12th Embodiment which actualized this invention. 本発明を具体化した第１３実施形態の圧力センサ１１０の概略構造を示す要部概略縦断面図。The principal part schematic longitudinal cross-sectional view which shows schematic structure of the pressure sensor 110 of 13th Embodiment which actualized this invention. 本発明を具体化した第１４実施形態の半導体装置１２０の概略構造を示す要部概略縦断面図。The principal part schematic longitudinal cross-sectional view which shows schematic structure of the semiconductor device 120 of 14th Embodiment which actualized this invention. 本発明を具体化した第１５実施形態の半導体装置１３０の概略構造を示す要部概略縦断面図。The principal part schematic longitudinal cross-sectional view which shows schematic structure of the semiconductor device 130 of 15th Embodiment which actualized this invention. 図１３（Ａ）は、本発明を具体化した第１６実施形態の半導体チップ１４０における電極パッドPadの近傍を示す要部概略平面図。図１３（Ｂ）は、第１６実施形態の半導体チップ１４０における電極パッドPadの近傍を示す要部概略縦断面図であり、図１３（Ａ）に示すＸ−Ｘ線断面図。FIG. 13A is a schematic plan view of the main part showing the vicinity of an electrode pad Pad in a semiconductor chip 140 according to a sixteenth embodiment that embodies the present invention. FIG. 13B is a schematic vertical cross-sectional view of the main part showing the vicinity of the electrode pad Pad in the semiconductor chip 140 of the sixteenth embodiment, and is a cross-sectional view taken along line XX shown in FIG. 図１４（Ａ）は、本発明を具体化した第１７実施形態の半導体チップ１５０における電極パッドPadの近傍を示す要部概略平面図。図１４（Ｂ）は、第１７実施形態の半導体チップ１５０における電極パッドPadの近傍を示す要部概略縦断面図であり、図１４（Ａ）に示すＸ−Ｘ線断面図。FIG. 14A is a main part schematic plan view showing the vicinity of the electrode pad Pad in the semiconductor chip 150 of the seventeenth embodiment embodying the present invention. FIG. 14B is a main part schematic longitudinal sectional view showing the vicinity of the electrode pad Pad in the semiconductor chip 150 of the seventeenth embodiment, and is a sectional view taken along line XX shown in FIG. 図１５（Ａ）は、本発明を具体化した第１８実施形態の半導体チップ１６０における電極パッドPadの近傍を示す要部概略平面図。図１５（Ｂ）は、第１８実施形態の半導体チップ１６０における電極パッドPadの近傍を示す要部概略縦断面図であり、図１５（Ａ）に示すＸ−Ｘ線断面図。FIG. 15A is a main part schematic plan view showing the vicinity of an electrode pad Pad in a semiconductor chip 160 according to an eighteenth embodiment embodying the present invention. FIG. 15B is a schematic vertical cross-sectional view of the main part showing the vicinity of the electrode pad Pad in the semiconductor chip 160 of the eighteenth embodiment, and is a cross-sectional view along the line XX shown in FIG. 図１６（Ａ）は、本発明を具体化した第１９実施形態の半導体チップ１７０における電極パッドPadの近傍を示す要部概略平面図。図１６（Ｂ）は、第１９実施形態の半導体チップ１７０における電極パッドPadの近傍を示す要部概略縦断面図であり、図１６（Ａ）に示すＸ−Ｘ線断面図。FIG. 16A is a main part schematic plan view showing the vicinity of the electrode pad Pad in the semiconductor chip 170 of the nineteenth embodiment embodying the present invention. FIG. 16B is a schematic vertical cross-sectional view of the main part showing the vicinity of the electrode pad Pad in the semiconductor chip 170 of the nineteenth embodiment, and is a cross-sectional view taken along line XX shown in FIG. 本発明を具体化した第１６実施形態の半導体チップ１４０によって構成された第２０実施形態のパワーＭＯＳトランジスタ１８０の概略構造を示す要部概略縦断面図であり、図１８に示すＸ−Ｘ線断面図。FIG. 19 is a schematic vertical sectional view of a main part showing a schematic structure of a power MOS transistor 180 according to a twentieth embodiment constituted by a semiconductor chip 140 according to a sixteenth embodiment embodying the present invention; Figure. 図１８（Ａ）は、第２０実施形態のパワーＭＯＳトランジスタ１８０の要部概略平面図。図１８（Ｂ）は、第２０実施形態のパワーＭＯＳトランジスタ１８０の要部概略底面図。FIG. 18A is a schematic plan view of a main part of a power MOS transistor 180 according to the twentieth embodiment. FIG. 18B is a schematic bottom view of the main part of the power MOS transistor 180 of the twentieth embodiment. 図１９（Ｂ）は、従来のパワーＭＯＳトランジスタ１９０の概略構造を示す要部概略縦断面図であり、図１９（Ａ）（Ｃ）に示すＸ−Ｘ線断面図。図１９（Ａ）は、従来のパワーＭＯＳトランジスタ１９０の要部概略平面図。図１９（Ｃ）は、従来のパワーＭＯＳトランジスタ１９０の要部概略底面図。FIG. 19B is a main part schematic longitudinal sectional view showing a schematic structure of a conventional power MOS transistor 190, and is a sectional view taken along line XX shown in FIGS. 19A and 19C. FIG. 19A is a schematic plan view of a main part of a conventional power MOS transistor 190. FIG. 19C is a schematic bottom view of a main part of a conventional power MOS transistor 190. 本発明を具体化した第２１実施形態のパワーＭＯＳトランジスタ２００の概略構造を示す要部概略縦断面図。The principal part schematic longitudinal cross-sectional view which shows schematic structure of the power MOS transistor 200 of 21st Embodiment which actualized this invention. 図２１（Ａ）は、本発明を具体化した第２２実施形態の半導体チップ２１０における電極パッドPadの近傍を示す要部概略平面図。図２１（Ｂ）は、第２２実施形態の半導体チップ２１０における電極パッドPadの近傍を示す要部概略縦断面図であり、図２１（Ａ）に示すＸ−Ｘ線断面図。FIG. 21A is a main part schematic plan view showing the vicinity of an electrode pad Pad in a semiconductor chip 210 of a twenty-second embodiment embodying the present invention. FIG. 21B is a schematic vertical cross-sectional view of the main part showing the vicinity of the electrode pad Pad in the semiconductor chip 210 of the 22nd embodiment, and is a cross-sectional view taken along line XX shown in FIG. 図２２（Ａ）は、本発明を具体化した第２３実施形態の半導体チップ２２０における電極パッドPadの近傍を示す要部概略平面図。図２２（Ｂ）は、第２３実施形態の半導体チップ２２０における電極パッドPadの近傍を示す要部概略縦断面図であり、図２２（Ａ）に示すＸ−Ｘ線断面図。FIG. 22A is a main part schematic plan view showing the vicinity of the electrode pad Pad in the semiconductor chip 220 of the twenty-third embodiment embodying the present invention. FIG. 22B is a main part schematic longitudinal sectional view showing the vicinity of the electrode pad Pad in the semiconductor chip 220 of the twenty-third embodiment, and is a sectional view taken along line XX shown in FIG. 図２３（Ａ）は、本発明を具体化した第２４実施形態の半導体チップ２３０における電極パッドPadの近傍を示す要部概略平面図。図２３（Ｂ）は、第２４実施形態の半導体チップ２３０における電極パッドPadの近傍を示す要部概略縦断面図であり、図２３（Ａ）に示すＸ−Ｘ線断面図。FIG. 23A is a main part schematic plan view showing the vicinity of the electrode pad Pad in the semiconductor chip 230 of the twenty-fourth embodiment embodying the present invention. FIG. 23B is a schematic vertical sectional view showing the main part in the vicinity of the electrode pad Pad in the semiconductor chip 230 of the twenty-fourth embodiment, and is a sectional view taken along line XX shown in FIG. 図２４（Ａ）は、本発明を具体化した第２５実施形態の半導体チップ２４０における電極パッドPadの近傍を示す要部概略平面図。図２４（Ｂ）は、第２５実施形態の半導体チップ２４０における電極パッドPadの近傍を示す要部概略縦断面図であり、図２４（Ａ）に示すＸ−Ｘ線断面図。FIG. 24A is a main part schematic plan view showing the vicinity of the electrode pad Pad in the semiconductor chip 240 of the twenty-fifth embodiment embodying the present invention. FIG. 24B is a main part schematic longitudinal sectional view showing the vicinity of the electrode pad Pad in the semiconductor chip 240 of the twenty-fifth embodiment, and is a sectional view taken along line XX shown in FIG. 図２５（Ａ）は、従来の半導体チップ３００における電極パッドPadの近傍を示す要部概略縦断面図。図２５（Ｂ）は、腐食性ガスに耐性がある保護配線層３１１，３１２で電極パッドPadを覆うようにした従来の半導体チップ３１０の要部概略縦断面図。FIG. 25A is a schematic vertical sectional view showing a main part of the vicinity of an electrode pad Pad in a conventional semiconductor chip 300. FIG. 25B is a schematic longitudinal sectional view of a main part of a conventional semiconductor chip 310 in which the electrode pad Pad is covered with protective wiring layers 311 and 312 resistant to corrosive gas.

符号の説明Explanation of symbols

１０，２０，３０，４０，５０，６０，７０，８０，９０，１４０，１５０，１６０，１７０，２１０，２２０，２３０，２４０…半導体チップ（配線基板）
１１…シリコン基板
１２…絶縁膜
１３…層間絶縁膜
１３ａ…ビアホール
１３ｂ…層間絶縁膜１３の開口部
１４…保護絶縁膜
１４ａ，１４ｂ…保護絶縁膜１４の開口部
１５（１５α，１５β）…第１配線層
１６（１６α，１６β）…第２配線層
１６ａ…第２配線層１６における延出部分
２１…第３配線層
３１…第１接着層
４１…第４配線層
５１…ボンディングワイヤ
５２…バンプ
５３…実装基板
５４…配線層
６１…第２接着層
９１…第５配線層
９１ａ…第５配線層９１の端面
１００，１１０…圧力センサ
１２０．１３０…半導体装置
１２７…貫通電極
１８０，２００…パワーＭＯＳトランジスタ
Pad（Padα，Padβ）…電極パッド 10, 20, 30, 40, 50, 60, 70, 80, 90, 140, 150, 160, 170, 210, 220, 230, 240 ... semiconductor chip (wiring substrate)
DESCRIPTION OF SYMBOLS 11 ... Silicon substrate 12 ... Insulating film 13 ... Interlayer insulating film 13a ... Via hole 13b ... Opening part of interlayer insulating film 13 ... Protective insulating film 14a, 14b ... Opening part 15 (15 (alpha), 15 (beta)) ... 1st of protective insulating film 14 Wiring layer 16 (16α, 16β) ... second wiring layer 16a ... extended portion in the second wiring layer 16 ... third wiring layer 31 ... first adhesive layer 41 ... fourth wiring layer 51 ... bonding wire 52 ... bump 53 ... Mounting board 54 ... Wiring layer 61 ... Second adhesive layer 91 ... Fifth wiring layer 91a ... End face of fifth wiring layer 91 100, 110 ... Pressure sensor 120.130 ... Semiconductor device 127 ... Through electrode 180, 200 ... Power MOS Transistor
Pad (Padα, Padβ): Electrode pad

Claims (10)

基板の表面上に形成された第１配線層と、
その第１配線層の上方に形成された第２配線層と、
その第２配線層を覆うように形成された保護絶縁膜と、
その保護絶縁膜に形成された開口部と、
その開口部に配置された電極パッドと、
前記基板および前記第１配線層の表面上に形成された層間絶縁膜と、
その層間絶縁膜に形成されたビアホールと、
前記第２配線層の下側全面および前記層間絶縁膜の表面上に形成された第３配線層と
を備えた配線基板であって、
前記保護絶縁膜の開口部と前記第１配線層とが基板の板厚方向にて重ならない位置に形成され、
前記第２配線層は前記第１配線層から離れた位置まで延出されて引き出され、その第２配線層における延出部分は前記保護絶縁膜の開口部から露出され、その開口部から露出された第２配線層の延出部分によって前記電極パッドが形成され、
前記保護絶縁膜は、前記層間絶縁膜および前記第２配線層の表面上に形成され、
前記ビアホールの内部に前記第３配線層が充填されて埋め込まれ、
前記第１配線層と前記第３配線層とは前記ビアホールを介して接続され、
前記第１配線層と前記第２配線層とは、前記ビアホールの内部に充填された前記第３配線層を介して接続され、
前記第３配線層を介して前記層間絶縁膜と前記第２配線層が接着され、
前記第２配線層は金から成り、
前記第３配線層はタンタルから成ることを特徴とする配線基板。 A first wiring layer formed on the surface of the substrate;
A second wiring layer formed above the first wiring layer;
A protective insulating film formed to cover the second wiring layer;
An opening formed in the protective insulating film;
An electrode pad disposed in the opening;
An interlayer insulating film formed on the surface of the substrate and the first wiring layer;
Via holes formed in the interlayer insulating film;
A wiring board comprising a third wiring layer formed on the entire lower surface of the second wiring layer and on the surface of the interlayer insulating film ;
The opening of the protective insulating film and the first wiring layer are formed at positions that do not overlap in the thickness direction of the substrate,
The second wiring layer is extended to a position away from the first wiring layer, and an extended portion of the second wiring layer is exposed from the opening of the protective insulating film and exposed from the opening. The electrode pad is formed by the extended portion of the second wiring layer,
The protective insulating film is formed on the surface of the interlayer insulating film and the second wiring layer,
The third wiring layer is filled and embedded in the via hole,
The first wiring layer and the third wiring layer are connected via the via hole,
The first wiring layer and the second wiring layer are connected via the third wiring layer filled in the via hole,
The interlayer insulating film and the second wiring layer are bonded via the third wiring layer,
The second wiring layer is made of gold;
The wiring board, wherein the third wiring layer is made of tantalum. 請求項１に記載の配線基板において、
前記第２配線層の上側全面に形成された第４配線層を備え、
その第４配線層を介して前記第２配線層と前記保護絶縁膜が接着されることを特徴とする配線基板。 The wiring board according to claim 1,
A fourth wiring layer formed on the entire upper surface of the second wiring layer;
The wiring board, wherein the second wiring layer and the protective insulating film are bonded via the fourth wiring layer. 請求項１に記載の配線基板において、
前記保護絶縁膜の開口部の内部を除く前記第２配線層の上側に形成された第５配線層を備え、
その第５配線層を介して前記第２配線層と前記保護絶縁膜が接着され、
前記保護絶縁膜の開口部の内周壁面に位置する前記第５配線層の端面は前記保護絶縁膜によって覆われ、
前記保護絶縁膜の開口部から前記第２配線層が直接露出していることを特徴とする配線基板。 The wiring board according to claim 1,
A fifth wiring layer formed on the upper side of the second wiring layer excluding the inside of the opening of the protective insulating film;
The second wiring layer and the protective insulating film are bonded via the fifth wiring layer,
The end face of the fifth wiring layer located on the inner peripheral wall surface of the opening of the protective insulating film is covered with the protective insulating film,
The wiring board, wherein the second wiring layer is directly exposed from the opening of the protective insulating film. 請求項２に記載の配線基板において、
前記第４配線層はタンタルまたはタングステンチタンから成ることを特徴とする配線基板。 The wiring board according to claim 2,
The wiring board, wherein the fourth wiring layer is made of tantalum or tungsten titanium. 請求項３に記載の配線基板において、
前記第５配線層はタンタルまたはタングステンチタンから成ることを特徴とする配線基板。 The wiring board according to claim 3,
The wiring board according to claim 5, wherein the fifth wiring layer is made of tantalum or tungsten titanium. 請求項１に記載の配線基板において、
前記保護絶縁膜の開口部の内部を除く前記第２配線層の上側に形成された第２接着層を備え、
その第２接着層を介して前記第２配線層と前記保護絶縁膜が接着され、
前記保護絶縁膜の開口部から前記第２配線層が直接露出していることを特徴とする配線基板。 The wiring board according to claim 1,
A second adhesive layer formed on the upper side of the second wiring layer excluding the inside of the opening of the protective insulating film;
The second wiring layer and the protective insulating film are bonded via the second adhesive layer,
The wiring board, wherein the second wiring layer is directly exposed from the opening of the protective insulating film. 請求項１〜６のいずれか１項に記載の配線基板において、
前記電極パッドに対してワイヤボンディング接続法を用いて接続されたボンディングワイヤを備えたことを特徴とする配線基板。 In the wiring board according to any one of claims 1 to 6,
A wiring board comprising a bonding wire connected to the electrode pad using a wire bonding connection method. 請求項１〜６のいずれか１項に記載の配線基板において、
前記電極パッドに対してフリップチップ接続法を用いて接続されたバンプを備えたことを特徴とする配線基板。 In the wiring board according to any one of claims 1 to 6,
A wiring board comprising a bump connected to the electrode pad using a flip chip connection method. 請求項１〜８のいずれか１項に記載の配線基板において、
前記配線基板はセンサを構成することを特徴とする配線基板。 In the wiring board according to any one of claims 1 to 8,
The wiring board according to claim 1, wherein the wiring board constitutes a sensor. 請求項１〜８のいずれか１項に記載の配線基板において、
前記配線基板はパワー素子を構成することを特徴とする配線基板。 In the wiring board according to any one of claims 1 to 8,
The wiring board constitutes a power element.
JP2007157502A 2006-06-30 2007-06-14 Wiring board Expired - Fee Related JP5119756B2 (en)

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