JP5030796B2 - データ転送中にキャッシュへのアクセスを制限するシステムおよびその方法 - Google Patents
データ転送中にキャッシュへのアクセスを制限するシステムおよびその方法 Download PDFInfo
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- 238000012546 transfer Methods 0.000 title claims description 66
- 238000000034 method Methods 0.000 title claims description 22
- 239000000872 buffer Substances 0.000 claims description 9
- 238000005192 partition Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- 238000012545 processing Methods 0.000 description 7
- 230000004044 response Effects 0.000 description 3
- 238000013500 data storage Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
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- Theoretical Computer Science (AREA)
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Description
このような転送を行うために、グラフィックスドライバはタイトループあるいはx86 REP命令を用いてムーブファンクションを繰り返し行い、キャッシュを介してメモリからフレームバッファに、あるいはフレームバッファからメモリにデータブロックを連続的に転送する。
キャッシュ内にすでにあるデータを上書きすることで、キャッシュの効率性が低下するおそれがあることは明らかであろう。その理由は、キャッシュから画像データを転送した後、上書きされたデータをキャッシュに再書き込みする必要があり、多くの場合、この再書込みがプロセッサの大幅な遅延や失速を招くからである。
本明細書では、「キャッシュ列」という用語は、共通のインデックスに関連付けられる一連のキャッシュラインのことを指す。キャッシュメモリ120は、例えば、16のウェイ、128の列のキャッシュを備え、各キャッシュラインが32バイトのデータを格納できるものであってもよい。システム100はさらに、システムメモリ130などの、キャッシュ120を利用した1以上のモジュール、システムバス150などを介してキャッシュ120および/あるいはプロセッサ110に接続されたディスプレイフレームバッファ140を含み得る。
Claims (8)
- 転送されるデータのデータ形式を決定するステップ(402)、
前記データを転送するためのデータ転送コマンドを決定するステップ(404)、
前記データが第1の形式の場合に、前記データ転送コマンドとともに使用する第1のプレフィックスを選択するステップ(406)、および、
前記データが第2の形式の場合に、前記データ転送コマンドとともに使用する第2のプレフィックスを選択するステップ、を含み、
前記第1のプレフィックスが、前記データ転送コマンドによってキャッシュメモリの複数のウェイのうちの第1サブセットだけにアクセスを限定することにより前記キャッシュメモリへのアクセスを制御するものであり、
前記第2のプレフィックスが、前記データ転送コマンドによって前記キャッシュメモリの複数のウェイのうちの第2サブセットだけにアクセスを限定することにより前記キャッシュメモリへのアクセスを制御するものである、方法。 - 第1の形式の前記データは画像データであり、前記第2の形式のデータは前記第1の前記形式のデータとは異なる、請求項1に記載の方法。
- 第1の形式の前記データは画像フレームバッファ(140)に転送される、請求項1に記載の方法。
- 第1の形式の前記データは再利用されることのない一時データである、請求項1に記載の方法。
- 前記第1のプレフィックスは前記複数のウェイのうちの前記第1のサブセットだけにアクセスを限定する第1のキャッシュマスク(212、222)の選択を容易にし、前記第2のプレフィックスは前記複数のウェイのうちの前記第2のサブセットだけにアクセスを限定する第2のキャッシュマスク(212、222)の選択を容易にするために選択される、請求項1に記載の方法。
- プロセッサ(110)、
フレームバッファ(140)、
キャッシュメモリ(122)、および、
前記プロセッサ(110)によって実行される転送を実行するための命令の形式に基づいて、前記キャッシュメモリ(122)の複数のウェイのうちの1つのサブセットだけにアクセスを限定することにより、前記フレームバッファ(140)へデータを転送する間に前記キャッシュメモリ(122)へのアクセスを制御するキャッシュコントローラ(124)、を含むシステム。 - 前記キャッシュコントローラ(124)はさらに、前記プロセッサ(110)によって実行される前記命令の形式に基づいて複数のキャッシュマスク(212、222)から第1のキャッシュマスク(212)を選択し、前記選択された第1のキャッシュマスク(212)は、前記データ転送中に前記キャッシュメモリ(122)の複数のウェイのうちの前記1つのサブセットだけにアクセスを制御する、請求項6に記載のシステム。
- 前記キャッシュコントローラ(124)は、前記複数のウェイの、最も長時間未使用の情報に基づいて、前記ウェイの前記1つのサブセットからなる前記1以上のウェイを決定する、請求項6に記載のシステム。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US11/052,432 US7930484B2 (en) | 2005-02-07 | 2005-02-07 | System for restricted cache access during data transfers and method thereof |
US11/052,432 | 2005-02-07 | ||
PCT/US2006/001597 WO2006086121A2 (en) | 2005-02-07 | 2006-01-17 | System for restricted cache access during data transfers and method thereof |
Publications (2)
Publication Number | Publication Date |
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JP2008530656A JP2008530656A (ja) | 2008-08-07 |
JP5030796B2 true JP5030796B2 (ja) | 2012-09-19 |
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Application Number | Title | Priority Date | Filing Date |
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JP2007554109A Active JP5030796B2 (ja) | 2005-02-07 | 2006-01-17 | データ転送中にキャッシュへのアクセスを制限するシステムおよびその方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US7930484B2 (ja) |
JP (1) | JP5030796B2 (ja) |
KR (1) | KR101245823B1 (ja) |
CN (1) | CN100578472C (ja) |
DE (1) | DE112006000339B4 (ja) |
GB (1) | GB2437888B (ja) |
TW (1) | TWI403900B (ja) |
WO (1) | WO2006086121A2 (ja) |
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2005
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- 2006-01-17 GB GB0716023A patent/GB2437888B/en active Active
- 2006-01-17 JP JP2007554109A patent/JP5030796B2/ja active Active
- 2006-01-17 CN CN200680004210A patent/CN100578472C/zh active Active
- 2006-01-17 DE DE112006000339.9T patent/DE112006000339B4/de active Active
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Also Published As
Publication number | Publication date |
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US20060179228A1 (en) | 2006-08-10 |
WO2006086121A2 (en) | 2006-08-17 |
DE112006000339B4 (de) | 2020-10-29 |
GB2437888B (en) | 2010-11-17 |
US7930484B2 (en) | 2011-04-19 |
KR101245823B1 (ko) | 2013-03-21 |
GB0716023D0 (en) | 2007-09-26 |
KR20070110021A (ko) | 2007-11-15 |
JP2008530656A (ja) | 2008-08-07 |
TWI403900B (zh) | 2013-08-01 |
DE112006000339T5 (de) | 2007-12-20 |
GB2437888A (en) | 2007-11-07 |
CN100578472C (zh) | 2010-01-06 |
CN101116061A (zh) | 2008-01-30 |
TW200636467A (en) | 2006-10-16 |
WO2006086121A3 (en) | 2007-03-29 |
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