JP5022392B2 - ペーストバンプを用いた印刷回路基板の製造方法 - Google Patents
ペーストバンプを用いた印刷回路基板の製造方法 Download PDFInfo
- Publication number
- JP5022392B2 JP5022392B2 JP2009025296A JP2009025296A JP5022392B2 JP 5022392 B2 JP5022392 B2 JP 5022392B2 JP 2009025296 A JP2009025296 A JP 2009025296A JP 2009025296 A JP2009025296 A JP 2009025296A JP 5022392 B2 JP5022392 B2 JP 5022392B2
- Authority
- JP
- Japan
- Prior art keywords
- paste
- substrate
- bump
- paste bump
- core substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/50—Fixed connections
- H01R12/51—Fixed connections for rigid printed circuits or like structures
- H01R12/52—Fixed connections for rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
- H01R12/523—Fixed connections for rigid printed circuits or like structures connecting to other rigid printed circuits or like structures by an interconnection through aligned holes in the boards or multilayer board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0353—Making conductive layer thin, e.g. by etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Description
ペーストバンプの付着されていない第1コア基板を製造するために、図4の(a1)のようにベイキング(Baking)などの前処理工程を経た銅箔積層板(CCL)などのコア部材10を準備し、図4の(a2)のようにBVH16が形成される部分の銅箔層12を予め除去して開放部(window)14を形成する。
図4の(b1)のように用意された銅箔板(Copper Foil)30に図4の(b2)のようにシルバーペーストなどの導電性ペーストを印刷してペーストバンプ(Paste Bump)32を形成する。一括積層の効率性を高めるために、図4の(b3)のようにプリプレグ(Prepreg)などの絶縁材34を銅箔板30に積層する。この過程で銅箔板30に形成されているペーストバンプ32がプリプレグを貫いて絶縁材34の表面へ突出される。
図4の(c1)のように第1コア基板の製造工程より製造されたコア基板を準備して、図4の(c2)のように導電性ペーストを用いてBVH16のメッキ層18が形成された部分のディンプル42の反対側面にペーストバンプ44を印刷する。第2コア基板に結合されるペーストバンプ44は他のコア基板のディンプルまたは回路パターンと電気的に繋がるし、第2コア基板に形成されるメッキ層のディンプル42は他のコア基板またはペーストバンプ基板に結合されるペーストバンプにより充填される。
図4の(d)のように、第1コア基板、第2コア基板、ペーストバンプ基板を、ペーストバンプの位置がメッキ層18のディンプル19の位置と整列されるようにレイアップ(Lay−up)し、図4の(e)のように一括積層された各基板を圧着して多層印刷回路基板を製造する。以後、印刷回路基板に外層回路36を形成する工程には従来の一般ビルドアップ(Build−up)工法を適用することができる。
Claims (8)
- (a)コア基板を貫通してビアホールを形成する段階と、
(b)前記コア基板の表面に内層回路を形成する段階と、
(c)前記コア基板の表面にペーストバンプ(paste bump)基板を積層する段階と、
(d)前記ペーストバンプ基板の表面に外層回路を形成する段階と
を含み、
前記ペーストバンプ基板は、
(e)前記ビアホールの形成された位置に対応して銅箔板にペーストバンプを印刷する段階と、
(f)前記ペーストバンプを硬化させる段階と、
(g)前記ペーストバンプが絶縁材を貫くように前記銅箔板に前記絶縁材を積層する段階と
を経て形成され、
前記ペーストバンプの量は、前記ビアホールに充填されるように前記ビアホールの大きさに応じて決まり、
前記段階(a)は、前記ビアホールの内周面にメッキ層を形成する段階をさらに含み、
前記メッキ層の厚みは、前記ビアホールの入口から深さ方向に行くほど増加することを特徴とするペーストバンプを用いた印刷回路基板の製造方法。 - 前記段階(c)は、前記コア基板の両面にて前記ペーストバンプ基板を積層する段階を含む請求項1に記載のペーストバンプを用いた印刷回路基板の製造方法。
- 前記段階(c)と前記段階(d)の間に前記コア基板の両面にて前記ペーストバンプ基板を圧着する段階をさらに含む請求項2に記載のペーストバンプを用いた印刷回路基板の製造方法。
- 前記ペーストバンプは、前記内層回路と前記外層回路を電気的に連結するBVH(blind via hole)の形状に形成される請求項1から3のいずれか1項に記載のペーストバンプを用いた印刷回路基板の製造方法。
- 前記ペーストバンプは、前記コア基板より強度が低く、前記絶縁材より強度が高い請求項1から4のいずれか1項に記載のペーストバンプを用いた印刷回路基板の製造方法。
- 前記ペーストバンプは、シルバーペースト(silver paste)を含む請求項1から5のいずれか1項に記載のペーストバンプを用いた印刷回路基板の製造方法。
- 前記コア基板は、銅箔積層板(CCL)である請求項1から6のいずれか1項に記載のペーストバンプを用いた印刷回路基板の製造方法。
- 前記段階(a)は、機械的ドリリングにより前記ビアホールを穿孔することを含む請求項1から7のいずれか1項に記載のペーストバンプを用いた印刷回路基板の製造方法。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050109850A KR100704922B1 (ko) | 2005-11-16 | 2005-11-16 | 페이스트 범프를 이용한 인쇄회로기판 및 그 제조방법 |
KR10-2005-0109855 | 2005-11-16 | ||
KR1020050109855A KR100704927B1 (ko) | 2005-11-16 | 2005-11-16 | 페이스트 범프를 이용한 인쇄회로기판 및 그 제조방법 |
KR10-2005-0109850 | 2005-11-16 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006303279A Division JP4287458B2 (ja) | 2005-11-16 | 2006-11-08 | ペーストバンプを用いた印刷回路基板およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009124173A JP2009124173A (ja) | 2009-06-04 |
JP5022392B2 true JP5022392B2 (ja) | 2012-09-12 |
Family
ID=38039573
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006303279A Expired - Fee Related JP4287458B2 (ja) | 2005-11-16 | 2006-11-08 | ペーストバンプを用いた印刷回路基板およびその製造方法 |
JP2009025296A Expired - Fee Related JP5022392B2 (ja) | 2005-11-16 | 2009-02-05 | ペーストバンプを用いた印刷回路基板の製造方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006303279A Expired - Fee Related JP4287458B2 (ja) | 2005-11-16 | 2006-11-08 | ペーストバンプを用いた印刷回路基板およびその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (3) | US20070107934A1 (ja) |
JP (2) | JP4287458B2 (ja) |
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KR100757907B1 (ko) * | 2006-07-06 | 2007-09-11 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
US8440916B2 (en) * | 2007-06-28 | 2013-05-14 | Intel Corporation | Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method |
US9098646B2 (en) * | 2007-08-10 | 2015-08-04 | Kyocera Corporation | Printed circuit board design system and method |
JP4317245B2 (ja) * | 2007-09-27 | 2009-08-19 | 新光電気工業株式会社 | 電子装置及びその製造方法 |
KR100897316B1 (ko) * | 2007-10-26 | 2009-05-14 | 삼성전기주식회사 | 인쇄회로기판의 제조방법 |
JP5166890B2 (ja) * | 2008-01-24 | 2013-03-21 | 日本特殊陶業株式会社 | 配線基板およびその製造方法 |
KR101009176B1 (ko) * | 2008-03-18 | 2011-01-18 | 삼성전기주식회사 | 다층 인쇄회로기판의 제조방법 |
JP5448354B2 (ja) * | 2008-03-25 | 2014-03-19 | 日本特殊陶業株式会社 | 配線基板およびその製造方法 |
TWI392405B (zh) * | 2009-10-26 | 2013-04-01 | Unimicron Technology Corp | 線路結構 |
US8519270B2 (en) | 2010-05-19 | 2013-08-27 | Unimicron Technology Corp. | Circuit board and manufacturing method thereof |
US8552564B2 (en) * | 2010-12-09 | 2013-10-08 | Intel Corporation | Hybrid-core through holes and vias |
KR101167466B1 (ko) * | 2010-12-30 | 2012-07-26 | 삼성전기주식회사 | 다층 인쇄회로기판 그 제조방법 |
US9818682B2 (en) * | 2014-12-03 | 2017-11-14 | International Business Machines Corporation | Laminate substrates having radial cut metallic planes |
CN107205313B (zh) * | 2016-03-16 | 2020-01-03 | 景硕科技股份有限公司 | 易于测试的多层电路板 |
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CN109673112B (zh) * | 2017-10-13 | 2021-08-20 | 鹏鼎控股(深圳)股份有限公司 | 柔性电路板以及柔性电路板的制作方法 |
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-
2006
- 2006-11-08 JP JP2006303279A patent/JP4287458B2/ja not_active Expired - Fee Related
- 2006-11-13 US US11/598,140 patent/US20070107934A1/en not_active Abandoned
-
2008
- 2008-07-21 US US12/219,381 patent/US7973248B2/en not_active Expired - Fee Related
- 2008-10-29 US US12/289,534 patent/US20090064497A1/en not_active Abandoned
-
2009
- 2009-02-05 JP JP2009025296A patent/JP5022392B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20080283288A1 (en) | 2008-11-20 |
JP2009124173A (ja) | 2009-06-04 |
US20090064497A1 (en) | 2009-03-12 |
JP2007142399A (ja) | 2007-06-07 |
US7973248B2 (en) | 2011-07-05 |
US20070107934A1 (en) | 2007-05-17 |
JP4287458B2 (ja) | 2009-07-01 |
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