JP4995834B2 - 半導体記憶装置 - Google Patents
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Description
図1(a),(b)及び図1(c)に、本発明の半導体記憶装置で用いる情報記憶部列の構造を示す。相変化薄膜(カルコゲナイド)101は上部プラグ電極102と下部電極104に挟まれている。相変化薄膜101の組成はGe2Sb2Te5であり、上部プラグ電極102および下部電極104の組成は、タングステンである。プラグ寸法131は直径160nmである。プラグ寸法は使用する半導体プロセスの世代により異なる。上部プラグ電極102の組成としてはタングステンが用いられることが多いが、導電性のものであればよい。
このI1は低抵抗状態にある非選択セルの相変化記憶部に流れるもっとも大きな電流値である。同様に高抵抗状態(reest状態)にある非選択セルの相変化記憶部に流れるもっとも大きな電流値I2は、次の式で表される。
I1,I2ともにset動作に用いる電流Isetに比べ、無視出来ないほど大きくなった場合、繰り返しの電流パルス印加により高抵抗状態の低抵抗化(reset状態からset状態への遷移)あるいは低抵抗状態(set状態)への書き込みによる低抵抗状態の固定化など非選択セルの情報擾乱が起こる。したがって、少なくとも
I1< Iset (3)
I2< Iset (4)
理想的には
I1< 10×Iset (5)
I2< 10×Iset (6)
が成り立つ様、選択トランジスタを設計しなければならない。
(7)式の右辺第2項は非選択セルによる寄生抵抗である。この寄生抵抗部分がreset抵抗よりも十分小さい、即ち
(N−1)×(RON 2/ROFF)×((ROFF+Rset)/(RON+Rset))<< Rreset (8)
理想的には
(N−1)×(RON 2/ROFF)×((ROFF+Rset)/(RON+Rset))< 10×Rreset (9)
を満たす様、トランジスタを設計しなければ相変化記憶部に蓄えた情報を読み出す事が困難になる。つまり、(9)式を満たす様相変化記憶部の特性に合わせてセル選択トランジスタの性能を決めなければならない。但し、(1)〜(9)式を用いた以上の議論は簡単の為、全ての電流値を正として扱っている。ここではメモリセル列を構成する相変化記憶部及びMOSトランジスタの抵抗値の大きさのみを取り扱っているため、電流値の正負は議論の結果には何ら影響を及ぼさない。
前記実施の形態1と同じ等価回路の構成でありながら、隣接するセルを選択し書き込み動作を行う際に電流を流す方向を切り替える必要の無い構造を持つメモリセルについて、以下説明を行う。
図17に本実施の形態3による相変化メモリの構成の略図を示す。即ち、当該相変化メモリは、メモリアレイとマルチプレクサMUX、ロウ(行)デコーダXDEC、カラム(列)デコーダYDEC、読み出し回路RC、書換え回路PRGM0で構成される。メモリアレイは、複数のメモリセルで構成されたメモリブロックMB00〜MBmnで構成される。同図では、一例として8つのメモリセルMC0〜MC7で構成されたメモリブロックが示されている。メモリセルの各々は、ビット線BL0〜BLnとソース線(ここでは、SL12やSL34)との間で、ロウ・デコーダXDEC0の出力信号であるワード線WL00〜WL07、…、WLm0〜WLm7とビット線BL0〜BLnとの各交点にそれぞれ配置される。ソース線の各々は、隣接するメモリブロックで共有される。メモリブロックは、ビット線とメモリセルとの間に挿入された階層スイッチHS0をさらに有する。階層スイッチHS0は、ロウ・デコーダXDEC0の出力信号であるメモリブロック選択信号MBS0〜MBSmの中の一つがゲート電極に接続されたNMOSトランジスタQMHで構成されており、ドレイン−ソース間の電流経路がビット線とメモリセルとの間の電流経路に含まれるように接続される。
本実施の形態4では、メモリアレイの別の構成と動作を説明する。図22に本実施の形態4による相変化メモリの構成の略図を示す図である。図17との相違は、大きく二つある。第一に、ロウ・デコーダXDEC1と書換え回路PRGM1との結線を排し、ロウ・アドレス判別回路XFLGを取り除いた。第二に、ロウ・デコーダXDEC1に、メモリブロックとビット線との接続を制御するための信号をメモリブロックあたり2つ発生する機能を追加した。
本実施の形態5では、メモリアレイのさらに別の構成と動作を説明する。図27は、本実施の形態5によるメモリアレイおよびメモリブロックの構成を示している。本実施の形態5によるメモリアレイは、選択ワード線に接続されるメモリブロックにおける非選択メモリセルへの微小電流の流入を阻止するために、二つのビット線を用いてメモリセルの電流経路を形成することに特徴がある。また、回路構成の特徴は、次の四点である。
Claims (9)
- 第1の抵抗値を有する結晶状態と前記第1の抵抗値よりも高い抵抗値を有するアモルファス状態との2つの安定相を持つ相変化薄膜と、
前記相変化薄膜の一方に設けられた第1及び第2の電極と、
前記相変化薄膜の他方に設けられた第3の電極と、
ドレイン端子が前記第1の電極に接続され、ソース端子が前記第3の電極に接続され、ゲート端子が第1のワード線に接続された第1のトランジスタと、
ドレイン端子が前記第2の電極に接続され、ソース端子が前記第3の電極に接続され、ゲート端子が第2のワード線に接続された第2のトランジスタとを有し、
第1のメモリセルは、前記第1の電極と前記第3の電極に挟まれた前記相変化薄膜中の第1の相変化領域と、前記第1のトランジスタとを具備して成り、
第2のメモリセルは、前記第2の電極と前記第3の電極に挟まれた前記相変化薄膜中の第2の相変化領域と、前記第2のトランジスタとを具備して成り、
前記第1のメモリセルへの書き込み時に、前記第1のトランジスタをオフにし、前記第1の電極から前記第3の電極へ電流を流し、
前記第2のメモリセルへの書き込み時に、前記第2のトランジスタをオフにし、前記第2の電極から前記第3の電極へ電流を流すことを特徴とする半導体記憶装置。 - 請求項1記載の半導体記憶装置において、
さらに、前記第1のメモリセルと前記第2のメモリセルと直列に接続された電流制御用トランジスタを有することを特徴とする半導体記憶装置。 - 請求項2記載の半導体記憶装置において、
前記第1及び前記第2のメモリセルが繰り返し複数個直列に接続され、
直列に接続されたメモリセル列内のメモリセル数をNとしたとき、
前記メモリセルを構成するトランジスタのオン抵抗RON、オフ抵抗ROFF、前記メモリセルを構成する相変化薄膜がアモルファス状態である時の抵抗値Rreset、及び結晶状態である時の抵抗値Rsetが、
(N−1)×(RON 2/ROFF)×((ROFF+Rset)/(RON+Rset))<10×Rreset
の条件を満たすことを特徴とする半導体記憶装置。 - 請求項1記載の半導体記憶装置において、
読み出し時に、選択されたメモリセルのトランジスタのみをオフとし、非選択のメモリセルのトランジスタをオンとすることにより選択された相変化領域の両電極に読み出し電圧を印加し、選択された前記メモリセルのデータを読み出し、
書き込み時に、選択されたメモリセルのトランジスタのみをオフとし、非選択のメモリセルのトランジスタをオンとすることにより選択された相変化領域の両電極に書き込み電圧を印加し、選択された前記相変化領域に対して書き込み電流を印加することを特徴とする半導体記憶装置。 - 請求項1記載の半導体記憶装置において、
選択されたメモリセルへの書き込みを行うに当たり、直列に接続されたメモリセルのうち、隣接するメモリセルの書き込みには互いに反対の極性を持つ電流を印加することにより書き込むことを特徴とする半導体記憶装置。 - 請求項1記載の半導体記憶装置において、
同じ数のメモリセルを直列に接続したメモリセル列を複数本並べて配置し、それらメモリセル列と直行する方向にワード線を配置した配列を形成して、前記メモリセル列と前記ワード線との組み合わせにより、書き込み、読み出しのメモリセルを選択することを特徴とする半導体記憶装置。 - 請求項6記載の半導体記憶装置において、
前記第1のメモリセルに情報を書き込む際、選択した前記第1のメモリセルを構成する前記第1のトランジスタのゲート電極に接続された第1のワード線を介して前記第1のトランジスタをオフ状態にし、選択した第1のメモリセルを含む直列に接続されたメモリセル列に第1の電流パルスを印加して書き込みを行い、
第1のワード線に隣接する第2のワード線を介し前記第1のメモリセルに隣接する前記第2のメモリセルに書き込みを行う際、前記第1及び第2のメモリセルを含むセル列に対して前記第1の電流パルスと逆方向の第2の電流パルスを印加することを特徴とする半導体記憶装置。 - 請求項1記載の半導体記憶装置において、
選択されたメモリセルの読み出しを行うに当たり、直列に接続されたメモリセルの両端に印加する読み出し電圧は、全ての読み出しメモリセルに対し常に同じ条件でのパルスを用いることを特徴とする半導体記憶装置。 - 複数のワード線と、
前記複数のワード線に交差する複数のビット線と、
前記複数のワード線と前記複数のビット線との交点に配置され、記憶情報に応じて抵抗が変化する記憶素子とトランジスタとをそれぞれ含む複数のメモリセルと、
前記複数のワード線の配置の合間に一定の間隔で配置された複数の階層スイッチと、
共通データ線と、
前記複数のビット線と前記共通データ線との間に配置され、前記複数のビット線の1つを選択して前記共通データ線に接続するためのスイッチ回路と、
前記共通データ線に接続された書換え回路とを備え、
前記複数の階層スイッチのうちの第1の階層スイッチは、前記複数のビット線のうちの第1のビット線および接地電圧端子と前記複数のメモリセルのうちの第1のメモリセルとの間に挿入され、前記複数の階層スイッチのうちの第2の階層スイッチは、前記第1のビット線および接地電圧端子と前記複数のメモリセルのうちの第2のメモリセルとの間に挿入され、
前記第1の階層スイッチにおいて、前記第1のビット線と前記第1のメモリセルが接続され、
かつ、前記第2の階層スイッチにおいて、前記接地端子と前記第2のメモリセルが接続された時、前記第1および前記第2のメモリセルには第1の方向に電流が流れ、前記第1の階層スイッチにおいて、前記接地端子と前記第1のメモリセルが接続され、
かつ、前記第2の階層スイッチにおいて、前記第1のビット線と前記第2のメモリセルが接続された時、前記第1および前記第2のメモリセルには第2の方向に電流が流れ、前記第1の電流の向きと前記第2の電流の向きは互いに逆向きであり、
前記複数のメモリセルの各々は、前記記憶素子と前記トランジスタとが並列接続され、
前記記憶素子は、カルコゲナイド材料を含む材料であることを特徴とする半導体記憶装置。
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Families Citing this family (172)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009084514A1 (ja) * | 2007-12-27 | 2009-07-09 | Nec Corporation | 記憶素子、半導体記憶装置、および情報読み出し方法 |
US7768812B2 (en) | 2008-01-15 | 2010-08-03 | Micron Technology, Inc. | Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices |
KR100971423B1 (ko) * | 2008-04-04 | 2010-07-21 | 주식회사 하이닉스반도체 | 상변화 메모리 소자 및 그 제조방법 |
US8211743B2 (en) | 2008-05-02 | 2012-07-03 | Micron Technology, Inc. | Methods of forming non-volatile memory cells having multi-resistive state material between conductive electrodes |
US20110073357A1 (en) * | 2008-06-02 | 2011-03-31 | Nxp B.V. | Electronic device and method of manufacturing an electronic device |
US8134137B2 (en) | 2008-06-18 | 2012-03-13 | Micron Technology, Inc. | Memory device constructions, memory cell forming methods, and semiconductor construction forming methods |
US9343665B2 (en) | 2008-07-02 | 2016-05-17 | Micron Technology, Inc. | Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array |
KR101430171B1 (ko) * | 2008-07-18 | 2014-08-14 | 삼성전자주식회사 | 다중치 상변화 메모리 소자 |
JP5378722B2 (ja) * | 2008-07-23 | 2013-12-25 | ルネサスエレクトロニクス株式会社 | 不揮発性記憶装置およびその製造方法 |
EP2151827B1 (en) * | 2008-08-07 | 2012-02-01 | Sony Corporation | Electronic device for a reconfigurable logic circuit |
US11018133B2 (en) | 2009-10-12 | 2021-05-25 | Monolithic 3D Inc. | 3D integrated circuit |
US11374118B2 (en) | 2009-10-12 | 2022-06-28 | Monolithic 3D Inc. | Method to form a 3D integrated circuit |
US10157909B2 (en) | 2009-10-12 | 2018-12-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10366970B2 (en) | 2009-10-12 | 2019-07-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10354995B2 (en) | 2009-10-12 | 2019-07-16 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US10388863B2 (en) | 2009-10-12 | 2019-08-20 | Monolithic 3D Inc. | 3D memory device and structure |
US11984445B2 (en) | 2009-10-12 | 2024-05-14 | Monolithic 3D Inc. | 3D semiconductor devices and structures with metal layers |
US10043781B2 (en) | 2009-10-12 | 2018-08-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10910364B2 (en) | 2009-10-12 | 2021-02-02 | Monolitaic 3D Inc. | 3D semiconductor device |
US8411477B2 (en) | 2010-04-22 | 2013-04-02 | Micron Technology, Inc. | Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells |
US8427859B2 (en) | 2010-04-22 | 2013-04-23 | Micron Technology, Inc. | Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells |
US8289763B2 (en) * | 2010-06-07 | 2012-10-16 | Micron Technology, Inc. | Memory arrays |
US10217667B2 (en) | 2011-06-28 | 2019-02-26 | Monolithic 3D Inc. | 3D semiconductor device, fabrication method and system |
US8351242B2 (en) | 2010-09-29 | 2013-01-08 | Micron Technology, Inc. | Electronic devices, memory devices and memory arrays |
US11482440B2 (en) | 2010-12-16 | 2022-10-25 | Monolithic 3D Inc. | 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits |
US10497713B2 (en) | 2010-11-18 | 2019-12-03 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11257867B1 (en) | 2010-10-11 | 2022-02-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with oxide bonds |
US11469271B2 (en) | 2010-10-11 | 2022-10-11 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US11018191B1 (en) | 2010-10-11 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11158674B2 (en) | 2010-10-11 | 2021-10-26 | Monolithic 3D Inc. | Method to produce a 3D semiconductor device and structure |
US11024673B1 (en) | 2010-10-11 | 2021-06-01 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11600667B1 (en) | 2010-10-11 | 2023-03-07 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US11315980B1 (en) | 2010-10-11 | 2022-04-26 | Monolithic 3D Inc. | 3D semiconductor device and structure with transistors |
US11227897B2 (en) | 2010-10-11 | 2022-01-18 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
US10896931B1 (en) | 2010-10-11 | 2021-01-19 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10290682B2 (en) | 2010-10-11 | 2019-05-14 | Monolithic 3D Inc. | 3D IC semiconductor device and structure with stacked memory |
US11855114B2 (en) | 2010-10-13 | 2023-12-26 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US10679977B2 (en) | 2010-10-13 | 2020-06-09 | Monolithic 3D Inc. | 3D microdisplay device and structure |
US11855100B2 (en) | 2010-10-13 | 2023-12-26 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11063071B1 (en) | 2010-10-13 | 2021-07-13 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with waveguides |
US10833108B2 (en) | 2010-10-13 | 2020-11-10 | Monolithic 3D Inc. | 3D microdisplay device and structure |
US11437368B2 (en) | 2010-10-13 | 2022-09-06 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11404466B2 (en) | 2010-10-13 | 2022-08-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US10978501B1 (en) | 2010-10-13 | 2021-04-13 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with waveguides |
US11605663B2 (en) | 2010-10-13 | 2023-03-14 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11869915B2 (en) | 2010-10-13 | 2024-01-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11043523B1 (en) | 2010-10-13 | 2021-06-22 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US10998374B1 (en) | 2010-10-13 | 2021-05-04 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11133344B2 (en) | 2010-10-13 | 2021-09-28 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11164898B2 (en) | 2010-10-13 | 2021-11-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11163112B2 (en) | 2010-10-13 | 2021-11-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with electromagnetic modulators |
US11327227B2 (en) | 2010-10-13 | 2022-05-10 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with electromagnetic modulators |
US11694922B2 (en) | 2010-10-13 | 2023-07-04 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11984438B2 (en) | 2010-10-13 | 2024-05-14 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11929372B2 (en) | 2010-10-13 | 2024-03-12 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US10943934B2 (en) | 2010-10-13 | 2021-03-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US8759809B2 (en) | 2010-10-21 | 2014-06-24 | Micron Technology, Inc. | Integrated circuitry comprising nonvolatile memory cells having platelike electrode and ion conductive material layer |
US8526213B2 (en) | 2010-11-01 | 2013-09-03 | Micron Technology, Inc. | Memory cells, methods of programming memory cells, and methods of forming memory cells |
US8796661B2 (en) | 2010-11-01 | 2014-08-05 | Micron Technology, Inc. | Nonvolatile memory cells and methods of forming nonvolatile memory cell |
US11610802B2 (en) | 2010-11-18 | 2023-03-21 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes |
US11004719B1 (en) | 2010-11-18 | 2021-05-11 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11031275B2 (en) | 2010-11-18 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11164770B1 (en) | 2010-11-18 | 2021-11-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
US11121021B2 (en) | 2010-11-18 | 2021-09-14 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11615977B2 (en) | 2010-11-18 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11508605B2 (en) | 2010-11-18 | 2022-11-22 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11901210B2 (en) | 2010-11-18 | 2024-02-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11495484B2 (en) | 2010-11-18 | 2022-11-08 | Monolithic 3D Inc. | 3D semiconductor devices and structures with at least two single-crystal layers |
US11569117B2 (en) | 2010-11-18 | 2023-01-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US11355381B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11923230B1 (en) | 2010-11-18 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11107721B2 (en) | 2010-11-18 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with NAND logic |
US11094576B1 (en) | 2010-11-18 | 2021-08-17 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11211279B2 (en) | 2010-11-18 | 2021-12-28 | Monolithic 3D Inc. | Method for processing a 3D integrated circuit and structure |
US11784082B2 (en) | 2010-11-18 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11018042B1 (en) | 2010-11-18 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11355380B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | Methods for producing 3D semiconductor memory device and structure utilizing alignment marks |
US11862503B2 (en) | 2010-11-18 | 2024-01-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11854857B1 (en) | 2010-11-18 | 2023-12-26 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11482439B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors |
US11482438B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11443971B2 (en) | 2010-11-18 | 2022-09-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11804396B2 (en) | 2010-11-18 | 2023-10-31 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11521888B2 (en) | 2010-11-18 | 2022-12-06 | Monolithic 3D Inc. | 3D semiconductor device and structure with high-k metal gate transistors |
US11735462B2 (en) | 2010-11-18 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US9454997B2 (en) | 2010-12-02 | 2016-09-27 | Micron Technology, Inc. | Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells |
US8431458B2 (en) | 2010-12-27 | 2013-04-30 | Micron Technology, Inc. | Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells |
US8791447B2 (en) | 2011-01-20 | 2014-07-29 | Micron Technology, Inc. | Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells |
US8488365B2 (en) | 2011-02-24 | 2013-07-16 | Micron Technology, Inc. | Memory cells |
US8537592B2 (en) | 2011-04-15 | 2013-09-17 | Micron Technology, Inc. | Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells |
US10388568B2 (en) | 2011-06-28 | 2019-08-20 | Monolithic 3D Inc. | 3D semiconductor device and system |
US8536562B2 (en) * | 2012-02-22 | 2013-09-17 | Micron Technology, Inc. | Methods of forming memory structures and methods of forming memory arrays |
US11164811B2 (en) | 2012-04-09 | 2021-11-02 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers and oxide-to-oxide bonding |
US11088050B2 (en) | 2012-04-09 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers |
US11616004B1 (en) | 2012-04-09 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11594473B2 (en) | 2012-04-09 | 2023-02-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11476181B1 (en) | 2012-04-09 | 2022-10-18 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US10600888B2 (en) | 2012-04-09 | 2020-03-24 | Monolithic 3D Inc. | 3D semiconductor device |
US11881443B2 (en) | 2012-04-09 | 2024-01-23 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11735501B1 (en) | 2012-04-09 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11410912B2 (en) | 2012-04-09 | 2022-08-09 | Monolithic 3D Inc. | 3D semiconductor device with vias and isolation layers |
US11694944B1 (en) | 2012-04-09 | 2023-07-04 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11961827B1 (en) | 2012-12-22 | 2024-04-16 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11217565B2 (en) | 2012-12-22 | 2022-01-04 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11916045B2 (en) | 2012-12-22 | 2024-02-27 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11309292B2 (en) | 2012-12-22 | 2022-04-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11063024B1 (en) | 2012-12-22 | 2021-07-13 | Monlithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11784169B2 (en) | 2012-12-22 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11018116B2 (en) | 2012-12-22 | 2021-05-25 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11967583B2 (en) | 2012-12-22 | 2024-04-23 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11087995B1 (en) | 2012-12-29 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10903089B1 (en) | 2012-12-29 | 2021-01-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10651054B2 (en) | 2012-12-29 | 2020-05-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10115663B2 (en) | 2012-12-29 | 2018-10-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10600657B2 (en) | 2012-12-29 | 2020-03-24 | Monolithic 3D Inc | 3D semiconductor device and structure |
US11430668B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11004694B1 (en) | 2012-12-29 | 2021-05-11 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10892169B2 (en) | 2012-12-29 | 2021-01-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11430667B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11177140B2 (en) | 2012-12-29 | 2021-11-16 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10325651B2 (en) | 2013-03-11 | 2019-06-18 | Monolithic 3D Inc. | 3D semiconductor device with stacked memory |
US11935949B1 (en) | 2013-03-11 | 2024-03-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US11869965B2 (en) | 2013-03-11 | 2024-01-09 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US8902663B1 (en) | 2013-03-11 | 2014-12-02 | Monolithic 3D Inc. | Method of maintaining a memory state |
US11923374B2 (en) | 2013-03-12 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11088130B2 (en) | 2014-01-28 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10840239B2 (en) | 2014-08-26 | 2020-11-17 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11398569B2 (en) | 2013-03-12 | 2022-07-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10224279B2 (en) | 2013-03-15 | 2019-03-05 | Monolithic 3D Inc. | Semiconductor device and structure |
US9117749B1 (en) * | 2013-03-15 | 2015-08-25 | Monolithic 3D Inc. | Semiconductor device and structure |
US11341309B1 (en) | 2013-04-15 | 2022-05-24 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11487928B2 (en) | 2013-04-15 | 2022-11-01 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11720736B2 (en) | 2013-04-15 | 2023-08-08 | Monolithic 3D Inc. | Automation methods for 3D integrated circuits and devices |
US11574109B1 (en) | 2013-04-15 | 2023-02-07 | Monolithic 3D Inc | Automation methods for 3D integrated circuits and devices |
US9021414B1 (en) | 2013-04-15 | 2015-04-28 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11270055B1 (en) | 2013-04-15 | 2022-03-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11030371B2 (en) | 2013-04-15 | 2021-06-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US9184377B2 (en) * | 2013-06-11 | 2015-11-10 | Micron Technology, Inc. | Resistance variable memory cell structures and methods |
US10297586B2 (en) | 2015-03-09 | 2019-05-21 | Monolithic 3D Inc. | Methods for processing a 3D semiconductor device |
US11031394B1 (en) | 2014-01-28 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11107808B1 (en) | 2014-01-28 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US9583187B2 (en) * | 2015-03-28 | 2017-02-28 | Intel Corporation | Multistage set procedure for phase change memory |
US11056468B1 (en) | 2015-04-19 | 2021-07-06 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11011507B1 (en) | 2015-04-19 | 2021-05-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10825779B2 (en) | 2015-04-19 | 2020-11-03 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10381328B2 (en) | 2015-04-19 | 2019-08-13 | Monolithic 3D Inc. | Semiconductor device and structure |
US11956952B2 (en) | 2015-08-23 | 2024-04-09 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US11978731B2 (en) | 2015-09-21 | 2024-05-07 | Monolithic 3D Inc. | Method to produce a multi-level semiconductor memory device and structure |
CN115942752A (zh) | 2015-09-21 | 2023-04-07 | 莫诺利特斯3D有限公司 | 3d半导体器件和结构 |
US10522225B1 (en) | 2015-10-02 | 2019-12-31 | Monolithic 3D Inc. | Semiconductor device with non-volatile memory |
US12016181B2 (en) | 2015-10-24 | 2024-06-18 | Monolithic 3D Inc. | 3D semiconductor device and structure with logic and memory |
US10418369B2 (en) | 2015-10-24 | 2019-09-17 | Monolithic 3D Inc. | Multi-level semiconductor memory device and structure |
US11114464B2 (en) | 2015-10-24 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11296115B1 (en) | 2015-10-24 | 2022-04-05 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11991884B1 (en) | 2015-10-24 | 2024-05-21 | Monolithic 3D Inc. | 3D semiconductor device and structure with logic and memory |
US10847540B2 (en) | 2015-10-24 | 2020-11-24 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11937422B2 (en) | 2015-11-07 | 2024-03-19 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US11114427B2 (en) | 2015-11-07 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor processor and memory device and structure |
US10032713B2 (en) * | 2016-01-27 | 2018-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
US11329059B1 (en) | 2016-10-10 | 2022-05-10 | Monolithic 3D Inc. | 3D memory devices and structures with thinned single crystal substrates |
US11869591B2 (en) | 2016-10-10 | 2024-01-09 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11711928B2 (en) | 2016-10-10 | 2023-07-25 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11251149B2 (en) | 2016-10-10 | 2022-02-15 | Monolithic 3D Inc. | 3D memory device and structure |
US11930648B1 (en) | 2016-10-10 | 2024-03-12 | Monolithic 3D Inc. | 3D memory devices and structures with metal layers |
US11812620B2 (en) | 2016-10-10 | 2023-11-07 | Monolithic 3D Inc. | 3D DRAM memory devices and structures with control circuits |
US11296106B2 (en) | 2019-04-08 | 2022-04-05 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11763864B2 (en) | 2019-04-08 | 2023-09-19 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures with bit-line pillars |
US11158652B1 (en) | 2019-04-08 | 2021-10-26 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11018156B2 (en) | 2019-04-08 | 2021-05-25 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US10892016B1 (en) | 2019-04-08 | 2021-01-12 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US10991761B2 (en) | 2019-05-13 | 2021-04-27 | Sandisk Technologies Llc | Three-dimensional cross-point memory device containing inter-level connection structures and method of making the same |
US10879313B2 (en) | 2019-05-13 | 2020-12-29 | Sandisk Technologies Llc | Three-dimensional cross-point memory device containing inter-level connection structures and method of making the same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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TW200835007A (en) | 2008-08-16 |
JPWO2008068867A1 (ja) | 2010-03-18 |
WO2008068867A1 (ja) | 2008-06-12 |
US7864568B2 (en) | 2011-01-04 |
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