JP4923003B2 - Nanowire fabrication method, nanowire element, and nanowire structure - Google Patents

Nanowire fabrication method, nanowire element, and nanowire structure Download PDF

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JP4923003B2
JP4923003B2 JP2008186474A JP2008186474A JP4923003B2 JP 4923003 B2 JP4923003 B2 JP 4923003B2 JP 2008186474 A JP2008186474 A JP 2008186474A JP 2008186474 A JP2008186474 A JP 2008186474A JP 4923003 B2 JP4923003 B2 JP 4923003B2
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功太 舘野
国強 章
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Nippon Telegraph and Telephone Corp
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本発明は、ナノメートル級の大きさの金属微粒子を触媒とし、気相−液相−固相法を用いて結晶成長を行うナノワイヤ作製方法、ナノワイヤ素子、ナノワイヤ構造物に関するものであり、特に電子デバイスや光デバイスなどに応用が可能なものである。   The present invention relates to a nanowire manufacturing method, a nanowire element, and a nanowire structure in which nanometer-sized metal fine particles are used as a catalyst and crystal growth is performed using a gas phase-liquid phase-solid phase method. It can be applied to devices and optical devices.

金属触媒を用いてナノワイヤを成長する気相−液相−固相(VLS:Vapor-Liquid-Solid)法は、下記非特許文献1に示すように、1960年代に、Au微粒子とSi半導体を材料として確認された半導体成長法である。AuとSiが合金化することによって液状となる温度が単体の場合に比べて著しく低下し、共晶点で400℃近くまで下がる。Au以外の部分では、原料が結晶成長するには温度が低すぎるが、Au合金の部分では液状化して原料が分解し、Au合金内で原料のSiが過飽和状態となり、液相エピタキシ(LPE:Liquid-Phase Epitaxy)と同様のエピタキシャル成長が起きる。例えば、触媒をAu微粒子、基板をGaAs(111)B、原料としてトリメチルガリウム(TMGa)及びアルシン(AsH)を用いる。始めに、基板上に金属触媒を配置する。次に、有機金属気相成長(MOVPE:Metal Organic Vapor-Phase Epitaxial)法などの結晶成長装置内で成長を行う。400℃付近で原料を供給すると、{111}面や{110}、{100}、{112}面などの安定なマイクロファセットが周りに形成され、全体として安定するようにサイドファセットを形成しながら、特に[111]B方向に空間に立った状態(フリースタンディング)でGaAsのナノワイヤが成長する。また、下記非特許文献2では、ナノワイヤの成長温度など、成長条件について言及している。
R.S.Wagner and W.C.Ellis,APL4(1964)89. M.Mattila,Nanotechnology 17(2006)1580.
Vapor-Liquid-Solid (VLS) method for growing nanowires using a metal catalyst is based on Au fine particles and Si semiconductors in the 1960s, as shown in Non-Patent Document 1 below. It is a semiconductor growth method confirmed as follows. As a result of the alloying of Au and Si, the temperature of the liquid state is significantly reduced as compared with the case of a single substance, and the eutectic point is lowered to nearly 400 ° C. In parts other than Au, the temperature is too low for crystal growth of the raw material, but in the Au alloy part, the raw material is liquefied and the raw material decomposes, and the raw material Si becomes supersaturated in the Au alloy, so that liquid phase epitaxy (LPE: Epitaxial growth similar to Liquid-Phase Epitaxy occurs. For example, Au fine particles are used as a catalyst, GaAs (111) B is used as a substrate, and trimethylgallium (TMGa) and arsine (AsH 3 ) are used as raw materials. First, a metal catalyst is disposed on a substrate. Next, growth is performed in a crystal growth apparatus such as a metal organic vapor phase epitaxy (MOVPE) method. When the raw material is supplied at around 400 ° C., stable micro facets such as {111} face, {110}, {100}, {112} face are formed around, and side facets are formed so as to be stable as a whole. In particular, GaAs nanowires grow in a state of standing in space in the [111] B direction (free standing). Non-Patent Document 2 below refers to growth conditions such as the growth temperature of nanowires.
RSWagner and WCEllis, APL4 (1964) 89. M. Mattila, Nanotechnology 17 (2006) 1580.

しかしながら、フリースタンディングナノワイヤのような{111}方向のナノワイヤでは積層欠陥が形成されやすいため、たくさんの双晶が軸方向に形成される。また、前記非特許文献2に記載されるように、材料によっては、閃亜鉛鉱(Zincblende)構造のものがウルツ鉱(Wurtzute)構造になることがある。従って、バンド構造がナノワイヤ内で変化し、電子伝導特性や光学特性が単結晶のものより劣るという問題がある。
本発明は、これらの諸問題に着目して開発されたものであり、ナノワイヤの成長方向を制御することで結晶基板の結晶状態を維持し且つ欠陥のない単結晶のナノワイヤを成長させることが可能なナノワイヤ作製方法、ナノワイヤ素子、ナノワイヤ構造体を提供することを目的とするものである。
However, since a stacking fault is easily formed in a {111} -direction nanowire such as a free-standing nanowire, many twins are formed in the axial direction. Further, as described in Non-Patent Document 2, depending on the material, a zinc-blende (Zincblende) structure may become a wurtzite structure. Therefore, there is a problem that the band structure changes in the nanowire, and the electronic conduction characteristics and optical characteristics are inferior to those of the single crystal.
The present invention has been developed by paying attention to these problems, and by controlling the growth direction of the nanowire, it is possible to maintain the crystal state of the crystal substrate and grow single-crystal nanowires without defects. An object of the present invention is to provide a nanowire manufacturing method, a nanowire element, and a nanowire structure.

上記諸問題を解決するため、本発明者はフリースタンディングのナノワイヤ成長温度よりも低い温度で、且つGaAs(311)B基板とInPの原料であるトリメチルインジウム(TMIn)とフォスフィン(PH)の組合せで、結晶基板の表面と平行な方向(以下、単に横方向とも記す)への成長が起こることを見出した。図1aには走査型電子顕微鏡による成長後の基板表面を示す。また、図1bに示すように、GaAs(311)B基板とAlGaAsの原料であるトリメチルアルミニウム(TMAl)、TMGa、AsHの組合せで、基板表面上を[110]方向にナノワイヤを成長させることができることを確認した。そして、このような横方向成長のナノワイヤは、基板の結晶状態を維持して単結晶で成長するため、電子伝導特性や光学特性が良好であり、また、フリースタンディングでは難しいフレキシブルな網状、布状構造を容易に制御よく得ることも可能であり、より高密度な電子回路をフレキシブルなパネルシート内に形成することもでき、ディスプレイや太陽電池などへの応用の可能性がある。なお、このようなVLS成長法を用いた基板表面上の横方向ナノワイヤ成長技術は報告されていない。 In order to solve the above problems, the present inventor has a combination of trimethylindium (TMIn) and phosphine (PH 3 ), which are lower than the free-standing nanowire growth temperature, and a GaAs (311) B substrate and InP raw materials. Thus, it has been found that growth occurs in a direction parallel to the surface of the crystal substrate (hereinafter also simply referred to as a lateral direction). FIG. 1a shows the substrate surface after growth by a scanning electron microscope. Also, as shown in FIG. 1b, nanowires can be grown on the surface of the substrate in the [110] direction with a combination of a GaAs (311) B substrate and trimethylaluminum (TMAl), TMGa, AsH 3 which are AlGaAs raw materials. I confirmed that I can do it. Such laterally grown nanowires grow as a single crystal while maintaining the crystalline state of the substrate, so they have good electronic conductivity and optical properties, and are also flexible networks and cloths that are difficult to achieve with free standing. The structure can be easily obtained with good control, and a higher-density electronic circuit can be formed in a flexible panel sheet, which can be applied to displays, solar cells, and the like. In addition, a lateral nanowire growth technique on a substrate surface using such a VLS growth method has not been reported.

而して、本発明のナノワイヤ作製方法は、気相−液相−固相法を用い、ナノメートル級の大きさの金属微粒子を触媒として結晶成長を行うナノワイヤ作製方法であり、且つ結晶基板の表面と平行な方向に、当該結晶基板に接するナノワイヤを成長させる作製方法であって、前記結晶基板の表面に溝又はステップを形成した後に、前記結晶基板の結晶状態を維持し且つ欠陥のない単結晶のナノワイヤを、前記溝又はステップに沿って成長させることを特徴とするものである。 And Thus, nanowire manufacturing method of the present invention, vapor phase - liquid phase - a solid phase method, Ri nanowire manufacturing method der performing crystal growth of nanometric size of the fine metal particles as a catalyst, and the crystal substrate A method of growing nanowires in contact with the crystal substrate in a direction parallel to the surface of the substrate, wherein a groove or a step is formed on the surface of the crystal substrate, and the crystal state of the crystal substrate is maintained and defect-free A single-crystal nanowire is grown along the groove or step .

また、本発明のナノワイヤ作製方法は、前記ナノワイヤの成長中に、原料種の切り替え及び添加物の導入の少なくとも何れか一方を行うことにより、ヘテロ構造を有するナノワイヤを成長させることを特徴とするものである。 In addition, the nanowire manufacturing method of the present invention is characterized in that a nanowire having a heterostructure is grown by performing at least one of switching of raw material species and introduction of an additive during the growth of the nanowire. It is.

また、本発明のナノワイヤ作製方法は、前記成長方向が同一方向に揃った複数の第1のナノワイヤを作製した後、その上方に、前記第1のナノワイヤとは成長方向が異なり且つ互いの成長方向が同一方向に揃った複数の第2のナノワイヤを作製することにより、ナノワイヤからなる網状の半導体膜を形成することを特徴とするものである。 Further, in the nanowire manufacturing method of the present invention, after the plurality of first nanowires having the same growth direction aligned in the same direction, the growth direction is different from that of the first nanowires and the growth directions of the first nanowires are above the first nanowires. By forming a plurality of second nanowires having the same alignment in the same direction, a net-like semiconductor film made of nanowires is formed.

また、本発明のナノワイヤ素子は、前記ナノワイヤ作製方法で作製されたヘテロ構造を有するナノワイヤに電極を付設したことを特徴とするものである。
また、本発明のナノワイヤ構造物は、前記ナノワイヤ作製方法で網状の半導体膜を形成した後、結晶基板を除去して、当該半導体膜が空間に浮いた構造としたことを特徴とするものである。
The nanowire element of the present invention is characterized in that an electrode is attached to a nanowire having a heterostructure produced by the nanowire production method.
Further, the nanowire structure of the present invention is characterized in that after forming a net-like semiconductor film by the nanowire manufacturing method, the crystal substrate is removed to make the semiconductor film float in the space. .

本発明のナノワイヤ作製方法によれば、気相−液相−固相法を用い、ナノメートル級の大きさの金属微粒子を触媒として結晶成長を行うにあたり、結晶基板の表面と平行な方向に、当該結晶基板に接するナノワイヤを成長させることにより、前記結晶基板の結晶状態を維持し且つ欠陥のない単結晶のナノワイヤを成長させることが可能となる。また、溝やステップ、電界や磁界によってナノワイヤの結晶基板の表面と平行な方向への成長を制御することが可能となる。また、原料種の切り替え及び添加物の導入により、異なる特性の半導体を連続して作製することが可能となる。また、この技術を用いることにより、ナノメートル級の半導体、電子デバイス、光デバイスだけでなく、フレキシブルな網状の半導体構造物を、簡易に、安価に、且つ精度よく作製することができ、広範囲の分野に応用することが可能となる。   According to the method for producing a nanowire of the present invention, in performing crystal growth using a metal fine particle of a nanometer class using a gas phase-liquid phase-solid phase method as a catalyst, in a direction parallel to the surface of the crystal substrate, By growing nanowires in contact with the crystal substrate, it is possible to grow single-crystal nanowires that maintain the crystal state of the crystal substrate and have no defects. Further, the growth of the nanowire in the direction parallel to the surface of the crystal substrate can be controlled by the groove, step, electric field or magnetic field. In addition, semiconductors having different characteristics can be continuously produced by switching the raw material species and introducing additives. In addition, by using this technology, not only nanometer-class semiconductors, electronic devices, and optical devices, but also flexible network semiconductor structures can be manufactured easily, inexpensively, and with high accuracy. It becomes possible to apply to the field.

次に、本発明のナノワイヤ作製方法、ナノワイヤ素子、ナノワイヤ構造物の実施形態について、図面を用いながら説明する。
[第1実施形態]
図2aは、本発明のナノワイヤ作製方法の第1実施形態として、VLS法でナノワイヤ3を結晶基板1から成長させるために、触媒であるAu微粒子2を結晶基板1の表面に配置した状態を示し、図2bは、このAu微粒子2から結晶基板1の表面と平行な方向(横方向)に当該結晶基板1に接するナノワイヤ3を成長させた状態を示し、図2cは、従来のフリースタンディング状態のナノワイヤ3を示す。
Next, embodiments of the nanowire fabrication method, nanowire element, and nanowire structure of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 2a shows a state in which Au fine particles 2 as a catalyst are arranged on the surface of the crystal substrate 1 in order to grow the nanowire 3 from the crystal substrate 1 by the VLS method as a first embodiment of the nanowire production method of the present invention. 2b shows a state in which nanowires 3 that are in contact with the crystal substrate 1 are grown in a direction parallel to the surface of the crystal substrate 1 (lateral direction) from the Au fine particles 2, and FIG. 2c shows a conventional free-standing state. A nanowire 3 is shown.

空間に立ったフリースタンディングナノワイヤを可能にする、成長温度、圧力、原料供給量、化合物組成比などの成長条件が、前記従来技術に示されている。この成長条件は、一般に狭い範囲の条件であるため、その成長条件範囲からあえてずらした成長条件でナノワイヤを成長させることにより、前述したサイドファセットの形成を不安定にし、横方向成長を可能とする。   Growth conditions such as growth temperature, pressure, raw material supply amount, compound composition ratio, etc. that enable free standing nanowires standing in space are shown in the prior art. Since this growth condition is generally in a narrow range, by growing nanowires under growth conditions deviated from the growth condition range, the above-described side facet formation becomes unstable and lateral growth is possible. .

サイドファセットの形成を不安定にするには、フリースタンディングナノワイヤの成長条件から、成長温度を10度以上高い温度や10度以下の低い温度に設定したり、圧力を2倍以上の高い圧力や1/2以下の低い圧力に設定したり、原料供給量を2倍以上の多量や1/2以下の少量に変更したり、原料ガスと異なる他の元素を10%以上添加して化合物組成比を変化させたり、ナノワイヤと基板材料の格子定数差が1%以上になるように材料を選択したりすることにより行うが、これらの成長条件のうちの何れか一つ、又は、複数を組合せて行う。以下に、ナノワイヤの横方向成長の一例を示す。   In order to make the formation of the side facets unstable, the growth temperature is set to a temperature higher than 10 degrees or a temperature lower than 10 degrees from the growth conditions of the free-standing nanowires, / 2 or lower pressure, change the raw material supply amount to more than twice or less than 1/2, or add 10% or more of other elements different from the source gas to increase the compound composition ratio This is done by changing the material or selecting the material so that the difference in the lattice constant between the nanowire and the substrate material is 1% or more, but any one of these growth conditions, or a combination of a plurality of them. . Below, an example of the lateral growth of nanowires is shown.

GaAs(311)B基板の表面に直径10nmのAu微粒子を、Auの蒸着とアニールによる自己形成、或いはAu微粒子を含む溶液の塗布などの方法によって分散させた。その後、基板をMOVPE装置内に設置し、380℃でTMIn 1×10−5mol/minとPH 6×10−4mol/minを導入してInPナノワイヤを5分成長した。前記図1aに示すナノワイヤは、この成長条件で横方向にVLS成長したInPナノワイヤである。この場合、InPとGaAsの格子定数差が4%もあり、また温度も、InP基板上のフリースタンディングナノワイヤの成長温度より20℃程度低いため、フリースタンディングでナノワイヤが成長するよりも横方向成長の方が安定し、ナノワイヤの横方向成長が可能となる。 Au fine particles having a diameter of 10 nm were dispersed on the surface of the GaAs (311) B substrate by a method such as self-formation by vapor deposition and annealing of Au, or application of a solution containing Au fine particles. Thereafter, the substrate was placed in a MOVPE apparatus, and TMIn 1 × 10 −5 mol / min and PH 3 6 × 10 −4 mol / min were introduced at 380 ° C. to grow InP nanowires for 5 minutes. The nanowire shown in FIG. 1a is an InP nanowire that has been VLS grown laterally under this growth condition. In this case, the lattice constant difference between InP and GaAs is 4%, and the temperature is about 20 ° C. lower than the growth temperature of the free-standing nanowire on the InP substrate. This is more stable and enables the nanowire to grow in the lateral direction.

[第2実施形態]
次に、本発明のナノワイヤ作製方法の第2実施形態について説明する。本実施形態では、図3に示すように、GaAs(100)基板1の表面に電子線リソグラフィにより幅20nm、深さ20nm、長さ5μmの溝4を[110]方向に形成した。その後、触媒として直径100nmのAu微粒子2を、Auの蒸着とアニールによる自己形成、或いは電子線リソグラフィによるパターニング、或いはAu微粒子1を含む溶液の塗布などの方法によって溝3の内部に配置した。
[Second Embodiment]
Next, 2nd Embodiment of the nanowire preparation method of this invention is described. In the present embodiment, as shown in FIG. 3, a groove 4 having a width of 20 nm, a depth of 20 nm, and a length of 5 μm is formed in the [110] direction on the surface of the GaAs (100) substrate 1 by electron beam lithography. Thereafter, Au fine particles 2 having a diameter of 100 nm as a catalyst were arranged inside the grooves 3 by a method such as self-formation by Au deposition and annealing, patterning by electron beam lithography, or application of a solution containing Au fine particles 1.

Au微粒子2の形成後、基板1をMOVPE装置内に設置し、前記第1実施形態と同様に、サイドファセット形成が不安定になるように、成長温度、圧力、原料供給量、化合物組成比を設定して、溝4に沿ったナノワイヤ3の横方向成長を行った。この横方向成長条件としては、例えば380℃でTMIn 1×10−5mol/minとPH 6×10−4mol/minを導入してInPナノワイヤを溝4に沿って5分成長した。このサンプルの発光特性を、フォトルミネッセンス測定により測定したところ、図4に示すように、910nm付近にピークを有するInPの発光を確認した。なお、本実施形態では、結晶基板としてGaAs基板を用いたが、Si、GaP、InP、サファイヤ基板などでもよく、格子定数差が臨界膜厚を超えない条件でナノワイヤの半導体材料を選択することができる。また、結晶基板には、AlGaAsやGaInAsなどの三元混晶も使用可能である。 After the formation of the Au fine particles 2, the substrate 1 is placed in the MOVPE apparatus, and the growth temperature, pressure, raw material supply amount, and compound composition ratio are set so that the side facet formation becomes unstable as in the first embodiment. As set, lateral growth of the nanowire 3 along the groove 4 was performed. As this lateral growth condition, for example, TMIn 1 × 10 −5 mol / min and PH 3 6 × 10 −4 mol / min were introduced at 380 ° C., and InP nanowires were grown along the grooves 4 for 5 minutes. When the emission characteristics of this sample were measured by photoluminescence measurement, the emission of InP having a peak near 910 nm was confirmed as shown in FIG. In this embodiment, a GaAs substrate is used as the crystal substrate. However, a Si, GaP, InP, sapphire substrate, or the like may be used, and a nanowire semiconductor material may be selected under the condition that the lattice constant difference does not exceed the critical film thickness. it can. Further, a ternary mixed crystal such as AlGaAs or GaInAs can be used for the crystal substrate.

[第3実施形態]
次に、本発明のナノワイヤ作製方法及びナノワイヤ素子の第3実施形態について説明する。本実施形態では、まず図5aに示すように、半絶縁性のGaAs(311)B基板1の表面に触媒として直径40nmのAu微粒子2を、Auの蒸着とアニールによる自己形成、或いは電子線リソグラフィによるパターニング、或いはAu微粒子2を含む溶液の塗布などの方法によって配置した。Au微粒子2の形成後、図5bに示すように、MOVPE装置内に設置し、380℃でTMIn 1×10−5mol/minとPH 6×10−4mol/min、ドーパントとしてジシラン(Si)を2×10−7mol/min導入してn型InPナノワイヤ3nを2分成長した。これに続いて、図5cに示すように、TMIn 1×10−5mol/minとPH 6×10−4mol/min、ドーパントとしてジエチクルジンク(DEZn)を2×10−7mol/min導入してp型InPナノワイヤ3pを2分成長した。何れのナノワイヤ3n、3pも、図中の原子ステップ8に沿った方向である[110]方向に横方向に基板表面に沿って成長した。最後に、図6に示すように、n型InPナノワイヤ3n部分にはAuGeNiでn型電極5nを形成し、p型InPナノワイヤ3p部分にはAuZnNiでp型電極5pを形成した。n型InPナノワイヤ3nとp型InPナノワイヤ3pの間には、i−GaInAsのヘテロ界面7が存在し、全体としてヘテロ構造をなす。このナノワイヤ3n、3pに電圧を印加して電流を流したところ、それらナノワイヤ3n,3pはダイオード特性を示し、図7に注入電流に対する発光強度を示す。良好な発光ダイオード特性を示した。
[Third Embodiment]
Next, a third embodiment of the nanowire manufacturing method and the nanowire element of the present invention will be described. In this embodiment, first, as shown in FIG. 5a, Au fine particles 2 having a diameter of 40 nm as a catalyst are formed on the surface of a semi-insulating GaAs (311) B substrate 1 by self-forming by Au vapor deposition and annealing, or electron beam lithography. It arrange | positioned by methods, such as the patterning by A, or application | coating of the solution containing Au microparticles | fine-particles 2. After the formation of the Au fine particles 2, as shown in FIG. 5b, it is placed in a MOVPE apparatus, TMIn 1 × 10 −5 mol / min and PH 3 6 × 10 −4 mol / min at 380 ° C., and disilane (Si 2 H 6 ) was introduced at 2 × 10 −7 mol / min to grow n-type InP nanowires 3n for 2 minutes. Subsequently, as shown in FIG. 5c, TMIn 1 × 10 −5 mol / min and PH 3 6 × 10 −4 mol / min and 2 × 10 −7 mol / min of diethyl zinc (DEZn) as a dopant were introduced. Then, the p-type InP nanowire 3p was grown for 2 minutes. All the nanowires 3n and 3p were grown along the substrate surface in the [110] direction, which is the direction along the atomic step 8 in the figure. Finally, as shown in FIG. 6, an n-type electrode 5n was formed of AuGeNi on the n-type InP nanowire 3n portion, and a p-type electrode 5p of AuZnNi was formed on the p-type InP nanowire 3p portion. An i-GaInAs heterointerface 7 exists between the n-type InP nanowire 3n and the p-type InP nanowire 3p, and forms a heterostructure as a whole. When a current was applied by applying a voltage to the nanowires 3n and 3p, the nanowires 3n and 3p showed diode characteristics, and FIG. 7 shows the emission intensity with respect to the injected current. Good light-emitting diode characteristics were shown.

[第4実施形態]
次に、本発明のナノワイヤ作製方法及びナノワイヤ構造物の第4実施形態について説明する。本実施形態では、まず図8aに示すように、GaAs(100)基板1の表面に触媒として直径100nmのAu微粒子2を、電子線リソグラフィによるパターニングによって、直線上に等間隔に7つ配置した。このAu微粒子2の形成後、基板1をMOVPE装置内に設置し、図8bに示すように、Au微粒子2の配列方向と直交方向に矢印で示す1.5×10V/mの電界を加えながら、TMIn 1×10−5mol/minとPH 6×10−4mol/min、ドーパントとしてジシラン(Si)を2×10−7mol/min導入して7本のn型InPナノワイヤ3nを互いに平行に横方向、つまり電界方向に5分成長した。次に、図8cに示すように、n型InPナノワイヤ3nの成長方向先端部に相当するAu微粒子2の部分にSiOを蒸着してマスク6を形成し、次いでGaAs(100)基板1の表面上のn型InPナノワイヤ3nの成長方向側方に、同じく触媒として直径100nmのAu微粒子2を電子線リソグラフィによって直線上に等間隔に7つ配置した。その後、新たに形成したAu微粒子2の配列方向と直交方向、即ちn型InPナノワイヤ3nの成長方向と直交方向に矢印で示す電界を前述と同様に加えながら、図8dに示すように、既設のn型InPナノワイヤ3nに直交する7本のn型InPナノワイヤ3nを電界方向に5分成長し、網状のナノワイヤ3nによる構造物を得た。
[Fourth Embodiment]
Next, a nanowire manufacturing method and a nanowire structure according to a fourth embodiment of the present invention will be described. In the present embodiment, first, as shown in FIG. 8a, seven Au fine particles 2 having a diameter of 100 nm as a catalyst are arranged on the surface of a GaAs (100) substrate 1 at regular intervals on a straight line by patterning by electron beam lithography. After the formation of the Au fine particles 2, the substrate 1 is placed in the MOVPE apparatus, and as shown in FIG. 8b, an electric field of 1.5 × 10 5 V / m indicated by an arrow in the direction perpendicular to the arrangement direction of the Au fine particles 2 is applied. While adding TMIn 1 × 10 −5 mol / min and PH 3 6 × 10 −4 mol / min and disilane (Si 2 H 6 ) as a dopant 2 × 10 −7 mol / min, 7 n-types were introduced. InP nanowires 3n were grown in parallel in the lateral direction, that is, in the electric field direction for 5 minutes. Next, as shown in FIG. 8 c, SiO is deposited on the Au fine particle 2 portion corresponding to the tip of the growth direction of the n-type InP nanowire 3 n to form a mask 6, and then on the surface of the GaAs (100) substrate 1. On the side of the growth direction of the n-type InP nanowires 3n, seven Au fine particles 2 having a diameter of 100 nm were also arranged on the straight line at equal intervals by electron beam lithography. Then, while applying an electric field indicated by an arrow in the direction orthogonal to the direction of arrangement of the newly formed Au fine particles 2, that is, the direction orthogonal to the growth direction of the n-type InP nanowire 3n, as shown in FIG. Seven n-type InP nanowires 3n orthogonal to the n-type InP nanowires 3n were grown in the electric field direction for 5 minutes to obtain a structure made of network-like nanowires 3n.

この状態から、HSO/H/HO=1/10/50の溶液を用いて基板1をエッチングすることにより、図9に示すような網状のナノワイヤ膜構造物を作ることができる。この構造に樹脂を塗布することによりフレキシブルに曲げられるシート状の半導体膜を作製することができる。また、転写技術、所謂インプリント技術によって、他の基板にInPナノワイヤの網構造を転写することも可能である。また、選択的に基板1をエッチングすることによって、基板1からナノワイヤ網状構造物が空間に浮いたような構造とすることもできる。更には、ナノワイヤ網状構造物を多数、密接に作製することにより布状にすることもできる。なお、ナノワイヤ成長方向を制御する力は、電界に代えて、磁界を印加するようにしてもよい。
なお、本発明のナノワイヤ作製方法、ナノワイヤ素子、ナノワイヤ構造物は、前記実施形態に限定されるものではなく、本発明の主旨を逸脱しない範囲で、広く応用可能なものである。
From this state, the substrate 1 is etched using a solution of H 2 SO 4 / H 2 O 2 / H 2 O = 1/10/50, thereby forming a network-like nanowire film structure as shown in FIG. be able to. By applying a resin to this structure, a sheet-like semiconductor film that can be flexibly bent can be manufactured. It is also possible to transfer the network structure of InP nanowires to another substrate by transfer technology, so-called imprint technology. Further, by selectively etching the substrate 1, a structure in which the nanowire network structure floats in the space from the substrate 1 can also be obtained. Further, a large number of nanowire network structures can be made closely to form a cloth. The force for controlling the nanowire growth direction may be a magnetic field instead of an electric field.
In addition, the nanowire production method, nanowire element, and nanowire structure of the present invention are not limited to the above-described embodiments, and can be widely applied without departing from the gist of the present invention.

(a)はGaAs(311)B基板表面に横方向に成長したInPナノワイヤの説明図であり、(b)はGaAs(311)B基板表面に横方向に成長したAlGaAsナノワイヤの説明図である。(A) is explanatory drawing of InP nanowire grown laterally on the surface of GaAs (311) B substrate, (b) is explanatory drawing of AlGaAs nanowire grown laterally on the surface of GaAs (311) B substrate. (a)は結晶基板の表面に金属触媒を配置した状態の断面図、(b)は本発明の第1実施形態として結晶基板の表面に横方向に成長したナノワイヤの断面図、(c)は従来のフリースタンディングナノワイヤの断面図である。(A) is a cross-sectional view of a state in which a metal catalyst is disposed on the surface of the crystal substrate, (b) is a cross-sectional view of a nanowire grown laterally on the surface of the crystal substrate as a first embodiment of the present invention, and (c) is a cross-sectional view of the nanowire. It is sectional drawing of the conventional free standing nanowire. 本発明の第2実施形態として結晶基板表面の溝に沿って成長したナノワイヤの説明図である。It is explanatory drawing of the nanowire grown along the groove | channel of the crystal substrate surface as 2nd Embodiment of this invention. 図3のナノワイヤの発光強度の説明図である。It is explanatory drawing of the emitted light intensity of the nanowire of FIG. 本発明の第3実施形態として原子ステップに沿ったナノワイヤの成長途中でドーパントを変更し、ヘテロ構造としたナノワイヤの説明図である。It is explanatory drawing of the nanowire which changed the dopant during the growth of the nanowire along the atomic step as 3rd Embodiment of this invention, and was set as the heterostructure. 図5のナノワイヤに電極を付設してナノワイヤ素子とした状態の説明図である。It is explanatory drawing of the state which attached the electrode to the nanowire of FIG. 5, and was set as the nanowire element. 図6のナノワイヤの注入電流に対する発光特性の説明図である。It is explanatory drawing of the light emission characteristic with respect to the injection current of the nanowire of FIG. 本発明の第4実施形態として結晶基板の表面に網状の半導体膜に形成されたナノワイヤ構造物の説明図である。It is explanatory drawing of the nanowire structure formed in the net-like semiconductor film on the surface of the crystal substrate as 4th Embodiment of this invention. 図8のナノワイヤ構造物から基板を除去した状態の説明図である。It is explanatory drawing of the state which removed the board | substrate from the nanowire structure of FIG.

符号の説明Explanation of symbols

1は基板、2はAu微粒子(触媒)、3、3n、3pはナノワイヤ、4は溝、5n、5pは電極、6はマスク、7はヘテロ界面、8は原子ステップ   1 is substrate, 2 is Au fine particle (catalyst), 3n, 3p is nanowire, 4 is groove, 5n, 5p is electrode, 6 is mask, 7 is hetero interface, 8 is atomic step

Claims (6)

気相−液相−固相法を用い、ナノメートル級の大きさの金属微粒子を触媒として結晶成長を行うナノワイヤ作製方法であり、且つ結晶基板の表面と平行な方向に、当該結晶基板に接するナノワイヤを成長させる作製方法であって、前記結晶基板の表面に溝又はステップを形成した後に、前記結晶基板の結晶状態を維持し且つ欠陥のない単結晶のナノワイヤを、前記溝又はステップに沿って成長させることを特徴とするナノワイヤ作製方法。 Vapor - liquid phase - a solid phase method, the nanometric size of the metal particles Ri nanowire manufacturing method der performing crystal growth as a catalyst, and in a direction parallel to the surface of the crystal substrate, on the crystal substrate A method of growing nanowires in contact with each other, wherein after forming grooves or steps on the surface of the crystal substrate, single crystal nanowires that maintain the crystal state of the crystal substrate and have no defects are formed along the grooves or steps. A method for producing nanowires, characterized in that the nanowires are grown. 前記ナノワイヤの成長中に、原料種の切り替え及び添加物の導入の少なくとも何れか一方を行うことにより、ヘテロ構造を有するナノワイヤを成長させることを特徴とする請求項1に記載のナノワイヤ作製方法。 2. The nanowire manufacturing method according to claim 1, wherein a nanowire having a heterostructure is grown by performing at least one of switching of raw material species and introduction of an additive during the growth of the nanowire. 前記成長方向が同一方向に揃った複数の第1のナノワイヤを作製した後、その上方に、前記第1のナノワイヤとは成長方向が異なり且つ互いの成長方向が同一方向に揃った複数の第2のナノワイヤを作製することにより、ナノワイヤからなる網状の半導体膜を形成することを特徴とする請求項1又は2に記載のナノワイヤ作製方法。 After producing a plurality of first nanowires having the same growth direction aligned in the same direction, a plurality of second nanowires having a growth direction different from that of the first nanowires and having the growth directions aligned in the same direction above the first nanowires. A nanowire production method according to claim 1 or 2 , wherein a network semiconductor film made of nanowires is formed by producing the nanowire. 請求項に記載のナノワイヤ作製方法で作製されたヘテロ構造を有するナノワイヤに電極を付設したことを特徴とするナノワイヤ素子。 A nanowire element comprising an electrode attached to a nanowire having a heterostructure produced by the nanowire production method according to claim 2 . 請求項に記載のナノワイヤ作製方法で網状の半導体膜を形成した後、結晶基板を除去して、当該半導体膜が空間に浮いた構造としたことを特徴とするナノワイヤ構造物。 A nanowire structure characterized in that after forming a network semiconductor film by the nanowire manufacturing method according to claim 3 , the crystal substrate is removed to make the semiconductor film float in the space. 気相−液相−固相法を用い、ナノメートル級の大きさの金属微粒子を触媒として結晶成長を行うナノワイヤ作製方法として、結晶基板の表面と平行な方向に、当該結晶基板に接するナノワイヤを成長させることにより、前記結晶基板の結晶状態を維持し且つ欠陥のない単結晶のナノワイヤを成長させ、前記成長方向が同一方向に揃った複数の第1のナノワイヤを作製した後、その上方に、前記第1のナノワイヤとは成長方向が異なり且つ互いの成長方向が同一方向に揃った複数の第2のナノワイヤを作製することにより、ナノワイヤからなる網状の半導体膜を形成するナノワイヤ作製方法で網状の半導体膜を形成した後、結晶基板を除去して、当該半導体膜が空間に浮いた構造としたことを特徴とするナノワイヤ構造物。As a nanowire manufacturing method for growing crystals using metal fine particles of nanometer size using a gas phase-liquid phase-solid phase method as a catalyst, nanowires in contact with the crystal substrate in a direction parallel to the surface of the crystal substrate By growing the single-crystal nanowires that maintain the crystal state of the crystal substrate and have no defects, and produce a plurality of first nanowires in which the growth directions are aligned in the same direction, A nanowire manufacturing method for forming a network semiconductor film made of nanowires by forming a plurality of second nanowires having a growth direction different from that of the first nanowires and in which the growth directions are aligned in the same direction. A nanowire structure characterized in that after a semiconductor film is formed, the crystal substrate is removed so that the semiconductor film floats in space.
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