JP4899365B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4899365B2
JP4899365B2 JP2005210068A JP2005210068A JP4899365B2 JP 4899365 B2 JP4899365 B2 JP 4899365B2 JP 2005210068 A JP2005210068 A JP 2005210068A JP 2005210068 A JP2005210068 A JP 2005210068A JP 4899365 B2 JP4899365 B2 JP 4899365B2
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furnace
temperature
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trench
oxide film
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晴司 野口
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Fuji Electric Co Ltd
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Description

本発明は、半導体装置の製造方法に関し、特には、トレンチを用いた誘電体分離構造を有する半導体装置の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a dielectric isolation structure using a trench.

相互に素子分離を必要とする低耐圧の制御回路デバイスと高耐圧デバイスなどとを同一基板上に形成するパワーＩＣにおいて、分離に要する面積の縮小や前記デバイスに内蔵される寄生デバイスによる悪影響の低減または素子分離機能を完全にする等のためにＳＯＩ基板が利用される。ＳＯＩ基板は半導体支持基板上に絶縁膜を挟んで半導体機能層を形成するための半導体層（基板）を貼り合わせた構造となっている。前記半導体層はＳＯＩ基板上で素子分離構造と前記支持基板上の絶縁膜とにより囲まれた複数の半導体島領域に相互に絶縁分離され、それぞれの半導体島領域内に、前記制御回路デバイスや高耐圧デバイス等の機能領域が形成される。そのような素子分離構造として、前記半導体層に表面から前記絶縁膜に達するように形成されたトレンチにノンドープポリシリコンやシリコン酸化膜などの絶縁膜を充填させた誘電体分離構造が知られている。   In a power IC in which a low-breakdown-voltage control circuit device and a high-breakdown-voltage device that require element isolation are formed on the same substrate, reduction of the area required for separation and reduction of adverse effects due to parasitic devices incorporated in the device Alternatively, an SOI substrate is used to complete the element isolation function. The SOI substrate has a structure in which a semiconductor layer (substrate) for forming a semiconductor functional layer is bonded to a semiconductor support substrate with an insulating film interposed therebetween. The semiconductor layer is insulated and isolated from each other into a plurality of semiconductor island regions surrounded by an element isolation structure and an insulating film on the support substrate on an SOI substrate. A functional region such as a breakdown voltage device is formed. As such an element isolation structure, a dielectric isolation structure is known in which a trench formed in the semiconductor layer so as to reach the insulating film from the surface is filled with an insulating film such as non-doped polysilicon or silicon oxide film. .

従来の前記誘電体分離構造を有するＳＯＩ半導体基板の製造方法について説明する。
たとえば、図３（ａ）に示すように、半導体支持基板５１の上に絶縁膜５２を介して形成された半導体層５３（半導体基板）の表面にエッチングマスク層５４を形成し、それにフッ素系混合ガスを用いて異方性エッチングを施し、誘電体分離構造用トレンチ形成予定領域を窓開けする。
次に、図３（ｂ）に示すように、エッチングマスク層５４の窓開け部から、フッ素系混合ガスを用いて異方性のプラズマエッチングを施して、絶縁膜５２にまで達する前記誘電体分離構造用トレンチ（以降分離用トレンチ５５と略）５５を形成する。ここで、前記分離用トレンチ５５の幅は１〜４μｍ、その深さは１０〜４０μｍである。
次に、エッチングマスク層５４を除去した後、図３（ｃ）に示すように、半導体層５３の表面側を、約１１５０℃の水蒸気雰囲気中で約１００分間、熱酸化して、前記分離用トレンチ５５の側壁に厚さが約１μｍの側壁絶縁膜５６を形成する。このとき、分離用トレンチ５５の外部の半導体層５３の表面側にも絶縁膜５６ａが形成される。 A conventional method for manufacturing an SOI semiconductor substrate having the dielectric isolation structure will be described.
For example, as shown in FIG. 3A, an etching mask layer 54 is formed on the surface of a semiconductor layer 53 (semiconductor substrate) formed on an insulating film 52 on a semiconductor support substrate 51, and a fluorine-based mixture is formed thereon. An anisotropic etching is performed using a gas to open a region where a dielectric isolation structure trench is to be formed.
Next, as shown in FIG. 3B, anisotropic dielectric etching is performed using a fluorine-based mixed gas from the window opening portion of the etching mask layer 54 to reach the insulating film 52. A structural trench (hereinafter abbreviated as isolation trench 55) 55 is formed. Here, the isolation trench 55 has a width of 1 to 4 [mu] m and a depth of 10 to 40 [mu] m.
Next, after removing the etching mask layer 54, as shown in FIG. 3C, the surface side of the semiconductor layer 53 is thermally oxidized for about 100 minutes in a steam atmosphere at about 1150 ° C. A sidewall insulating film 56 having a thickness of about 1 μm is formed on the sidewall of the trench 55. At this time, the insulating film 56 a is also formed on the surface side of the semiconductor layer 53 outside the isolation trench 55.

次に、図３（ｄ）に示すように、熱ＣＶＤ法により、半導体層５３の表面側に多結晶半導体層５７（充填層）を堆積して分離用トレンチ５５の内部を埋め込む。このとき、分離用トレンチ５５の外部の半導体層５３の表面側にも多結晶半導体層５７ａが堆積する。
次に、図４（ａ）に示すように、半導体層５３の表面側にエッチバックまたは研磨を施して、分離用トレンチ５５の外部の多結晶半導体層５７ａを除去する。
しかる後に、図４（ｂ）に示すように、希フッ酸を用いて分離用トレンチ５５の外部の絶縁膜５６ａを除去すると、半導体層５３に、側壁絶縁膜５６および多結晶半導体層５７を備える分離用トレンチ５５と、絶縁膜５２とによって素子分離された半導体島領域を備える誘電体分離構造を備えたＳＯＩ半導体基板５０が形成される。
次に、図４（ｃ）に示すように、半導体層５３に形成された半導体島領域としての素子形成領域５０ａ，５０ｂ，５０ｃ，５０ｄに第１のダイオード５９ａ，ｐｎｐトランジスタ５９ｂ，ＭＯＳＦＥＴ５９ｃおよび第２のダイオード５９ｄをそれぞれ形成して集積回路を構成する発明が知られている（特許文献１）。 Next, as shown in FIG. 3D, a polycrystalline semiconductor layer 57 (filling layer) is deposited on the surface side of the semiconductor layer 53 by thermal CVD to bury the inside of the isolation trench 55. At this time, the polycrystalline semiconductor layer 57 a is also deposited on the surface side of the semiconductor layer 53 outside the isolation trench 55.
Next, as shown in FIG. 4A, the semiconductor layer 53 is etched back or polished to remove the polycrystalline semiconductor layer 57 a outside the isolation trench 55.
Thereafter, as shown in FIG. 4B, when the insulating film 56a outside the isolation trench 55 is removed using dilute hydrofluoric acid, the semiconductor layer 53 includes the sidewall insulating film 56 and the polycrystalline semiconductor layer 57. An SOI semiconductor substrate 50 having a dielectric isolation structure including a semiconductor island region that is isolated by the isolation trench 55 and the insulating film 52 is formed.
Next, as shown in FIG. 4C, the first diode 59a, the pnp transistor 59b, the MOSFET 59c and the second diode are formed in the element formation regions 50a, 50b, 50c, and 50d as semiconductor island regions formed in the semiconductor layer 53. An invention is known in which an integrated circuit is formed by forming the respective diodes 59d (Patent Document 1).

前述のように、トレンチを用いた前記誘電体分離構造は前記半導体層にトレンチを形成した後、トレンチ内に酸化膜を充填したり、前述のように薄い酸化膜を介してノンドープポリシリコンを充填して形成される。また、前記誘電体分離構造を形成するタイミングとしては、前記各半導体島領域内に制御回路や高耐圧デバイスなどの機能領域を形成する前に行う場合と、前記機能領域を形成した後に行う場合とがあり、必要に応じて選択される。いずれにしても、前記半導体島領域内に形成される機能領域の電気特性やその信頼性に悪影響を及ぼさないように、または逆に前記機能領域の形成条件により前記誘電体分離構造の形成条件に制約を受けるので、分離構造の形成方法、形成条件および形成時期を適切に選択する必要がある。前述の特許文献１に記載のトレンチへのポリシシリコンの充填による誘電体分離構造は、各半導体島領域内に制御回路や高耐圧デバイスなどの機能領域を形成する前に行う場合には適しているが、後に行う場合は、絶縁性の高く質の高い薄い熱酸化膜の形成が困難なため、分離性能が充分に発揮されないことがある。従って、半導体島領域内に機能領域を形成した後に、良好なトレンチによる誘電体分離構造を設ける場合の製造方法の改良が望まれている。以降の説明では、前記半導体島領域内への機能領域の形成後に、前記誘電体分離構造を形成する場合に限定して説明することとする。この場合、前記分離構造の形成の際には、半導体島領域内の機能領域に悪影響を及ぼすような高温の熱処理などを行うことはできないという制約を受けるので、この点を考慮する必要がある。   As described above, in the dielectric isolation structure using a trench, after forming a trench in the semiconductor layer, the trench is filled with an oxide film or filled with non-doped polysilicon through a thin oxide film as described above. Formed. In addition, the timing of forming the dielectric isolation structure may be performed before forming a functional region such as a control circuit or a high breakdown voltage device in each semiconductor island region, or after forming the functional region. And is selected as needed. In any case, in order not to adversely affect the electrical characteristics and reliability of the functional region formed in the semiconductor island region, or conversely, the formation condition of the dielectric isolation structure is determined by the functional region formation condition. Since it is restricted, it is necessary to appropriately select the formation method, formation conditions, and formation time of the separation structure. The dielectric isolation structure by filling the trench with the polysilicon described in Patent Document 1 is suitable when it is performed before forming a functional region such as a control circuit or a high voltage device in each semiconductor island region. However, when it is performed later, it is difficult to form a thin thermal oxide film with high insulation and high quality, so that the separation performance may not be sufficiently exhibited. Therefore, it is desired to improve the manufacturing method in the case where a dielectric isolation structure with a good trench is provided after the functional region is formed in the semiconductor island region. In the following description, only the case where the dielectric isolation structure is formed after the functional region is formed in the semiconductor island region will be described. In this case, when the isolation structure is formed, there is a restriction that high-temperature heat treatment or the like that adversely affects the functional region in the semiconductor island region cannot be performed.

さらに、前記誘電体分離構造のトレンチ幅は狭い方がコスト的に有利である。しかし、その結果、トレンチ形状は深さと幅との比、すなわち、深さ／幅が高アスペクト比となり、ますます、酸化膜を充填する際にトレンチ開口部が先に塞がれやすくなって、トレンチ中にボイドを巻き込み易くなるという課題が生じる。この課題の克服も重要である。
前記トレンチに充填されるシリコン酸化膜としては、シラン系材料を用いたＣＶＤ酸化膜よりも、カバレッジ性の高い有機系材料から形成されるＴＥＯＳ（テトラエチルオルソシリケート）酸化膜が一般的に好ましく用いられる。その中でも高アスペクト比を有するトレンチへの充填には、ボイドを形成し難くてカバレッジ性に特に優れたＬＰ（Ｌｏｗ Ｐｒｅｓｓｕｒｅ）−ＴＥＯＳ酸化膜が特に好ましい。ＬＰ−ＴＥＯＳ酸化膜は減圧ＣＶＤ法により、有機系のＴＥＯＳガスと酸素系ガスとの反応により形成されるシリコン酸化膜であり、前述のようにステップカバレッジ性が特に優れている。ただし、絶縁性を高めて膜質を上げるには膜中に残存する炭素Ｃと水素Ｈ原子を充分に除去するため、ポストアニールを行う必要がある。 Furthermore, it is advantageous in terms of cost if the trench width of the dielectric isolation structure is narrow. However, as a result, the trench shape has a ratio of depth to width, that is, depth / width has a high aspect ratio, and the trench opening is more likely to be blocked first when filling the oxide film. There arises a problem that voids are easily caught in the trench. Overcoming this challenge is also important.
As the silicon oxide film filled in the trench, a TEOS (tetraethylorthosilicate) oxide film formed from an organic material having a higher coverage than a CVD oxide film using a silane material is generally preferably used. . Among these, an LP (Low Pressure) -TEOS oxide film, which is difficult to form voids and has particularly excellent coverage, is particularly preferable for filling a trench having a high aspect ratio. The LP-TEOS oxide film is a silicon oxide film formed by a reaction between an organic TEOS gas and an oxygen gas by a low pressure CVD method, and has a particularly excellent step coverage as described above. However, post-annealing is required to sufficiently remove carbon C and hydrogen H atoms remaining in the film in order to enhance the insulation and improve the film quality.

一方、よく知られたＳＴＩ（Ｓｈａｌｌｏｗ Ｔｒｅｎｃｈ Ｉｓｏｌａｔｉｏｎ）分離構造において、シリコン基板に設けられたトレンチにＴＥＯＳ酸化膜を埋め込む場合、その後の高温熱処理で体積が収縮することにより、トレンチ内に熱酸化膜を介して埋め込まれたＴＥＯＳ酸化膜がトレンチ内側面のシリコンから剥がれ、前記内側面に隙間が生じることがある。このような隙間が生じると、この隙間に配線材などが入り込み、ショート不良を起こす問題があることが知られている（特許文献２―課題）。
さらに、ＳＯＩ構造の半導体装置において、深いトレンチに酸化物系の充填材を充填して、絶縁耐圧を低下させることなく結晶欠陥の発生を防止するために、支持基板に酸化膜を介して貼り付けられたシリコン層にマスクパターンの形成後に、異方性エッチングを行い、前記酸化膜に至る深いトレンチを形成し、このトレンチに薄い熱酸化膜を介してＴＥＯＳ酸化膜を埋め込む半導体装置の製造方法の発明も知られている（特許文献３−要約）。
特開平６―１５１５７６号公報 特開平１０−２８９９４６号公報 特開平８−２３０２７号公報 On the other hand, in a well-known STI (Shallow Trench Isolation) isolation structure, when a TEOS oxide film is embedded in a trench provided in a silicon substrate, the volume is shrunk by a subsequent high-temperature heat treatment, so that a thermal oxide film is formed in the trench. The TEOS oxide film buried through the trench may peel off from the silicon on the inner surface of the trench, and a gap may be formed on the inner surface. When such a gap occurs, it is known that a wiring material or the like enters the gap and causes a short-circuit defect (Patent Document 2-Problem).
Furthermore, in an SOI structure semiconductor device, a deep trench is filled with an oxide-based filler, and is attached to a support substrate via an oxide film in order to prevent the occurrence of crystal defects without lowering the withstand voltage. In the method of manufacturing a semiconductor device, after forming a mask pattern in the silicon layer, anisotropic etching is performed to form a deep trench reaching the oxide film, and a TEOS oxide film is embedded in the trench through a thin thermal oxide film. The invention is also known (Patent Document 3-Abstract).
JP-A-6-151576 Japanese Patent Laid-Open No. 10-289946 JP-A-8-23027

しかしながら、ＬＰ−ＴＥＯＳ酸化膜は、前述のように、膜中に残存する炭素Ｃと水素Ｈ原子を除去するためにポストアニールを行うと、炭素Ｃと水素Ｈが抜けて膜の収縮を起こすという性質があり、この収縮により、トレンチ内部に埋め込まれたＬＰ−ＴＥＯＳ酸化膜の中心部にクラックが発生し、空洞ができるという不具合が見られることがある。図２はトレンチ中心部に発生したクラックを示す半導体基板の断面図である。このようなクラックが発生すれば、予定した誘電体分離性能は発揮されず、半導体装置の品質が低下し、良品率が悪くなる。また、誘電体分離性能への直接的な影響が小さい場合でも、後工程における洗浄工程などにおいて、前記空洞内部に薬液が浸入し、またその薬液は残存し易いので、汚染され、半導体特性の劣化、良品率低下などを引き起こす原因となることがあった。   However, as described above, when the LP-TEOS oxide film is subjected to post-annealing in order to remove carbon C and hydrogen H atoms remaining in the film, the carbon C and hydrogen H are released and the film shrinks. Due to this contraction, there is a case where a crack is generated in the central portion of the LP-TEOS oxide film embedded in the trench and a cavity is formed. FIG. 2 is a cross-sectional view of a semiconductor substrate showing a crack generated in the center of the trench. If such a crack occurs, the planned dielectric separation performance is not exhibited, the quality of the semiconductor device is lowered, and the yield rate is deteriorated. In addition, even when the direct influence on the dielectric separation performance is small, the chemical solution penetrates into the cavity in the subsequent cleaning process and the like, and the chemical solution is likely to remain, so it is contaminated and deteriorates the semiconductor characteristics. In some cases, it may cause a decrease in the yield rate.

本発明は、以上述べた点に鑑みてなされたものであり、ＳＯＩ構造の半導体基板の半導体島領域内に機能領域を形成した後に、高アスペクト比のトレンチをエッチング形成し、ＬＰ−ＴＥＯＳ酸化膜を充填し、アニール処理を施して誘電体分離構造を形成する場合に、前記半導体島領域の電気特性に悪影響を及ぼさず且つ前記ＬＰ−ＴＥＯＳ膜にクラックを生じさせない半導体装置の製造方法の提供を目的とするものである。   The present invention has been made in view of the above points, and after forming a functional region in a semiconductor island region of a semiconductor substrate having an SOI structure, a high aspect ratio trench is formed by etching to form an LP-TEOS oxide film. A semiconductor device manufacturing method that does not adversely affect the electrical characteristics of the semiconductor island region and does not cause cracks in the LP-TEOS film when the dielectric isolation structure is formed by filling the substrate and annealing. It is the purpose.

特許請求の範囲の請求項１記載の本発明によれば、半導体支持基板上に絶縁膜を介して半導体層を備えるＳＯＩ構造の半導体基板の前記半導体層内に機能領域を形成した後に、前記半導体層の表面から前記絶縁膜に達するトレンチを形成し、該トレンチに減圧ＣＶＤ法により形成されるＴＥＯＳ酸化膜を充填した後、熱処理炉で８５０℃乃至９５０℃の範囲のいずれかの温度によるポストアニール処理を施す際に、炉入れおよび炉出し温度を６５０℃乃至８００℃の範囲のいずれかの温度とし、前記炉入れおよび炉出し温度と前記ポストアニール温度との間の昇温速度および降温速度を３℃／分乃至４℃／分の範囲のいずれかの速度とし、前記ＴＥＯＳ酸化膜充填後のＳＯＩ構造の半導体基板を炉外から炉内へ引き入れる炉入れ速度およびその逆の場合の炉出し速度をそれぞれ５０ｍｍ／分以下とする半導体装置の製造方法とすることにより、達成される。 According to the first aspect of the present invention, after the functional region is formed in the semiconductor layer of the semiconductor substrate having the SOI structure including the semiconductor layer on the semiconductor supporting substrate via the insulating film , the semiconductor A trench reaching the insulating film from the surface of the layer is formed, and the trench is filled with a TEOS oxide film formed by a low pressure CVD method, and then post-annealed at a temperature in the range of 850 ° C. to 950 ° C. in a heat treatment furnace When performing the treatment, the furnace charging / unloading temperature is set to a temperature in the range of 650 ° C. to 800 ° C., and the heating rate and the cooling rate between the furnace charging / unloading temperature and the post-annealing temperature are set. 3 ° C. / min to 4 ° C. / either speed minute range, the furnace insertion speed and its drawing in the semiconductor substrate of the SOI structure after the TEOS oxide film filled from the outside of the furnace into the furnace With the method of manufacturing a semiconductor device which opposite the furnace out speed when the respective 50 mm / min or less, is achieved.

特許請求の範囲の請求項２記載の本発明によれば、前記炉入れおよび炉出し温度をそれぞれ約７００℃とする特許請求の範囲の請求項１記載の半導体装置の製造方法とすることがより好ましい。
特許請求の範囲の請求項３記載の本発明によれば、前記昇温速度および降温速度をそれぞれ約３．５℃／分とする特許請求の範囲の請求項１または２に記載の半導体装置の製造方法とすることが望ましい。

According to claim 2 the present invention described in the claims, more be a process according to claim 1, the semiconductor device of the appended claims to about 700 ° C. the furnace insertion and furnace out temperature, respectively preferable.
According to the claims claim 3 the present invention as claimed in claims, the semiconductor device according to claim 1 or 2 claims to the heating rate and are about 3.5 ° C. / min and cooling rate It is desirable to use a manufacturing method.

本発明によれば、ＳＯＩ構造の半導体基板の半導体島領域内に機能領域を形成した後に、高アスペクト比のトレンチを形成し、ＬＰ−ＴＥＯＳ酸化膜を充填し、アニール処理を施して誘電体分離構造を形成する場合に、前記半導体島領域の電気特性に悪影響を及ぼさず且つＬＰ−ＴＥＯＳ膜にクラックを生じさせない半導体装置の製造方法を提供することができる。   According to the present invention, after forming a functional region in a semiconductor island region of a semiconductor substrate having an SOI structure, a trench with a high aspect ratio is formed, filled with an LP-TEOS oxide film, and subjected to an annealing process to separate a dielectric. When the structure is formed, it is possible to provide a method for manufacturing a semiconductor device that does not adversely affect the electrical characteristics of the semiconductor island region and does not cause cracks in the LP-TEOS film.

図１は本発明の半導体装置の製造方法にかかる製造工程を示す半導体基板の要部断面図である。本発明は、その要旨を超えないかぎり、以下説明する実施例の記載に限定されるものではない。   FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a manufacturing process according to a method for manufacturing a semiconductor device of the present invention. The present invention is not limited to the description of the examples described below unless it exceeds the gist.

６〜８インチ径のシリコン半導体支持基体１上に絶縁膜２を介してｎ型シリコン半導体層３を貼り付けたＳＯＩシリコン半導体基板を用意する。前記ｎ型シリコン半導体層３を所要の適切な厚さに加工した後、図示しない高耐圧スイッチングデバイスやその制御回路デバイスなどを前記シリコン半導体層３のそれぞれ相互に異なる領域内に形成した後、さらに、その表面にシリコン酸化膜４を形成する。シリコン酸化膜４にフォトリソグラフィ技術を用いて、前記デバイス領域間に生じ易い電気的な相互干渉を防止するための誘電体分離構造を形成するために用いられるトレンチ用のパターン形成を行う（図１（ａ））。開口後フォトレジストおよび／またはシリコン酸化膜をマスクとして、公知のＲＩＥ（Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ）技術により異方性エッチングを行い絶縁膜２に達するトレンチ５を形成する（図１（ｂ））。ＲＩＥに用いられる材料としては、ＨＢｒ、ＮＦ３ガスなどが好ましい。 An SOI silicon semiconductor substrate is prepared in which an n-type silicon semiconductor layer 3 is bonded to a 6-8 inch diameter silicon semiconductor support base 1 with an insulating film 2 interposed therebetween. After processing the n-type silicon semiconductor layer 3 to a required appropriate thickness, a high voltage switching device (not shown) and its control circuit device are formed in different regions of the silicon semiconductor layer 3, and Then, a silicon oxide film 4 is formed on the surface. A pattern for a trench used for forming a dielectric isolation structure for preventing electrical mutual interference that easily occurs between the device regions is formed on the silicon oxide film 4 by using a photolithography technique (FIG. 1). (A)). After the opening, a trench 5 reaching the insulating film 2 is formed by anisotropic etching by a known RIE (Reactive Ion Etching) technique using a photoresist and / or a silicon oxide film as a mask (FIG. 1B). As a material used for RIE, HBr, NF 3 gas and the like are preferable.

次に、図示しない減圧ＣＶＤ装置中、６００℃〜７５０℃の温度の酸素雰囲気で、有機系のＴＥＯＳ（テトラエチルオルソシリケイト）ソースガスの分解および化学反応により形成されるＴＥＯＳ酸化膜６を、前記トレンチエッチングされたＳＯＩシリコン基板上に、前記トレンチ５を充分に埋めるに足りる厚さ以上に堆積させる（図１（ｃ））。堆積後、ＴＥＯＳ酸化膜６から残存する炭素Ｃと水素Ｈを除去して緻密で絶縁性の高い膜とするために、さらに、別の熱処理炉で酸素雰囲気で、８５０℃、３０分間の条件でポストアニール処理を行う。ポストアニール温度は８５０℃〜９５０℃の範囲から必要に応じて選択することができる。アニール時間は少なくとも３０分程度が必要である。アニール温度が９５０℃を超えると、既に、ＳＯＩ半導体基板上の半導体層３に形成されている前記デバイス領域（図示せず）に影響を及ぼす。一方、アニール温度が８５０℃を下回ると、膜中の残存炭素Ｃや水素Ｈが充分に抜けない傾向が強くなり、膜質が劣化し、絶縁性も次第に悪くなるので好ましくない。   Next, a TEOS oxide film 6 formed by decomposition and chemical reaction of an organic TEOS (tetraethylorthosilicate) source gas in an oxygen atmosphere at a temperature of 600 ° C. to 750 ° C. in a low pressure CVD apparatus (not shown) is formed in the trench. On the etched SOI silicon substrate, the trench 5 is deposited to a thickness more than enough to fill the trench 5 (FIG. 1C). After the deposition, in order to remove the carbon C and hydrogen H remaining from the TEOS oxide film 6 to obtain a dense and highly insulating film, it is further subjected to another heat treatment furnace in an oxygen atmosphere at 850 ° C. for 30 minutes. Post-annealing is performed. The post-annealing temperature can be selected as necessary from the range of 850 ° C. to 950 ° C. The annealing time needs to be at least about 30 minutes. When the annealing temperature exceeds 950 ° C., the device region (not shown) already formed in the semiconductor layer 3 on the SOI semiconductor substrate is affected. On the other hand, if the annealing temperature is lower than 850 ° C., there is a strong tendency that residual carbon C and hydrogen H in the film cannot be sufficiently removed, film quality is deteriorated, and insulation properties are gradually deteriorated, which is not preferable.

ただし、本発明では特に８５０℃〜９５０℃の前記ポストアニール温度によるアニール処理の前後の炉入れ温度、炉出し温度と炉入れ温度から前記アニール温度への昇温速度および前記アニール温度から前記炉出し温度への降温速度を規定することが充填したＴＥＯＳ酸化膜６のクラック７およびクラック７に誘発されるシリコンクラック８（図２）の発生防止にとって重要であることを見つけてなされたものである。それによると、炉入れ温度と炉出し温度は６５０℃〜８００℃の範囲のいずれかの温度から選ばれるのが好ましく、特には７００℃近辺の温度が好ましい。且つ炉入れ温度から前記アニール温度間の昇温速度および前記アニール温度処理の終了後炉出し温度までの降温速度はそれぞれ３．０℃／分〜４．０℃／分から選択することができるが、３．５℃／分とすることが最も好ましいことが分かった。ただし、前述の炉入れ温度と炉出し温度、または前記昇温速度と降温速度をそれぞれ同一とする必要性は特にはない。   However, in the present invention, in particular, the furnace temperature before and after the annealing treatment at the post-annealing temperature of 850 ° C. to 950 ° C., the furnace temperature, the temperature rising rate from the furnace temperature to the annealing temperature, and the furnace temperature from the annealing temperature. The inventors have found that it is important to define the rate of temperature decrease to the temperature in order to prevent generation of cracks 7 in the filled TEOS oxide film 6 and silicon cracks 8 induced in the cracks 7 (FIG. 2). According to this, the furnace entry temperature and the furnace exit temperature are preferably selected from any temperature within the range of 650 ° C. to 800 ° C., and particularly preferably around 700 ° C. Further, the rate of temperature increase from the furnace temperature to the annealing temperature and the temperature decreasing rate from the annealing temperature treatment to the furnace exit temperature can be selected from 3.0 ° C./min to 4.0 ° C./min, respectively. It has been found that a rate of 3.5 ° C./min is most preferable. However, there is no particular need to make the above-described furnace charging temperature and furnace discharge temperature, or the temperature increase rate and temperature decrease rate the same.

前記炉入れ温度と炉出し温度の６５０℃〜８００℃について説明すると、下限の６５０℃以下とすることは前記クラック７、８を防止することに関しては好ましいものの、６５０℃以下の温度とすると、アニール温度との差が次第に大きくなり過ぎ、昇温と降温に時間が掛かるようになり、生産効率的に好ましくないということである。上限の８００℃以上の場合、通常の生産的な炉入れ速度、炉出し速度（５０ｍｍ／分）でＳＯＩ半導体基板を炉に出し入れすると、前記クラック７、８が入る惧れが大きいということである。前記昇温速度と降温速度については、下限の３．０℃／分以下とすることはクラック７、８の防止という観点からは良好であるが、生産効率的に実際的でないということであり、上限の４．０℃／分以上ではクラック７、８の惧れが大きくなることから、前述のように温度範囲、速度範囲などが決められた。   The furnace temperature and the furnace temperature of 650 ° C. to 800 ° C. will be described. The lower limit of 650 ° C. or lower is preferable for preventing the cracks 7 and 8, but the temperature of 650 ° C. or lower is annealed. This means that the difference from the temperature becomes gradually larger, and it takes time to raise and lower the temperature, which is not preferable in terms of production efficiency. When the upper limit is 800 ° C. or higher, there is a high possibility that the cracks 7 and 8 are generated when the SOI semiconductor substrate is taken in and out at a normal productive furnace charging speed and furnace discharging speed (50 mm / min). . Regarding the temperature increase rate and temperature decrease rate, the lower limit of 3.0 ° C./min or less is good from the viewpoint of preventing cracks 7 and 8, but it is impractical in terms of production efficiency. At the upper limit of 4.0 ° C./min or more, the fear of cracks 7 and 8 increases, so the temperature range, speed range, etc. were determined as described above.

ＴＥＯＳ酸化膜６充填後のＳＯＩ半導体基板を炉外からアニール炉内へ引き入れる炉入れ速度およびその逆の場合の炉出し速度をそれぞれ５０ｍｍ／分以下とする。この炉入れ速度および炉出し速度は、本発明にかかる温度範囲内の炉入れ温度および炉出し温度であっても、それらの温度からの急冷、急熱は好ましくないということから、生産効率的な観点をも考慮に入れて決められた５０ｍｍ／分を上限値とするものであり、これ以下であれば、クラック防止の観点からは問題ないので、下限値は特に設定していない。従って、生産効率的観点からは５０ｍｍ／分に近い速度が好ましい。
これ以降の製造工程は、ＳＯＩ半導体基板の表面に形成されたＴＥＯＳ酸化膜６とマスク酸化膜２をエッチバックまたは研摩により除去すると、ＴＥＯＳ酸化膜による誘電体分離構造により半導体島領域に分離され、該半導体島領域それぞれ制御回路デバイスや高耐圧デバイスなどが形成されたＳＯＩ半導体基板を備えたパワーＩＣなどの半導体装置が形成される。 The furnace loading speed at which the SOI semiconductor substrate after filling the TEOS oxide film 6 is drawn into the annealing furnace from the outside of the furnace and the furnace discharge speed in the opposite case are each set to 50 mm / min or less. Even if the furnace charging speed and the furnace discharging speed are within the temperature range according to the present invention, rapid cooling and rapid heating from those temperatures are not preferable. The upper limit is set to 50 mm / min determined in consideration of the viewpoint, and if it is less than this, there is no problem from the viewpoint of crack prevention, so the lower limit is not particularly set. Therefore, a speed close to 50 mm / min is preferable from the viewpoint of production efficiency.
In the subsequent manufacturing process, when the TEOS oxide film 6 and the mask oxide film 2 formed on the surface of the SOI semiconductor substrate are removed by etching back or polishing, the TEOS oxide film is separated into semiconductor island regions by a dielectric isolation structure, A semiconductor device such as a power IC provided with an SOI semiconductor substrate on which each of the semiconductor island regions is formed with a control circuit device, a high breakdown voltage device and the like is formed.

本発明の半導体装置の製造方法にかかる製造工程を示す半導体基板の要部断面図である。It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process concerning the manufacturing method of the semiconductor device of this invention. 従来の半導体装置の製造方法にかかるトレンチ内のＬＰ−ＴＥＯＳ酸化膜にクラックが発生したことを示す半導体基板の要部断面図である。It is principal part sectional drawing of the semiconductor substrate which shows that the crack generate | occur | produced in the LP-TEOS oxide film in the trench concerning the manufacturing method of the conventional semiconductor device. 従来の誘電体分離構造を有するＳＯＩ半導体基板の製造工程を示す半導体基板の要部断面図である（その１）。It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of the SOI semiconductor substrate which has the conventional dielectric isolation structure (the 1). 従来の誘電体分離構造を有するＳＯＩ半導体基板の製造工程を示す半導体基板の要部断面図である（その２）。It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of the SOI semiconductor substrate which has the conventional dielectric isolation structure (the 2).

符号の説明Explanation of symbols

１ 半導体支持基板
２ 絶縁膜
３ 半導体層
４ マスク酸化膜
５ トレンチ酸化膜
７ クラック
８ シリコンクラック。 DESCRIPTION OF SYMBOLS 1 Semiconductor support substrate 2 Insulating film 3 Semiconductor layer 4 Mask oxide film 5 Trench oxide film 7 Crack 8 Silicon crack.

Claims (3)

半導体支持基板上に絶縁膜を介して半導体層を備えるＳＯＩ構造の半導体基板の前記半導体層内に機能領域を形成した後に、前記半導体層の表面から前記絶縁膜に達するトレンチを形成し、該トレンチに減圧ＣＶＤ法により形成されるＴＥＯＳ酸化膜を充填した後、熱処理炉で８５０℃乃至９５０℃の範囲のいずれかの温度によるポストアニール処理を施す際に、炉入れおよび炉出し温度を６５０℃乃至８００℃の範囲のいずれかの温度とし、前記炉入れおよび炉出し温度と前記ポストアニール温度との間の昇温速度および降温速度を３℃／分乃至４℃／分の範囲のいずれかの速度とし、前記ＴＥＯＳ酸化膜充填後のＳＯＩ構造の半導体基板を炉外から炉内へ引き入れる炉入れ速度およびその逆の場合の炉出し速度をそれぞれ５０ｍｍ／分以下とすることを特徴とする半導体装置の製造方法。 A functional region is formed in the semiconductor layer of a semiconductor substrate having an SOI structure including a semiconductor layer via an insulating film on the semiconductor support substrate, and then a trench reaching the insulating film from the surface of the semiconductor layer is formed. After filling a TEOS oxide film formed by a low pressure CVD method to a post-annealing treatment at a temperature in the range of 850 ° C. to 950 ° C. in a heat treatment furnace, the furnace insertion and furnace discharge temperatures are set to 650 ° C. to A temperature in the range of 800 ° C. is set, and a temperature rising rate and a temperature decreasing rate between the furnace charging / unloading temperature and the post-annealing temperature are in the range of 3 ° C./min to 4 ° C./min. and then, the TEOS oxide film draws from the furnace outside the semiconductor substrate of the SOI structure after filling into the furnace furnace insertion speed and each 50 mm / min or less a furnace out speed when the reverse The method of manufacturing a semiconductor device which is characterized in that a. 前記炉入れおよび炉出し温度をそれぞれ約７００℃とすることを特徴とする請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the furnace charging temperature and the furnace discharging temperature are about 700 [deg.] C., respectively. 前記昇温速度および降温速度をそれぞれ約３．５℃／分とすることを特徴とする請求項１または２に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that from about 3.5 ° C. / min the heating rate and cooling rate, respectively.
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