JP4895483B2

JP4895483B2 - Semiconductor device

Info

Publication number: JP4895483B2
Application number: JP2004179328A
Authority: JP
Inventors: 薫宮越; 信幸佐野
Original assignee: New Japan Radio Co Ltd
Current assignee: New Japan Radio Co Ltd
Priority date: 2004-06-17
Filing date: 2004-06-17
Publication date: 2012-03-14
Anticipated expiration: 2024-06-17
Also published as: JP2006005123A

Description

本発明は半導体基板上の絶縁領域あるいは半絶縁領域に離間して複数の半導体素子が形成された半導体装置に関し、特に隣接する２つの半導体素子に印加される電位が異なる構成となる半導体装置に関する。 The present invention relates to a semiconductor device in which a plurality of semiconductor elements are formed apart from an insulating region or semi-insulating region on a semiconductor substrate, and more particularly to a semiconductor device having a configuration in which potentials applied to two adjacent semiconductor elements are different.

半導体集積回路の製造工程において、素子分離は必須技術である。例えば、シリコン半導体の素子分離として、ＬＯＣＯＳ酸化膜を用いたり、イオン注入法により素子分離領域を形成するのが一般的である。これに対し、化合物半導体では、安定な酸化膜を形成することが難しいため、半絶縁性の半導体基板を素子分離領域としたり、不純物イオンを注入して高抵抗の素子分離領域を形成するのが一般的である（例えば、特許文献１）。 In the manufacturing process of a semiconductor integrated circuit, element isolation is an essential technique. For example, a LOCOS oxide film is generally used for element isolation of a silicon semiconductor, or an element isolation region is formed by ion implantation. On the other hand, since it is difficult to form a stable oxide film in a compound semiconductor, a semi-insulating semiconductor substrate is used as an element isolation region, or impurity ions are implanted to form a high resistance element isolation region. It is common (for example, patent document 1).

例えば、半絶縁性の半導体基板を素子分離領域とする場合、半導体素子形成予定領域に不純物イオンを注入して導電性の半導体領域を形成し、この半導体領域に抵抗素子や電界効果トランジスタ等の半導体素子を形成する。その結果、半導体素子間の半絶縁性の半導体基板が素子分離領域となる。また、高抵抗の素子分離領域を形成する場合は、導電性の半導体基板上の半導体素子形成予定領域を除く素子分離領域形成予定領域に、不純物イオンを注入して高抵抗の素子分離領域形成することになる。 For example, when a semi-insulating semiconductor substrate is used as an element isolation region, a conductive semiconductor region is formed by implanting impurity ions into a semiconductor element formation planned region, and a semiconductor such as a resistor element or a field effect transistor is formed in this semiconductor region. An element is formed. As a result, the semi-insulating semiconductor substrate between the semiconductor elements becomes the element isolation region. In the case of forming a high-resistance element isolation region, impurity ions are implanted into the element isolation region formation scheduled region excluding the semiconductor element formation planned region on the conductive semiconductor substrate to form the high resistance element isolation region. It will be.

ところで、隣接する半導体素子間に印加される電位は必ずしも一致するものではなく、半導体素子間に電位差が生じる場合がある。この半導体素子間の電位差により、半導体素子間の半絶縁性領域あるいは絶縁領域からなる素子分離領域に空乏層が広がる。隣接する半導体素子間の間隔が狭いと、空乏層は素子分離領域を越えて、隣接する半導体素子を構成する半導体領域まで広がり、この半導体領域を空乏化し、半導体素子の電気的特性が変動してしまう。このため、電位差の影響を受けないだけ、即ち、空乏層が広がる間隔より半導体素子間の間隔を広くしなければならず、集積度を上げる妨げとなっていた。特に、半導体素子に高電圧や大信号が入力する場合には、素子間の間隔が非常に大きくなるという問題があった。
特願２００２−３２９７３０号公報 By the way, the potentials applied between adjacent semiconductor elements do not necessarily coincide with each other, and a potential difference may occur between the semiconductor elements. Due to the potential difference between the semiconductor elements, a depletion layer spreads in an element isolation region composed of a semi-insulating region or an insulating region between the semiconductor elements. If the interval between adjacent semiconductor elements is narrow, the depletion layer extends beyond the element isolation region to the semiconductor area that constitutes the adjacent semiconductor element, and this semiconductor region is depleted and the electrical characteristics of the semiconductor element change. End up. For this reason, it is not affected by the potential difference, that is, the interval between the semiconductor elements must be wider than the interval at which the depletion layer spreads, which hinders the increase in the degree of integration. In particular, when a high voltage or a large signal is input to the semiconductor element, there is a problem that the distance between the elements becomes very large.
Japanese Patent Application No. 2002-329730

このように、隣接する半導体素子間に電位差が生じる構造の半導体装置において、集積度を上げるために隣接する半導体素子間の間隔を狭くする場合、隣接する半導体素子を構成する半導体領域に空乏層が広がり、半導体素子が設計通りに動作しないという問題があった。そのため、空乏層の影響を受けないだけ、半導体素子間の間隔を広くする必要があるが、半導体素子に高電圧や大信号が入力する場合には、半導体素子間に広がる空乏層の影響を受けないだけ半導体素子間の間隔を広くすることは、集積度を上げる妨げになるという問題があった。本発明はこれらの問題点を解消し、隣接する半導体素子間に広がる空乏層の広がりを抑制し、集積度を上げることができる半導体装置を提供することを目的とする。 Thus, in a semiconductor device having a structure in which a potential difference is generated between adjacent semiconductor elements, in order to increase the degree of integration, when the interval between adjacent semiconductor elements is narrowed, a depletion layer is formed in a semiconductor region constituting the adjacent semiconductor elements. There is a problem that the semiconductor device does not operate as designed. Therefore, it is necessary to widen the distance between the semiconductor elements so as not to be affected by the depletion layer. However, when a high voltage or a large signal is input to the semiconductor element, it is affected by the depletion layer spreading between the semiconductor elements. Increasing the distance between the semiconductor elements as much as possible has a problem of hindering the integration. An object of the present invention is to provide a semiconductor device capable of solving these problems, suppressing the spread of a depletion layer extending between adjacent semiconductor elements, and increasing the degree of integration.

上記目的を達成するため、請求項１に係る発明は、半導体基板上の絶縁領域あるいは半絶縁領域に、一導電型の半導体領域で形成された抵抗素子が隣接して配置された半導体装置において、一の前記抵抗素子と、隣接する別の前記抵抗素子との間の前記絶縁領域あるいは半絶縁領域に、一導電型の半導体領域からなり、フローティグ状態のガード層を備え、隣接する前記抵抗素子間に電位差が生じ、前記抵抗素子の一方から空乏層が広がるとき、前記ガード層で前記空乏層の広がりを抑えることを特徴とするものである。In order to achieve the above object, the invention according to claim 1 is a semiconductor device in which a resistance element formed of a semiconductor region of one conductivity type is disposed adjacent to an insulating region or a semi-insulating region on a semiconductor substrate. The insulating element or the semi-insulating area between one of the resistive elements and another adjacent resistive element is made of a semiconductor region of one conductivity type and includes a guard layer in a floating state, and the adjacent resistive element When a potential difference occurs between them and a depletion layer spreads from one of the resistance elements, the guard layer suppresses the spread of the depletion layer.

本発明の半導体装置は、隣接する半導体素子間に導電性の半導体領域からなるガード層を形成することで、半導体素子間に空乏層が広がったとしても、ガード層に達したところでその広がりを抑えることができるように構成している。これにより半導体素子間の間隔を狭くすることができ、集積度が高く、回路レイアウトの自由度の大きい半導体装置を実現することができる。 In the semiconductor device of the present invention, even if a depletion layer spreads between semiconductor elements by forming a guard layer made of a conductive semiconductor region between adjacent semiconductor elements, the spread is suppressed when the guard layer is reached. It is configured to be able to. As a result, the distance between the semiconductor elements can be narrowed, and a semiconductor device having a high degree of integration and a high degree of freedom in circuit layout can be realized.

本発明のガード層は、通常の半導体素子を構成する半導体領域と同時に形成することができ、簡便に製造することができる。 The guard layer of the present invention can be formed simultaneously with a semiconductor region constituting a normal semiconductor element, and can be easily manufactured.

以下、本発明について説明する。まず、２つの抵抗素子が隣接する半導体装置を例にとり、説明する。図３は隣接する２つの抵抗素子を示し、図３（ａ）はガード層を備えていない従来例の抵抗素子の構造を、図３（ｂ）はガード層を備えた本発明の抵抗素子の構造をそれぞれ示している。図４（ａ）は、図３（ａ）に示す従来例の抵抗素子における抵抗印加電圧（Vｓｉｄｅ）に対する抵抗変化率（Ｒ／Ｒ₀、Ｒは抵抗素子２の抵抗値、Ｒ₀は印加電圧Vｓｉｄｅ=０のときの抵抗素子２の抵抗値）を、図４（ｂ）は、図３（ｂ）に示す本発明の抵抗素子における抵抗印加電圧（Vｓｉｄｅ）に対する抵抗変化率を示す図である。図４では、抵抗素子２と抵抗素子３の間隔（ｄ）を１０、２０、３０、５０μｍと変化させ、抵抗素子３の電極間の抵抗印加電圧（Vｓｉｄｅ）を変化させたときの抵抗変化率（Ｒ／Ｒ₀）の変化を示している。抵抗素子２の電極間の抵抗印加電圧は１Ｖ、抵抗素子幅（Ｗ）は１．５μｍ、抵抗素子長さ（Ｌ）は３５μｍ、抵抗素子３の抵抗素子幅（Ｗ）は５μｍ、抵抗素子長さ（Ｌ）は１９．５μｍ、抵抗値（Ｒ）は１５ｋΩである。 The present invention will be described below. First, a semiconductor device in which two resistance elements are adjacent will be described as an example. FIG. 3 shows two adjacent resistance elements, FIG. 3 (a) shows the structure of a conventional resistance element not provided with a guard layer, and FIG. 3 (b) shows the resistance element of the present invention provided with a guard layer. Each structure is shown. 4 (a) is the rate of change in resistance to the resistance applied voltage in the resistance element of the conventional example shown in FIG. 3 (a) (Vside) ( R / R 0, R is the resistance value of the resistance element 2, R ₀ is the applied voltage the resistance value of the resistance element 2) when Vside = 0, FIG. 4 (b) is a diagram showing the resistance change ratio for the resistance applied voltage (Vside) in the resistance element of the present invention shown in FIG. 3 (b) . In FIG. 4 , the rate of change in resistance when the distance (d) between the resistive element 2 and the resistive element 3 is changed to 10, 20, 30, 50 μm, and the resistance applied voltage (Vside) between the electrodes of the resistive element 3 is changed. A change in (R / R ₀ ) is shown. The resistance applied voltage between the electrodes of the resistive element 2 is 1 V, the resistive element width (W) is 1.5 μm, the resistive element length (L) is 35 μm, the resistive element width (W) of the resistive element 3 is 5 μm, and the resistive element length The length (L) is 19.5 μm, and the resistance value (R) is 15 kΩ.

図４（ａ）に示す従来例の抵抗素子では、抵抗印加電圧が負側に大きくなる程、また抵抗素子間の間隔（ｄ）が狭い程、抵抗変化率が大きくなることを示している。これは、負電圧印加時に抵抗素子３側から半導体基板内に空乏層が広がり、抵抗素子２を構成する半導体領域が狭くなり、つまり抵抗素子２の抵抗素子幅（Ｗ）が狭くなり、抵抗素子２の抵抗値Ｒが高くなったものと考えられる。このような現象は、半導体領域の不純物濃度および抵抗素子の厚さと幅に関係し、低濃度で、浅く、また狭いほどその影響が大きくなることがわかっている。これに対し、図４（ｂ）に示す本発明の抵抗素子では、抵抗変化率の変動が小さく、本発明のガード層４が、抵抗変化率の変動を効果的に抑制していることがわかる。 4 by the resistance element in the conventional example shown in (a) is, the more resistance the applied voltage increases in the negative direction, also as the spacing between the resistive element (d) is narrow, the resistance change rate is shown that increase. This is because when a negative voltage is applied, a depletion layer spreads in the semiconductor substrate from the resistance element 3 side, the semiconductor region constituting the resistance element 2 becomes narrow, that is, the resistance element width (W) of the resistance element 2 becomes narrow, and the resistance element It is considered that the resistance value R of 2 was increased. Such a phenomenon is related to the impurity concentration of the semiconductor region and the thickness and width of the resistance element, and it has been found that the influence becomes greater as the concentration is lower, the depth is shallower, and the width is smaller. In contrast, in the resistance element of the present invention shown in FIG. 4 (b), fluctuation of the resistance change rate is small, the guard layer 4 of the present invention, it can be seen that the variation of the resistance change rate is effectively suppressed .

同様に図５は、本発明のガード層４の効果を説明するための図であり、抵抗素子２及び抵抗素子３間の間隔（ｄ）と抵抗変化率（Ｒ／Ｒ₀）の関係で示している。抵抗素子２の抵抗印加電圧は１Ｖ、抵抗素子幅（Ｗ）は１．５μｍ、抵抗素子長さ（Ｌ）は３５μｍ、抵抗素子３の抵抗印加電圧（Ｖｓｉｄｅ）は−２０Ｖ、抵抗素子３の抵抗素子幅（Ｗ）は５μｍ、抵抗素子長さ（Ｌ）は１９．５μｍである。 Similarly, FIG. 5 is a diagram for explaining the effect of the guard layer 4 of the present invention, and shows the relationship between the resistance element 2 and the interval (d) between the resistance elements 3 and the resistance change rate (R / R ₀ ). ing. The resistance application voltage of the resistance element 2 is 1 V, the resistance element width (W) is 1.5 μm, the resistance element length (L) is 35 μm, the resistance application voltage (Vside) of the resistance element 3 is −20 V, and the resistance of the resistance element 3 The element width (W) is 5 μm, and the resistance element length (L) is 19.5 μm.

図５に示すようにガード層４を挿入すると、抵抗変化率（Ｒ／Ｒ₀）が小さくなることがわかる。図５において、ガード層４のない従来例の抵抗変化率（Ｒ／Ｒ₀）を■印、ガード層４を備えた本発明の抵抗変化率（Ｒ／Ｒ₀）を△印で示している。抵抗素子２及び抵抗素子３間の間隔（ｄ）が狭い程、抵抗変化率（Ｒ／Ｒ₀）の変化を小さくする効果が大きいことがわかる。これは、ガード層４が空乏層の広がりを抑制し、抵抗素子２に与える電界の影響を緩和するためと考えられる。 As can be seen from FIG. 5 , when the guard layer 4 is inserted, the rate of change in resistance (R / R ₀ ) decreases. In FIG. 5 , the resistance change rate (R / R ₀ ) of the conventional example without the guard layer 4 is indicated by ■, and the resistance change rate (R / R ₀ ) of the present invention having the guard layer 4 is indicated by Δ. . It can be seen that the smaller the distance (d) between the resistance element 2 and the resistance element 3, the greater the effect of reducing the change in the resistance change rate (R / R ₀ ). This is presumably because the guard layer 4 suppresses the spread of the depletion layer and alleviates the influence of the electric field applied to the resistance element 2.

ガード層４の深さは抵抗素子と同じかそれ以上深く形成するのが好ましい。ガード層４の幅、配置位置は、空乏層の影響がないように適宜設定すれば良い。The guard layer 4 is preferably formed to have a depth equal to or greater than that of the resistance element. What is necessary is just to set suitably the width | variety and arrangement position of the guard layer 4 so that the influence of a depletion layer may not exist.

次に、具体的な実施例として、抵抗素子と電界効果トランジスタを半絶縁性基板上に形成する半導体装置の製造工程において、２つの抵抗素子を隣接して形成する場合について説明する。図１（ａ）は本発明の第１の実施例の平面図であって、半絶縁性基板１上に電界効果トランジスタのチャネル層の形成と同時に、ｎ型の半導体領域を用いた抵抗素子２及び抵抗素子３と、その間に、ｎ型の半導体領域によりガード層４を形成したものである。図１（ｂ）は図１（ａ）のＸ−Ｘ’線での断面図であって、抵抗素子２、３及びガード層４を構成する半導体領域は、イオン注入法によって形成することができる。 Next, as a specific example, a case where two resistance elements are formed adjacent to each other in a manufacturing process of a semiconductor device in which a resistance element and a field effect transistor are formed on a semi-insulating substrate will be described. FIG. 1A is a plan view of a first embodiment of the present invention, in which a resistance element 2 using an n-type semiconductor region is formed simultaneously with the formation of a channel layer of a field effect transistor on a semi-insulating substrate 1. And a resistance element 3 and a guard layer 4 formed of an n-type semiconductor region therebetween. FIG. 1B is a cross-sectional view taken along line XX ′ in FIG. 1A, and the semiconductor regions constituting the resistance elements 2 and 3 and the guard layer 4 can be formed by an ion implantation method. .

このように隣接して形成された抵抗素子２、３の一方に負電圧が印加し、空乏層が広がった場合でも、空乏層の先端がガード層４に達すると、ガード層４は周囲の半絶縁領域より不純物濃度が高い半導体領域で形成されているため、ガード層４内で空乏層が広がる間隔が狭くなり、隣接する抵抗素子への影響を緩和することができる。 Even when a negative voltage is applied to one of the resistance elements 2 and 3 formed adjacent to each other and the depletion layer expands, when the leading end of the depletion layer reaches the guard layer 4, the guard layer 4 is surrounded by the surrounding half. Since it is formed of a semiconductor region having an impurity concentration higher than that of the insulating region, the interval at which the depletion layer extends in the guard layer 4 is narrowed, and the influence on the adjacent resistance element can be mitigated.

なお抵抗素子２及び抵抗素子３は、いずれか一方あるいは両方が、別の半導体装置を構成する半導体領域であっても同様である。即ち、抵抗素子を構成する半導体領域の代わりに、電界効果トランジスタのチャネル領域を構成する半導体領域であっても同様である。以下の実施例においても同様である。 Note that the resistance element 2 and the resistance element 3 are the same even if one or both of them are semiconductor regions constituting another semiconductor device. That is, the same applies to a semiconductor region constituting a channel region of a field effect transistor instead of a semiconductor region constituting a resistance element. The same applies to the following embodiments.

図２（ａ）は本発明の第２の実施例であって、半絶縁性基板１上に、エピタキシャル成長層を用いて抵抗素子を形成した例である。抵抗素子２、３間には、例えばボロンイオンを注入して絶縁化した絶縁領域５が形成されている。図２（ｂ）は図２（ａ）のＸ−Ｘ’線での断面図であって、ガード層４は抵抗素子２、３と同様にエピタキシャル成長層を用いて形成されている。 FIG. 2A shows a second embodiment of the present invention, in which a resistance element is formed on a semi-insulating substrate 1 using an epitaxial growth layer. Between the resistance elements 2 and 3, an insulating region 5 is formed which is insulated by implanting, for example, boron ions. FIG. 2B is a cross-sectional view taken along line XX ′ in FIG. 2A, and the guard layer 4 is formed using an epitaxial growth layer in the same manner as the resistance elements 2 and 3 .

本発明の第１の実施例の説明図で、（ａ）は平面図、（ｂ）は図１（ａ）のＸ−Ｘ’線での断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is explanatory drawing of the 1st Example of this invention, (a) is a top view, (b) is sectional drawing in the X-X 'line | wire of Fig.1 (a). 本発明の第２の実施例の説明図で、（ａ）は平面図、（ｂ）は図２（ａ）のＸ−Ｘ’線での断面図である。It is explanatory drawing of the 2nd Example of this invention, (a) is a top view, (b) is sectional drawing in the X-X 'line | wire of Fig.2 (a). 本発明の説明図である。It is a description diagram of the present invention. 本発明と従来例の抵抗印加電圧と抵抗変化率を示す図である。It is a figure which shows the resistance applied voltage and resistance change rate of this invention and a prior art example . 本発明の効果を説明する図である。 It is a figure explaining the effect of this invention .

１；半絶縁性基板、２、３；抵抗素子、４；ガード層、５；絶縁領域 DESCRIPTION OF SYMBOLS 1; Semi-insulating board | substrate, 2, 3; Resistance element, 4; Guard layer, 5; Insulation area | region

Claims

半導体基板上の絶縁領域あるいは半絶縁領域に、一導電型の半導体領域で形成された抵抗素子が隣接して配置された半導体装置において、
一の前記抵抗素子と、隣接する別の前記抵抗素子との間の前記絶縁領域あるいは半絶縁領域に、一導電型の半導体領域からなり、フローティグ状態のガード層を備え、隣接する前記抵抗素子間に電位差が生じ、前記抵抗素子の一方から空乏層が広がるとき、前記ガード層で前記空乏層の広がりを抑えることを特徴とする半導体装置。In a semiconductor device in which a resistance element formed of a semiconductor region of one conductivity type is disposed adjacent to an insulating region or a semi-insulating region on a semiconductor substrate,
The insulating element or the semi-insulating area between one of the resistive elements and another adjacent resistive element is made of a semiconductor region of one conductivity type and includes a guard layer in a floating state, and the adjacent resistive element A semiconductor device characterized in that when a potential difference occurs between them and a depletion layer spreads from one of the resistance elements, the guard layer suppresses the spread of the depletion layer.