JP4894347B2 - Semiconductor integrated circuit element mounting substrate and semiconductor device - Google Patents

Semiconductor integrated circuit element mounting substrate and semiconductor device Download PDF

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JP4894347B2
JP4894347B2 JP2006125991A JP2006125991A JP4894347B2 JP 4894347 B2 JP4894347 B2 JP 4894347B2 JP 2006125991 A JP2006125991 A JP 2006125991A JP 2006125991 A JP2006125991 A JP 2006125991A JP 4894347 B2 JP4894347 B2 JP 4894347B2
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integrated circuit
semiconductor integrated
stiffener
slit
circuit element
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JP2007299887A (en
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美保 生稲
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Toppan Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

本発明は半導体集積回路素子を多層回路配線板に接続する際に、半導体集積回路素子に掛かる応力を緩和する構造に関する。詳しくは、補強材、放熱材として多層回路配線板に固着してあるスティフナーに関する。   The present invention relates to a structure for relaxing stress applied to a semiconductor integrated circuit element when the semiconductor integrated circuit element is connected to a multilayer circuit wiring board. Specifically, the present invention relates to a stiffener that is fixed to a multilayer circuit wiring board as a reinforcing material and a heat dissipation material.

半導体装置用の大規模集積回路（ＬＳＩ）等の半導体集積回路素子（以下半導体素子という）には、近年、その動作速度がクロック周波数で１ＧＨｚに達するものが出現している。このような高速度の半導体素子では、トランジスターの集積度が高く、その結果入出力端子数が１０００を越えることもある。
このような多端子数の半導体素子をプリント配線板に実装するために、半導体素子とプリント配線板の基板との間には、インターポーザと呼ばれる多層回路配線板が配置され、両者の電気的接合の橋渡しを担っている。
前記多層回路配線板（インターポーザ）では、高密度に配置した半導体素子の端子との接合に対応するため、非常に薄い配線層等の層構造と、微細なライン・アンド・スペースを有する回路配線パターンを持つ特徴がある。 In recent years, semiconductor integrated circuit elements (hereinafter referred to as semiconductor elements) such as large-scale integrated circuits (LSIs) for semiconductor devices have appeared that have an operating speed of 1 GHz as a clock frequency. In such a high-speed semiconductor device, the degree of integration of transistors is high, and as a result, the number of input / output terminals may exceed 1000.
In order to mount such a multi-terminal semiconductor element on a printed wiring board, a multilayer circuit wiring board called an interposer is disposed between the semiconductor element and the printed wiring board substrate, and electrical connection between the two is achieved. It serves as a bridge.
In the multilayer circuit wiring board (interposer), a circuit wiring pattern having a very thin layer structure such as a wiring layer and a fine line and space in order to cope with bonding with terminals of semiconductor elements arranged at high density There is a feature with.

現在広く実用化されているインターポーザとしては、例えばＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）やＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）等が挙げられる。最近では、更なる高密度実装への対応、又は高速度の動作周波数化への要望に答えるため、ポリイミド樹脂フィルムなどの基板に銅箔等からなる配線パターンを形成した導体層を積層してインターポーザ全体の基板厚を薄くすると共に、導体層間の接続長を短くすることにより高周波数に対応させたものも開発されてきている。
インターポーザへの半導体素子の搭載は、ハンダリフロー過程の処理プロセスにより行う。この製造プロセスでは、インターポーザと半導体素子との位置合わせの後、全体の雰囲気温度を２６０℃近辺まで昇温して、ハンダバンプを高温で融解し、インターポーザと半導体素子の各々ハンダバンプの所定箇所間を接合し、常温に戻す。温度低下と共に、ハンダバンプは固化してハンダバンプ接合は固定される。
このハンダリフロー過程の処理プロセスでは、インターポーザは薄く撓み易いので半導体素子搭載箇所を取り囲む形状のスティフナーと呼ばれる金属板を固着させ操作する。スティフナーは同一幅の枠型が一般的である。 Examples of interposers that are currently in wide use include BGA (Ball Grid Array) and CSP (Chip Size Package). Recently, in order to respond to the demand for higher density mounting or higher operating frequency, an interposer is formed by laminating a conductor layer with a wiring pattern made of copper foil etc. on a substrate such as a polyimide resin film. In addition to reducing the overall thickness of the substrate and shortening the connection length between the conductor layers, ones corresponding to high frequencies have been developed.
The semiconductor element is mounted on the interposer by a solder reflow process. In this manufacturing process, after the alignment of the interposer and the semiconductor element, the entire ambient temperature is raised to around 260 ° C., the solder bumps are melted at a high temperature, and the solder bumps of the interposer and the semiconductor element are joined between the predetermined portions of the solder bumps. Return to room temperature. As the temperature decreases, the solder bumps solidify and the solder bump joint is fixed.
In this solder reflow process, the interposer is thin and easy to bend, so that a metal plate called a stiffener having a shape surrounding the semiconductor element mounting portion is fixed and operated. The stiffener is generally a frame type with the same width.

シリコンからなる半導体素子の熱膨張係数は約３ppm/℃であり、ポリイミドからなる多層回路配線基板の熱膨張係数は約２０ppm/℃である。リフローによる接続でハンダが凝固し、室温に戻る際、冷却により多層回路配線基板、半導体素子ともに収縮する。
多層回路配線板の半導体素子が搭載された部分はハンダによって半導体素子と固定されているため半導体素子が縮む量しか縮めず、伸びを維持した状態となっているのに対し、半導体素子より外周は可動できるため内側に縮む力が働く。このことから半導体素子との境界部分の多層回路配線板に変形が生じ、更に半導体素子にも応力がかかる。
特に半導体素子の角の部分では１点で応力が集中されてしまう。
また、同一幅の枠型のスティフナーが取りつけてあることにより、多層回路配線基板は半導体素子にかかる応力が分散しづらく、バンプの接続不良および素子の割れが発生しやすくなる。
このような問題を解決するために、半導体チップの応力を分散させるべく、スティフナー内周コーナー部に湾曲状の切り欠きを形成したことを特徴とする半導体装置が提案されている（特許文献１参照）。 A semiconductor element made of silicon has a thermal expansion coefficient of about 3 ppm / ° C., and a multilayer circuit wiring board made of polyimide has a thermal expansion coefficient of about 20 ppm / ° C. When the solder is solidified by reflow connection and returns to room temperature, both the multilayer circuit wiring board and the semiconductor element shrink due to cooling.
The part of the multilayer circuit wiring board where the semiconductor element is mounted is fixed to the semiconductor element by soldering, so that the semiconductor element can only be shrunk and maintained in an expanded state. Because it can move, the force shrinks inward. As a result, deformation occurs in the multilayer circuit wiring board at the boundary with the semiconductor element, and stress is also applied to the semiconductor element.
In particular, stress is concentrated at one point in the corner portion of the semiconductor element.
In addition, since the frame-type stiffeners having the same width are attached, the stress applied to the semiconductor element is difficult to disperse in the multilayer circuit wiring board, and bump connection failure and element cracking are likely to occur.
In order to solve such a problem, a semiconductor device is proposed in which a curved notch is formed in the inner peripheral corner portion of the stiffener in order to disperse the stress of the semiconductor chip (see Patent Document 1). ).

また、近年、半導体デバイスの端子数の増加と動作クロック周波数の向上で、リーク電流が増えてきたために、従来から用いられていたシリコン酸化膜（ｋ＝４．１）に代り、Ｌｏｗ−ｋ材と呼ばれる低誘電率材料を絶縁膜として用いた半導体素子（半導体チップ）が使用されるようになっている。
しかし、Ｌｏｗ−ｋ材による絶縁膜はもろく、実装した多層回路配線基板の変形に耐えられず破壊されてしまうという問題があった。特に、多層回路配線基板が内層コアを有さない、フレキシブルなフィルム状絶縁体を絶縁層に用いたいわゆる薄型のコアレス基板である場合、熱履歴による変形は従来のプリント配線板よりも大きいため、Ｌｏｗ−ｋ材を用いた半導体チップの実装は困難を極めていた。
特開平１１−２８４０９７号公報 Further, in recent years, leakage current has increased due to an increase in the number of terminals of a semiconductor device and an improvement in operation clock frequency. Therefore, a low-k material has been used in place of the conventionally used silicon oxide film (k = 4.1). A semiconductor element (semiconductor chip) using a low dielectric constant material called as an insulating film is used.
However, the insulating film made of the low-k material is fragile, and there is a problem that it cannot withstand the deformation of the mounted multilayer circuit wiring board and is destroyed. In particular, when the multilayer circuit wiring board is a so-called thin coreless board that uses a flexible film-like insulator as an insulating layer without an inner layer core, the deformation due to the thermal history is larger than the conventional printed wiring board, Mounting a semiconductor chip using a low-k material has been extremely difficult.
JP-A-11-284097

しかし、厚さが０.５mm以下の多層回路配線基板では、半導体素子実装後の多層回路配線基板の変形が大きいためBGAボール搭載、母基板への実装が困難である。多層回路回線基板の変形を抑制するにはスティフナーの内周を狭くし、より半導体素子に近づけることが効果的であるが、応力を分散させるために、内周コーナー部に切り欠きを設けてしまうと、多層回路配線基板に対する変形抑制効果は失われるという不利があった。
本発明は、従来の技術における、前記の様な問題点を解決するためになされたものであり、その目的は、応力の分散を図りつつ多層回路配線基板に対する変形抑制効果を確保する上で有利な半導体集積回路素子搭載用基板および半導体装置を提供することにある。 However, in a multilayer circuit wiring board having a thickness of 0.5 mm or less, since the deformation of the multilayer circuit wiring board after mounting the semiconductor element is large, it is difficult to mount the BGA ball on the mother board. To suppress the deformation of the multilayer circuit board, it is effective to narrow the inner periphery of the stiffener and bring it closer to the semiconductor element, but in order to disperse the stress, a notch is provided in the inner peripheral corner portion. And there was a disadvantage that the deformation suppressing effect on the multilayer circuit wiring board was lost.
The present invention has been made in order to solve the above-described problems in the prior art, and the object thereof is advantageous in securing the effect of suppressing deformation of the multilayer circuit wiring board while distributing the stress. Another object of the present invention is to provide a semiconductor integrated circuit device mounting substrate and a semiconductor device.

上述の目的を達成するため、請求項１記載の発明は、厚さ方向の一方の面が半導体集積回路素子を搭載するための搭載面として形成された多層回路配線基板と、前記搭載面に接着され４つの角部を有する矩形板状のスティフナーとを備え、前記スティフナーには、前記半導体集積回路素子を収納可能な矩形状の開口部が、その開口部を構成する縁の４辺を前記スティフナーの４辺に平行させて形成されている半導体集積回路素子搭載用基板であって、前記開口部の各角部と前記スティフナーの対応する各角部にわたり延在するスリットが設けられ、前記スリットの延在方向の一端は前記開口部に開放状に形成され、他端は前記スティフナーの対応する角部の近傍に位置し、前記スリットの延在方向と直交する方向における前記スリットの幅は前記スリットの延在方向の長さよりも小さい寸法で形成され、前記スリットは前記幅が１ｍｍ以上３ｍｍ以下の寸法で形成され、前記スリットの他端とこのスリットに対応する前記スティフナーの角部との距離が０．５ｍｍ以上５ｍｍ以下であり、前記搭載面には前記半導体集積回路素子と接続するための電極バンプが形成され、前記スティフナーの厚さは、前記半導体集積回路素子の厚さと前記電極バンプの高さとの和と等しいことを特徴とする。
請求項２記載の発明は、前記多層回路配線基板は、絶縁性フィルムと、前記絶縁性フィルムの厚さ方向の両面に積層された配線層とを含んで構成されていることを特徴とする。
請求項３記載の発明は、前記開口部の角部とこの角部に対応する前記スティフナーの角部との間を結ぶ仮想線上に前記開口部の中心が位置していることを特徴とする。
請求項４記載の発明は、前記多層回路配線基板の厚さは０．０５ｍｍ以上０．５ｍｍ以下であることを特徴とする。
請求項５記載の発明は、請求項１乃至４に何れか１項記載の半導体集積回路素子搭載用基板の前記搭載面上で前記開口部の内側に前記半導体集積回路素子が搭載され、前記半導体集積回路素子は導電部を介して前記多層回路配線基板と電気的に接続された半導体装置であって、前記半導体集積回路素子は低誘電率材料を絶縁膜として用いたものであることを特徴とする。
請求項６記載の発明は、前記導電部は、前記半導体集積回路素子が前記搭載面に臨む箇所に設けられたはんだバンプと、前記搭載面が前記半導体集積回路素子に臨む箇所に設けられた電極パッドとがはんだ接合されることで構成されていることを特徴とする。
請求項７記載の発明は、厚さ方向の一方の面が半導体集積回路素子を搭載するための搭載面として形成された多層回路配線基板と、前記搭載面に接着され４つの角部を有する外形が４０ｍｍ×４０ｍｍの矩形板状のスティフナーとを備え、前記スティフナーには、前記半導体集積回路素子を収納可能な２５ｍｍ×２５ｍｍの矩形状の開口部が、その開口部を構成する縁の４辺を前記スティフナーの４辺に平行させて形成されている半導体集積回路素子搭載用基板であって、前記開口部の各角部と前記スティフナーの対応する各角部にわたり延在するスリットが設けられ、前記スリットの延在方向の一端は前記開口部に開放状に形成され、他端は前記スティフナーの対応する角部の近傍に位置し、前記スリットの延在方向と直交する方向における前記スリットの幅は前記スリットの延在方向の長さよりも小さい寸法で形成され、前記多層回路配線基板は、絶縁性フィルムと、前記絶縁性フィルムの厚さ方向の両面に積層された配線層とを含んで構成され、前記スリットは前記幅が１ｍｍ以上３ｍｍ以下の寸法で形成され、前記開口部の角部とこの角部に対応する前記スティフナーの角部との間を結ぶ仮想線上に前記開口部の中心が位置し、前記スリットの他端とこのスリットに対応する前記スティフナーの角部との距離が０．５ｍｍ以上５ｍｍ以下であり、前記多層回路配線基板の厚さは０．０５ｍｍ以上０．５ｍｍ以下であり、前記搭載面には前記半導体集積回路素子と接続するための電極バンプが形成され、前記スティフナーの厚さは、前記半導体集積回路素子の厚さと前記電極バンプの高さとの和と等しいことを特徴とする。
In order to achieve the above object, the invention according to claim 1 is directed to a multilayer circuit wiring board in which one surface in the thickness direction is formed as a mounting surface for mounting a semiconductor integrated circuit element, and bonded to the mounting surface. A rectangular plate-shaped stiffener having four corners, and the stiffener has a rectangular opening capable of accommodating the semiconductor integrated circuit element, and the stiffener has four sides that constitute the opening. The semiconductor integrated circuit element mounting substrate is formed in parallel with the four sides of the substrate, and includes slits extending over the corners of the opening and the corresponding corners of the stiffener. the extending direction of the one end of which is formed in an open shape in the opening, the other end is located near the corresponding corner of the stiffener, the width of the slit in the direction orthogonal to the extending direction of the slits The slit is formed with a dimension that is smaller than the length in the extending direction of the slit, and the slit is formed with a width of 1 mm to 3 mm, and the other end of the slit and the corner of the stiffener corresponding to the slit The distance is 0.5 mm or more and 5 mm or less, and an electrode bump for connecting to the semiconductor integrated circuit element is formed on the mounting surface, and the thickness of the stiffener is the thickness of the semiconductor integrated circuit element and the electrode bump. It is characterized by being equal to the sum of the heights .
The invention according to claim 2 is characterized in that the multilayer circuit wiring board includes an insulating film and wiring layers laminated on both surfaces in the thickness direction of the insulating film.
The invention according to claim 3 is characterized in that the center of the opening is located on an imaginary line connecting the corner of the opening and the corner of the stiffener corresponding to the corner.
The invention according to claim 4 is characterized in that the thickness of the multilayer circuit wiring board is 0.05 mm or more and 0.5 mm or less.
According to a fifth aspect of the present invention, the semiconductor integrated circuit element is mounted inside the opening on the mounting surface of the semiconductor integrated circuit element mounting substrate according to any one of the first to fourth aspects, and the semiconductor An integrated circuit element is a semiconductor device electrically connected to the multilayer circuit wiring board through a conductive portion, wherein the semiconductor integrated circuit element uses a low dielectric constant material as an insulating film. To do.
According to a sixth aspect of the present invention, the conductive portion includes a solder bump provided at a location where the semiconductor integrated circuit element faces the mounting surface, and an electrode provided at a location where the mounting surface faces the semiconductor integrated circuit element. It is characterized by comprising a pad and a solder joint.
The invention according to claim 7 is a multilayer circuit wiring board in which one surface in the thickness direction is formed as a mounting surface for mounting a semiconductor integrated circuit element, and an outer shape having four corners bonded to the mounting surface. Includes a rectangular plate-shaped stiffener having a size of 40 mm × 40 mm. The stiffener has a rectangular opening of 25 mm × 25 mm capable of accommodating the semiconductor integrated circuit element, and has four sides of an edge constituting the opening. A substrate for mounting a semiconductor integrated circuit element formed in parallel with four sides of the stiffener, wherein each slit of the opening and a slit extending over each corresponding corner of the stiffener are provided, One end in the extending direction of the slit is formed open in the opening, and the other end is located in the vicinity of the corresponding corner of the stiffener and in a direction perpendicular to the extending direction of the slit. The width of the slit is formed with a dimension smaller than the length in the extending direction of the slit, and the multilayer circuit wiring board includes an insulating film, and a wiring layer laminated on both surfaces of the insulating film in the thickness direction. The slit is formed with a width of 1 mm or more and 3 mm or less, and the opening is formed on a virtual line connecting a corner of the opening and a corner of the stiffener corresponding to the corner. The distance between the other end of the slit and the corner of the stiffener corresponding to the slit is 0.5 mm or more and 5 mm or less, and the thickness of the multilayer circuit wiring board is 0.05 mm or more and 0 5 mm or less, and electrode bumps for connection to the semiconductor integrated circuit element are formed on the mounting surface, and the thickness of the stiffener is equal to the thickness of the semiconductor integrated circuit element and the electrode bar. Characterized in that equal to a sum of the height of the flop.

本発明によれば、スリットの延在方向の一端をスティフナの開口部に開放状に形成し、他端をスティフナーの対応する角部の近傍に位置し、スリットの延在方向と直交する方向におけるスリットの幅をスリットの延在方向の長さよりも小さい寸法で形成したので、スリットとして可動性を持たせることができ、多層回路配線基板全体で応力を分散させる上で有利となる。   According to the present invention, one end in the slit extending direction is formed in an open shape at the opening of the stiffener, and the other end is positioned in the vicinity of the corresponding corner of the stiffener, in a direction perpendicular to the slit extending direction. Since the slit has a width smaller than the length in the extending direction of the slit, the slit can be provided with mobility, which is advantageous in distributing stress throughout the multilayer circuit wiring board.

次に本発明の実施の形態を添付の図面を基にして詳細に説明する。
図１は本実施の形態の半導体集積回路素子搭載用基板２の断面図、図２は本実施の形態の半導体装置１００の断面図である。
図１に示すように、半導体集積回路素子搭載用基板２は、多層回路配線基板１０と、スティフナー２０とを備えている。
多層回路配線基板１０は、絶縁基材１６（特許請求の範囲の絶縁性フィルムに相当）と、絶縁基材１６の厚さ方向の両面に積層された配線層１５とを含んで構成されている。本実施の形態では、多層回路配線基板１０の厚さは０．０５ｍｍ以上０．５ｍｍ以下の寸法で形成されている。
多層回路配線基板１０の厚さは、０．０５ｍｍ未満であると、基板の剛性が低下し変形をスティフナーで抑えきれない点で不利があり、０．５ｍｍより大きいと、基板の配線が長くなるので電気特性が悪くなる点で不利がある。
絶縁基材１６としては、例えば、ガラス／エポキシ樹脂やポリイミド樹脂などが用いられている。また、配線層１５としては、素材として銅がもっとも好ましいが、金属ペーストの焼結体なども任意に選択できる。
各配線層１５の表面はソルダーレジスト１３、１４で覆われている。
多層回路配線基板１０の厚さ方向の一方の面（ソルダーレジスト１３の表面）が半導体集積回路素子３０（図２参照）を搭載するための搭載面１０Ａとして形成されている。
搭載面１０Ａには半導体集積回路素子３０と接続するための電極バンプ１１が形成され、搭載面１０Ａの反対面１０Ｂには、ハンダボール用パッド１２が形成されている。
スティフナー２０は、多層回路配線基板１０の搭載面１０Ａの所定位置に接着剤層２１を介して貼り合わせされ、加熱、硬化して固定されている。
図２に示すように、半導体装置１００は、半導体集積回路素子搭載用基板２に半導体集積回路素子３０を実装し、スティフナー２０の内側で半導体集積回路素子３０と多層回路配線基板１０との間に、半導体集積回路素子３０と多層回路配線基板１０との接合を強化するためのアンダーフィル樹脂４１を充填し、ハンダボール用パッド１２上にはんだボール５１を形成したものである。 Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view of a semiconductor integrated circuit element mounting substrate 2 of the present embodiment, and FIG. 2 is a cross-sectional view of a semiconductor device 100 of the present embodiment.
As shown in FIG. 1, the semiconductor integrated circuit element mounting board 2 includes a multilayer circuit wiring board 10 and a stiffener 20.
The multilayer circuit wiring board 10 includes an insulating base material 16 (corresponding to an insulating film in claims) and a wiring layer 15 laminated on both surfaces of the insulating base material 16 in the thickness direction. . In the present embodiment, the multilayer circuit wiring board 10 is formed with a thickness of 0.05 mm or more and 0.5 mm or less.
If the thickness of the multilayer circuit wiring board 10 is less than 0.05 mm, there is a disadvantage in that the rigidity of the board decreases and deformation cannot be suppressed by a stiffener. If the thickness is larger than 0.5 mm, the wiring on the board becomes long. Therefore, there is a disadvantage in that the electrical characteristics are deteriorated.
For example, glass / epoxy resin or polyimide resin is used as the insulating substrate 16. The wiring layer 15 is most preferably copper as a material, but a sintered body of a metal paste or the like can be arbitrarily selected.
The surface of each wiring layer 15 is covered with solder resists 13 and 14.
One surface (the surface of the solder resist 13) in the thickness direction of the multilayer circuit wiring board 10 is formed as a mounting surface 10A for mounting the semiconductor integrated circuit element 30 (see FIG. 2).
Electrode bumps 11 for connection to the semiconductor integrated circuit element 30 are formed on the mounting surface 10A, and solder ball pads 12 are formed on the opposite surface 10B of the mounting surface 10A.
The stiffener 20 is bonded to a predetermined position on the mounting surface 10A of the multilayer circuit wiring board 10 via an adhesive layer 21, and is fixed by heating and curing.
As shown in FIG. 2, the semiconductor device 100 has the semiconductor integrated circuit element 30 mounted on the semiconductor integrated circuit element mounting substrate 2, and the semiconductor integrated circuit element 30 is interposed between the semiconductor integrated circuit element 30 and the multilayer circuit wiring substrate 10 inside the stiffener 20. The underfill resin 41 for reinforcing the bonding between the semiconductor integrated circuit element 30 and the multilayer circuit wiring board 10 is filled, and the solder balls 51 are formed on the solder ball pads 12.

以下、本発明の半導体装置の製造法について説明する。
まず、厚さ方向の一方の面（搭載面１０Ａ）に電極バンプ１１が形成され、他方の面（反対面１０Ｂ）にはんだボール用パッド１２が形成され、搭載面１０Ａ、反対面１０Ｂにそれぞれソルダーレジスト１３、１４が形成された多層回路配線板１０を作製する。
なお、はんだボール用パッド１２は、ソルダーレジスト１４に形成されたソルダーレジスト開口部を介して外方に露出している。 Hereinafter, a method for manufacturing the semiconductor device of the present invention will be described.
First, electrode bumps 11 are formed on one surface (mounting surface 10A) in the thickness direction, solder ball pads 12 are formed on the other surface (opposite surface 10B), and solder is mounted on the mounting surface 10A and the opposite surface 10B, respectively. The multilayer circuit wiring board 10 on which the resists 13 and 14 are formed is produced.
The solder ball pads 12 are exposed to the outside through the solder resist openings formed in the solder resist 14.

次に、枠の内周にスリット５６を有するスティフナー２０を用意する。
図３はスティフナー２０の平面図である。
図３に示すように、スティフナー２０は４つの角部５０を有する矩形板状に形成されている。
スティフナー２０には、半導体集積回路素子３０を収納可能な矩形状の開口部５２が、その開口部５２を構成する縁の４辺をスティフナー２０の４辺に平行させて形成されている。
開口部５２の各角部５４とスティフナー２０の対応する各角部５０にわたりスリット５６が設けられている。
スリット５６の延在方向の一端は開口部５２に開放状に形成され、他端はスティフナー２０の対応する角部５０の近傍に位置している。
スリット５６の延在方向と直交する方向におけるスリット５６の幅Ｗはスリット５６の延在方向の長さＬ１よりも小さい寸法で形成されている。
本実施の形態では、スリットは幅Ｗが１ｍｍ以上３ｍｍ以下の寸法で形成されている。
スリットの幅Ｗが１ｍｍ未満であると、応力緩和の効果が弱くなる点で不利があり、３ｍｍより大きいと基板の平坦度が悪化する点で不利がある。
また、開口部５２の角部５４とこの角部５４に対応するスティフナー２０の角部５０との間を結ぶ仮想線上に開口部５２の中心が位置している。
スリット５６の他端とこのスリット５６に対応するスティフナー２０の角部５０との距離Ｌ２が０．５ｍｍ以上５ｍｍ以下の寸法で形成されている。
距離Ｌ２が０．５ｍｍ未満であると、スティフナーの強度が低下して基板の変形を抑えられない点で不利があり、５ｍｍより大きいと、応力緩和効果が弱くなる点で不利がある。 Next, a stiffener 20 having a slit 56 on the inner periphery of the frame is prepared.
FIG. 3 is a plan view of the stiffener 20.
As shown in FIG. 3, the stiffener 20 is formed in a rectangular plate shape having four corners 50.
In the stiffener 20, a rectangular opening 52 that can accommodate the semiconductor integrated circuit element 30 is formed so that four edges of the opening 52 are parallel to the four sides of the stiffener 20.
A slit 56 is provided across each corner 54 of the opening 52 and each corresponding corner 50 of the stiffener 20.
One end of the slit 56 in the extending direction is formed in the opening 52 so as to be open, and the other end is positioned in the vicinity of the corresponding corner 50 of the stiffener 20.
The width W of the slit 56 in the direction orthogonal to the extending direction of the slit 56 is formed to be smaller than the length L1 of the extending direction of the slit 56.
In the present embodiment, the slit is formed with a width W of 1 mm or more and 3 mm or less.
If the slit width W is less than 1 mm, there is a disadvantage in that the effect of stress relaxation becomes weak, and if it is more than 3 mm, there is a disadvantage in that the flatness of the substrate deteriorates.
Further, the center of the opening 52 is located on an imaginary line connecting the corner 54 of the opening 52 and the corner 50 of the stiffener 20 corresponding to the corner 54.
A distance L2 between the other end of the slit 56 and the corner portion 50 of the stiffener 20 corresponding to the slit 56 is formed with a dimension of 0.5 mm or more and 5 mm or less.
If the distance L2 is less than 0.5 mm, there is a disadvantage in that the strength of the stiffener is lowered and the deformation of the substrate cannot be suppressed, and if it is greater than 5 mm, the stress relaxation effect is weakened.

また、スティフナー２０の材質としては多層回路配線基板１０と熱膨張係数が近い銅のほかに、４２Alloy、インバー、Alのような金属やセラミックスや樹脂なども可能である。
また、図２に示すように、スティフナー２０の厚さは半導体集積回路素子３０の厚さと電極バンプ１１の高さを合わせた高さと同じにする必要がある。
これは、放熱板６０を半導体集積回路素子３０の多層回路配線基板１０と接続されていない面に貼り合わせることから、半導体集積回路素子３０の多層回路配線基板１０と接続されていない面とスティフナー２０上面の高さが揃っている必要があるためである。
スティフナー２０の製法はエッチング、金型による打ち抜き、ワイヤーカットなどによる。
スティフナー２０の形状は枠型であるが、枠の内側は半導体集積回路素子３０が搭載されるため、半導体集積回路素子３０の外形サイズよりも大きい必要がある。
図３に示すように、スティフナー２０の開口部５２の各角部５４から形成させるスリット５６は開口部５２の角部５４から対応するスティフナー２０の角部５０に向かって形成させる。応力を均等に分散させるために、スリット５６の形状は、スリット５６の外側に配置されるスティフナー２０の角部５０と開口部５２の中心とをつなぐ直線に対して線対称のＵ字型あるいはＩ字型を呈している。
スリット５６の外側に配置されるスティフナー２０の角部５０と開口部５２の中心とをつなぐ直線に対して垂直方向のスリット５６の幅Ｗを３ｍｍ以下にすることで、半導体集積回路素子３０を実装した後の多層回路配線基板１０の変形を抑えるべくスティフナー２０内側をより半導体集積回路素子３０に近づけた場合に、多層回路配線基板１０の補強効果は損なわれることはない。
また、スリット５６の長さＬ１は長いほど多層回路配線基板１０の可動性は増すが、補強効果も持ちつつ、多層回路配線基板１０全体で動くことを可能とするためには、スリット５６の他端とスティフナー２０の角部５０との距離Ｌ２を０.５ｍｍ以上とするのが良い。
その結果、スリット５６全体として可動性を持たせることができ、多層回路配線基板１０全体で応力を分散させることが可能となり、半導体集積回路素子３０に掛かる応力を緩和させられ、更に、実装後の多層回路配線基板１０の変形も抑制させることができる。 Further, as the material of the stiffener 20, in addition to copper having a thermal expansion coefficient close to that of the multilayer circuit wiring board 10, metals such as 42Alloy, Invar, Al, ceramics, and resins can be used.
Further, as shown in FIG. 2, the thickness of the stiffener 20 needs to be the same as the combined height of the semiconductor integrated circuit element 30 and the electrode bump 11.
This is because the heat sink 60 is bonded to the surface of the semiconductor integrated circuit element 30 that is not connected to the multilayer circuit wiring board 10, so that the surface of the semiconductor integrated circuit element 30 that is not connected to the multilayer circuit wiring board 10 and the stiffener 20. This is because the height of the upper surface needs to be uniform.
The stiffener 20 is manufactured by etching, punching with a mold, wire cutting, or the like.
The shape of the stiffener 20 is a frame type, but since the semiconductor integrated circuit element 30 is mounted inside the frame, it needs to be larger than the outer size of the semiconductor integrated circuit element 30.
As shown in FIG. 3, the slit 56 formed from each corner 54 of the opening 52 of the stiffener 20 is formed from the corner 54 of the opening 52 toward the corresponding corner 50 of the stiffener 20. In order to evenly distribute the stress, the shape of the slit 56 is U-shaped or I-symmetric with respect to a straight line connecting the corner 50 of the stiffener 20 and the center of the opening 52 arranged outside the slit 56. It has a letter shape.
The semiconductor integrated circuit element 30 is mounted by setting the width W of the slit 56 in the direction perpendicular to the straight line connecting the corner 50 of the stiffener 20 and the center of the opening 52 arranged outside the slit 56 to 3 mm or less. When the inside of the stiffener 20 is brought closer to the semiconductor integrated circuit element 30 in order to suppress the deformation of the multilayer circuit wiring board 10 after this, the reinforcing effect of the multilayer circuit wiring board 10 is not impaired.
In addition, the longer the length L1 of the slit 56, the greater the mobility of the multilayer circuit wiring board 10. However, in order to be able to move the entire multilayer circuit wiring board 10 while having a reinforcing effect, A distance L2 between the end and the corner portion 50 of the stiffener 20 is preferably 0.5 mm or more.
As a result, the slit 56 as a whole can be provided with mobility, the stress can be distributed over the entire multilayer circuit wiring board 10, the stress applied to the semiconductor integrated circuit element 30 can be relieved, and further, after mounting. The deformation of the multilayer circuit wiring board 10 can also be suppressed.

次に、多層回路配線基板１０の所定位置にスティフナー２０を貼り合わせ、加圧、加熱することによって、半導体集積回路素子搭載用基板２が製作される。   Next, the stiffener 20 is bonded to a predetermined position of the multilayer circuit wiring board 10, pressurized and heated to manufacture the semiconductor integrated circuit element mounting substrate 2.

次に、はんだバンプ３１が形成された半導体集積回路素子３０をスティフナー２０が設けられた多層回路配線板１０の搭載面１０Ａの所定位置に載置し、ハンダリフローにて半導体集積回路素子３０のはんだバンプ３１との多層回路配線板１０の電極パッド１１をはんだ接合する。
これにより半導体装置１００が完成する。 Next, the semiconductor integrated circuit element 30 on which the solder bumps 31 are formed is placed at a predetermined position on the mounting surface 10A of the multilayer circuit wiring board 10 provided with the stiffener 20, and the solder of the semiconductor integrated circuit element 30 is soldered by reflow. The electrode pads 11 of the multilayer circuit wiring board 10 with the bumps 31 are soldered.
Thereby, the semiconductor device 100 is completed.

（実施例）
まず、厚さ方向の一方の面（搭載面１０Ａ）に電極パッド１１を、他方の面（反対面１０Ｂ）にはんだボール用パッド１２及びソルダーレジスト１３を形成した４０×４０ｍｍサイズで１５０μｍ厚の多層回路配線基板１０を作製した。
次に、スティフナー２０を作製した。スティフナー２０の外形は４０×４０mm、開口部５２の内周は２５×２５mmとした。厚さは５００μｍ、材質はＣｕとした。
スリット５６の幅Ｗは２.５mm、スリット５６の他端とスティフナー２０の角部５０との距離Ｌ２は２mmとした。
次に、多層回路配線基板１０の所定位置にスティフナー２０を貼り合わせ、加圧、加熱した。
次に、はんだバンプ３１が形成された２０ｍｍ角の半導体集積回路素子３０をスティフナー２０が形成された多層回路配線基板１０の載置面１０Ａ上の所定位置に載置し、ハンダリフローにて半導体集積回路素子３０のはんだバンプ３１と多層回路配線基板１０の電極パッド１１をはんだ接合した。
次に、半導体集積回路素子３０と多層回路配線基板１０間にアンダーフィル樹脂４１を充填、硬化した。
次に、半導体集積回路素子３０の背面に４０ｍｍ角の銅からなる放熱板６０を接着させた。
さらに、はんだボール用パッド１２上のソルダーレジスト開口部にはんだ球を載置し、はんだリフローにてはんだボール用パッド１２上にはんだボール５１を形成した。
これにより、半導体装置１００を得た。 (Example)
First, a multilayer of 40 × 40 mm size and 150 μm thickness in which electrode pad 11 is formed on one surface (mounting surface 10A) in the thickness direction and solder ball pad 12 and solder resist 13 are formed on the other surface (opposite surface 10B). A circuit wiring board 10 was produced.
Next, stiffener 20 was produced. The outer shape of the stiffener 20 was 40 × 40 mm, and the inner periphery of the opening 52 was 25 × 25 mm. The thickness was 500 μm and the material was Cu.
The width W of the slit 56 was 2.5 mm, and the distance L2 between the other end of the slit 56 and the corner portion 50 of the stiffener 20 was 2 mm.
Next, the stiffener 20 was bonded to a predetermined position of the multilayer circuit wiring board 10, and was pressurized and heated.
Next, the 20 mm square semiconductor integrated circuit element 30 on which the solder bumps 31 are formed is placed at a predetermined position on the placement surface 10A of the multilayer circuit wiring board 10 on which the stiffener 20 is formed, and the semiconductor integration is performed by solder reflow. The solder bumps 31 of the circuit element 30 and the electrode pads 11 of the multilayer circuit wiring board 10 were soldered.
Next, an underfill resin 41 was filled between the semiconductor integrated circuit element 30 and the multilayer circuit wiring board 10 and cured.
Next, a heat sink 60 made of 40 mm square copper was bonded to the back surface of the semiconductor integrated circuit element 30.
Further, solder balls were placed in the solder resist openings on the solder ball pads 12, and solder balls 51 were formed on the solder ball pads 12 by solder reflow.
Thereby, the semiconductor device 100 was obtained.

（比較例１）
比較例１で用いる多層回路配線基板１０と半導体集積回路素子３０は実施例１と同様のものを用いた。
また、スティフナー２０の外形は４０×４０mm、開口部５２の内周は２５×２５mmとした。
厚さは５００μｍ、材質はＣｕとしたが、開口部５２の角部５４にスリット５６を設けていない。
比較例１も実施例１と同様に多層回路配線基板１０にスティフナー２０を貼り合わせた後、半導体集積回路素子３０をはんだ接合させ、半導体集積回路素子３０と多層回路配線基板１０との間にアンダーフィル樹脂４１を充填、硬化させた。
さらに、はんだボール用パッド１２上のソルダーレジスト開口部にはんだ球を載置し、はんだリフローにてはんだボール用パッド１２上にはんだボール５１を形成して、半導体装置１００を得た。 (Comparative Example 1)
The multilayer circuit wiring board 10 and the semiconductor integrated circuit element 30 used in Comparative Example 1 were the same as those in Example 1.
The outer shape of the stiffener 20 was 40 × 40 mm, and the inner periphery of the opening 52 was 25 × 25 mm.
Although the thickness is 500 μm and the material is Cu, no slit 56 is provided at the corner 54 of the opening 52.
In the first comparative example, the stiffener 20 is bonded to the multilayer circuit wiring board 10 in the same manner as in the first embodiment, and then the semiconductor integrated circuit element 30 is solder-bonded. Fill resin 41 was filled and cured.
Furthermore, a solder ball was placed in the solder resist opening on the solder ball pad 12, and a solder ball 51 was formed on the solder ball pad 12 by solder reflow to obtain the semiconductor device 100.

（比較例２）
比較例２で用いる多層回路配線基板１０と半導体集積回路素子３０は実施例１および比較例１と同様のものを用いた。
また、スティフナー２０の外形は４０×４０mm、開口部５２の内周は２５×２５mmとした。
厚さは５００μｍ、材質はＣｕとした。
開口部５２の角部５４には、直径４ｍｍの円形の切り欠きを設けた。
比較例２も実施例１、比較例１と同様に多層回路配線基板１０にスティフナー２０を貼り合わせた後、半導体集積回路素子３０をはんだ接合させ、半導体集積回路素子３０と多層回路配線基板１０との間にアンダーフィル樹脂４１を充填、硬化させた。
さらに、はんだボール用パッド１２上のソルダーレジスト開口部にはんだ球を載置し、はんだリフローにてはんだボール用パッド１２上にはんだボール５１を形成して、半導体装置１００を得た。 (Comparative Example 2)
The multilayer circuit wiring board 10 and the semiconductor integrated circuit element 30 used in Comparative Example 2 were the same as those in Example 1 and Comparative Example 1.
The outer shape of the stiffener 20 was 40 × 40 mm, and the inner periphery of the opening 52 was 25 × 25 mm.
The thickness was 500 μm and the material was Cu.
The corner portion 54 of the opening 52 was provided with a circular cutout having a diameter of 4 mm.
In the second comparative example, the stiffener 20 is bonded to the multilayer circuit wiring board 10 and the semiconductor integrated circuit element 30 is soldered to the semiconductor integrated circuit element 30 and the multilayer circuit wiring board 10. Underfill resin 41 was filled and cured.
Furthermore, a solder ball was placed in the solder resist opening on the solder ball pad 12, and a solder ball 51 was formed on the solder ball pad 12 by solder reflow to obtain the semiconductor device 100.

Figure 0004894347
Figure 0004894347

表１は、実施例、比較例１、比較例２におけるはんだバンプ接続不良数、半導体素子（半導体集積回路素子３０）の割れの有無、Ｌｏｗ−ｋ膜の破壊の有無、基板（多層回路配線基板１０）の反り量の測定値を示す。
表１に示すように、比較例１に示すスティフナー２０を用いた半導体装置１００では、ハンダバンプの接続不良、半導体集積回路素子３０の割れ、Ｌｏｗ−ｋ膜の破壊が発生し、比較例２のスティフナー２０を用いた場合は、ハンダバンプの接続不良、Ｌｏｗ−ｋ膜の破壊が発生しが発生した。
これに対して、実施例では、接続不良、半導体集積回路素子３０の割れ、Ｌｏｗ−ｋ膜の破壊が無く、多層回路配線基板１０の補強効果を有することが可能となるため、基板の反りの初期値からの増加量も比較例１、２に比べて抑制させることができた。 Table 1 shows the number of defective solder bump connections in Examples, Comparative Examples 1 and 2, the presence or absence of cracks in the semiconductor element (semiconductor integrated circuit element 30), the presence or absence of destruction of the Low-k film, and the substrate (multilayer circuit wiring board) The measured value of the warpage amount of 10) is shown.
As shown in Table 1, in the semiconductor device 100 using the stiffener 20 shown in the comparative example 1, poor solder bump connection, cracking of the semiconductor integrated circuit element 30, and destruction of the low-k film occurred, and the stiffener of the comparative example 2 When No. 20 was used, solder bump connection failure and low-k film destruction occurred.
On the other hand, in the embodiment, there is no connection failure, cracking of the semiconductor integrated circuit element 30 and destruction of the low-k film, and the multilayer circuit wiring board 10 can have a reinforcing effect. The increase from the initial value could also be suppressed compared to Comparative Examples 1 and 2.

本実施の形態の半導体集積回路素子搭載用基板２の断面図である。It is sectional drawing of the semiconductor integrated circuit element mounting board | substrate 2 of this Embodiment. 本実施の形態の半導体装置１００の断面図である。It is sectional drawing of the semiconductor device 100 of this Embodiment. スティフナー２０の平面図である。3 is a plan view of a stiffener 20. FIG.

符号の説明Explanation of symbols

２……半導体集積回路素子搭載用基板、１０……多層回路配線基板、１１……電極バンプ、１２……はんだボール用パッド、１３、１４……ソルダーレジスト、１５……配線層、１６……絶縁層、２０……スティフナー、２１……接着剤層、３０……半導体集積回路素子、４０……はんだバンプ、４１……アンダーフィル樹脂、５１……はんだボール、５６……スリット、Ｗ……スリット５６の幅、Ｌ１……スリット５６の長さ、Ｌ２……スリット５６の他端とスティフナー２０の角部５０との距離、６０……放熱板、１００……半導体装置。
2 ... Semiconductor integrated circuit element mounting substrate, 10 ... Multi-layer circuit wiring board, 11 ... Electrode bump, 12 ... Solder ball pad, 13, 14 ... Solder resist, 15 ... Wiring layer, 16 ... Insulating layer, 20 ... Stiffener, 21 ... Adhesive layer, 30 ... Semiconductor integrated circuit element, 40 ... Solder bump, 41 ... Underfill resin, 51 ... Solder ball, 56 ... Slit, W ... The width of the slit 56, L1... The length of the slit 56, L2... The distance between the other end of the slit 56 and the corner 50 of the stiffener 20, 60.

Claims (7)

厚さ方向の一方の面が半導体集積回路素子を搭載するための搭載面として形成された多層回路配線基板と、
前記搭載面に接着され４つの角部を有する矩形板状のスティフナーとを備え、
前記スティフナーには、前記半導体集積回路素子を収納可能な矩形状の開口部が、その開口部を構成する縁の４辺を前記スティフナーの４辺に平行させて形成されている半導体集積回路素子搭載用基板であって、
前記開口部の各角部と前記スティフナーの対応する各角部にわたり延在するスリットが設けられ、
前記スリットの延在方向の一端は前記開口部に開放状に形成され、他端は前記スティフナーの対応する角部の近傍に位置し、
前記スリットの延在方向と直交する方向における前記スリットの幅は前記スリットの延在方向の長さよりも小さい寸法で形成され、
前記スリットは前記幅が１ｍｍ以上３ｍｍ以下の寸法で形成され、
前記スリットの他端とこのスリットに対応する前記スティフナーの角部との距離が０．５ｍｍ以上５ｍｍ以下であり、
前記搭載面には前記半導体集積回路素子と接続するための電極バンプが形成され、
前記スティフナーの厚さは、前記半導体集積回路素子の厚さと前記電極バンプの高さとの和と等しい、
ことを特徴とする半導体集積回路素子搭載用基板。 A multilayer circuit wiring board in which one surface in the thickness direction is formed as a mounting surface for mounting a semiconductor integrated circuit element;
A rectangular plate-like stiffener bonded to the mounting surface and having four corners;
Mounted on the stiffener is a semiconductor integrated circuit element in which a rectangular opening capable of accommodating the semiconductor integrated circuit element is formed with four sides of the edge constituting the opening parallel to the four sides of the stiffener Substrate for
Slits extending over each corner of the opening and corresponding corner of the stiffener are provided,
One end in the extending direction of the slit is formed open in the opening, and the other end is located near the corresponding corner of the stiffener,
The width of the slit in the direction perpendicular to the extending direction of the slit is formed with a dimension smaller than the length in the extending direction of the slit ,
The slit is formed with a width of 1 mm or more and 3 mm or less,
The distance between the other end of the slit and the corner of the stiffener corresponding to the slit is 0.5 mm or more and 5 mm or less,
Electrode bumps for connecting to the semiconductor integrated circuit element are formed on the mounting surface,
The thickness of the stiffener is equal to the sum of the thickness of the semiconductor integrated circuit element and the height of the electrode bump.
A substrate for mounting a semiconductor integrated circuit element. 前記多層回路配線基板は、絶縁性フィルムと、前記絶縁性フィルムの厚さ方向の両面に積層された配線層とを含んで構成されていることを特徴とする請求項１記載の半導体集積回路素子搭載用基板。   2. The semiconductor integrated circuit device according to claim 1, wherein the multilayer circuit wiring board includes an insulating film and a wiring layer laminated on both surfaces of the insulating film in the thickness direction. Mounting board. 前記開口部の角部とこの角部に対応する前記スティフナーの角部との間を結ぶ仮想線上に前記開口部の中心が位置していることを特徴とする請求項１記載の半導体集積回路素子搭載用基板。   2. The semiconductor integrated circuit device according to claim 1, wherein the center of the opening is located on a virtual line connecting the corner of the opening and the corner of the stiffener corresponding to the corner. Mounting board. 前記多層回路配線基板の厚さは０．０５ｍｍ以上０．５ｍｍ以下であることを特徴とする請求項１記載の半導体集積回路素子搭載用基板。   2. The substrate for mounting a semiconductor integrated circuit element according to claim 1, wherein the multilayer circuit wiring board has a thickness of 0.05 mm to 0.5 mm. 請求項１乃至４に何れか１項記載の半導体集積回路素子搭載用基板の前記搭載面上で前記開口部の内側に前記半導体集積回路素子が搭載され、前記半導体集積回路素子は導電部を介して前記多層回路配線基板と電気的に接続された半導体装置であって、前記半導体集積回路素子は低誘電率材料を絶縁膜として用いたものであることを特徴とする半導体装置。 The inside of the opening on the said mounting surface of the semiconductor integrated circuit device mounting board according to any one of the claims 1 to 4 semiconductor integrated circuit device is mounted, the semiconductor integrated circuit device through the conductive portion A semiconductor device electrically connected to the multilayer circuit wiring board, wherein the semiconductor integrated circuit element uses a low dielectric constant material as an insulating film. 前記導電部は、前記半導体集積回路素子が前記搭載面に臨む箇所に設けられたはんだバンプと、前記搭載面が前記半導体集積回路素子に臨む箇所に設けられた電極パッドとがはんだ接合されることで構成されていることを特徴とする請求項５記載の半導体装置。 In the conductive portion, a solder bump provided at a position where the semiconductor integrated circuit element faces the mounting surface and an electrode pad provided at a position where the mounting surface faces the semiconductor integrated circuit element are soldered. The semiconductor device according to claim 5, comprising: 厚さ方向の一方の面が半導体集積回路素子を搭載するための搭載面として形成された多層回路配線基板と、
前記搭載面に接着され４つの角部を有する外形が４０ｍｍ×４０ｍｍの矩形板状のスティフナーとを備え、
前記スティフナーには、前記半導体集積回路素子を収納可能な２５ｍｍ×２５ｍｍの矩形状の開口部が、その開口部を構成する縁の４辺を前記スティフナーの４辺に平行させて形成されている半導体集積回路素子搭載用基板であって、
前記開口部の各角部と前記スティフナーの対応する各角部にわたり延在するスリットが設けられ、
前記スリットの延在方向の一端は前記開口部に開放状に形成され、他端は前記スティフナーの対応する角部の近傍に位置し、
前記スリットの延在方向と直交する方向における前記スリットの幅は前記スリットの延在方向の長さよりも小さい寸法で形成され、
前記多層回路配線基板は、絶縁性フィルムと、前記絶縁性フィルムの厚さ方向の両面に積層された配線層とを含んで構成され、
前記スリットは前記幅が１ｍｍ以上３ｍｍ以下の寸法で形成され、
前記開口部の角部とこの角部に対応する前記スティフナーの角部との間を結ぶ仮想線上に前記開口部の中心が位置し、
前記スリットの他端とこのスリットに対応する前記スティフナーの角部との距離が０．５ｍｍ以上５ｍｍ以下であり、
前記多層回路配線基板の厚さは０．０５ｍｍ以上０．５ｍｍ以下であり、
前記搭載面には前記半導体集積回路素子と接続するための電極バンプが形成され、
前記スティフナーの厚さは、前記半導体集積回路素子の厚さと前記電極バンプの高さとの和と等しい、
ことを特徴とする半導体集積回路素子搭載用基板。 A multilayer circuit wiring board in which one surface in the thickness direction is formed as a mounting surface for mounting a semiconductor integrated circuit element;
A rectangular plate-shaped stiffener having an outer shape of 40 mm × 40 mm bonded to the mounting surface and having four corners;
In the stiffener, a 25 mm × 25 mm rectangular opening that can accommodate the semiconductor integrated circuit element is formed with four sides of the edge constituting the opening parallel to the four sides of the stiffener. A substrate for mounting an integrated circuit element,
Slits extending over each corner of the opening and corresponding corner of the stiffener are provided,
One end in the extending direction of the slit is formed open in the opening, and the other end is located near the corresponding corner of the stiffener,
The width of the slit in the direction perpendicular to the extending direction of the slit is formed with a dimension smaller than the length in the extending direction of the slit,
The multilayer circuit wiring board includes an insulating film, and a wiring layer laminated on both surfaces in the thickness direction of the insulating film,
The slit is formed with a width of 1 mm or more and 3 mm or less,
The center of the opening is located on an imaginary line connecting the corner of the opening and the corner of the stiffener corresponding to the corner,
The distance between the other end of the slit and the corner of the stiffener corresponding to the slit is 0.5 mm or more and 5 mm or less,
The multilayer circuit wiring board has a thickness of 0.05 mm or more and 0.5 mm or less,
Electrode bumps for connecting to the semiconductor integrated circuit element are formed on the mounting surface,
The thickness of the stiffener is equal to the sum of the thickness of the semiconductor integrated circuit element and the height of the electrode bump.
A substrate for mounting a semiconductor integrated circuit element.
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