JP4878813B2 - Semiconductor mounting equipment - Google Patents

Semiconductor mounting equipment Download PDF

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Publication number
JP4878813B2
JP4878813B2 JP2005322965A JP2005322965A JP4878813B2 JP 4878813 B2 JP4878813 B2 JP 4878813B2 JP 2005322965 A JP2005322965 A JP 2005322965A JP 2005322965 A JP2005322965 A JP 2005322965A JP 4878813 B2 JP4878813 B2 JP 4878813B2
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Prior art keywords
semiconductor chip
substrate
semiconductor
central portion
wiring board
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JP2007134356A (en
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友明 黒石
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Wire Bonding (AREA)

Description

本発明はプリント配線基板の上に半導体チップをフリップチップにて実装した半導体実装装置に関するものである。   The present invention relates to a semiconductor mounting apparatus in which a semiconductor chip is mounted on a printed wiring board by flip chip.

プリント配線基板と半導体チップとを電気接続する実装工法として、ワイヤーボンディング実装、フリップチップ実装などがある。フリップチップ実装では、図６（ｂ）に示すように、半導体チップ１の片面に形成されたパッドにバンプ２を形成し、このパンプ２が設けられた側を、図６（ａ）に示すように、プリント配線基板３の側に向けてバンプ２をプリント配線基板３のパッドに当接させた状態で、加熱すると共に超音波振動を加えて半導体チップ１とプリント配線基板３とをパンプ２を介して連結して電気接続し、さらに、半導体チップ１とプリント配線基板３との間に封止樹脂４を充填して、この封止樹脂４を硬化させてバンプ２による電気接続部分に水分などが侵入しないように処理されている。   As a mounting method for electrically connecting a printed wiring board and a semiconductor chip, there are wire bonding mounting and flip chip mounting. In flip chip mounting, as shown in FIG. 6B, bumps 2 are formed on pads formed on one side of the semiconductor chip 1, and the side on which the bumps 2 are provided is shown in FIG. 6A. In addition, with the bumps 2 being in contact with the pads of the printed wiring board 3 toward the printed wiring board 3 side, the semiconductor chip 1 and the printed wiring board 3 are pumped 2 by heating and applying ultrasonic vibration. Further, the sealing resin 4 is filled between the semiconductor chip 1 and the printed wiring board 3, and the sealing resin 4 is cured to cause moisture or the like in the electrical connection portion by the bumps 2. Has been processed to prevent intrusion.

なお、バンプ２は、図６（ｂ）に示すように半導体チップ１の片面の中央部５を除いてほぼ全面に形成されたものの他に、図７に示すように中央部５とこの中央部５を取り囲むように外周部６にもバンプ２を形成したものがある。何れの場合にも、半導体チップ１とプリント配線基板３との対向面の全体に封止樹脂４が充填されている。
特開平９−２８９２２１号公報 松下電工技報（２００４年２月号）第９頁〜第１６頁「半導体封止材料の技術動向」 The bump 2 is formed on almost the entire surface except for the central portion 5 on one side of the semiconductor chip 1 as shown in FIG. 6B, and also has a central portion 5 and this central portion as shown in FIG. Some of the outer peripheral portions 6 have bumps 2 formed so as to surround 5. In either case, the entire facing surface between the semiconductor chip 1 and the printed wiring board 3 is filled with the sealing resin 4.
JP-A-9-289221 Matsushita Electric Works Technical Report (February 2004 issue), page 9 to page 16, "Technological Trend of Semiconductor Encapsulation Materials"

しかし、従来の半導体実装装置では、半導体チップ１の基板１ａに図６（ａ）に仮想線で示した方向に反りが発生した場合には、半導体チップ１の特に最外周のバンプ２に大きな応力が作用し、半導体チップ１とプリント配線基板３との電気接続を維持できなくなる問題がある。特に、半導体チップ１が薄い場合に反りによる応力の発生が著しい。   However, in the conventional semiconductor mounting apparatus, when the substrate 1a of the semiconductor chip 1 is warped in the direction indicated by the phantom line in FIG. 6A, a large stress is applied to the bump 2 on the outermost periphery of the semiconductor chip 1 in particular. This causes a problem that electrical connection between the semiconductor chip 1 and the printed wiring board 3 cannot be maintained. In particular, when the semiconductor chip 1 is thin, the generation of stress due to warping is remarkable.

本発明は半導体チップ１の基板１ａに反りが発生した場合であっても、従来に比べて、長期の電気接続の信頼性の向上を期待できる半導体実装装置を提供することを目的とする。   An object of the present invention is to provide a semiconductor mounting apparatus that can be expected to improve the reliability of electrical connection over a long period of time compared to the conventional case even when the substrate 1a of the semiconductor chip 1 is warped.

本発明の請求項１記載の半導体実装装置は、半導体チップを基板に実装した半導体実装装置であって、前記半導体チップの前記基板との対向面に形成されたバンプで前記半導体チップと前記基板とを電気接続するとともに、前記半導体チップの前記基板との対向面の中央部に形成されたバンプよりも、半導体チップの前記中央部を取り巻く外周部に形成されたバンプが低いヤング率に形成するとともに、半導体チップの前記中央部と前記基板との間を封止樹脂で封止し、半導体チップの前記中央部を取り巻く外周部と前記基板との間を封止樹脂で封止していないことを特徴とする。 The semiconductor mounting apparatus according to claim 1 of the present invention is a semiconductor mounting apparatus in which a semiconductor chip is mounted on a substrate, and the semiconductor chip and the substrate are formed by bumps formed on a surface of the semiconductor chip facing the substrate. together with electrical connection, than said bumps formed in the central portion of the opposing surfaces of the substrate of the semiconductor chip, with bumps formed on an outer peripheral portion surrounding the central portion of the semiconductor chip is formed on a lower Young's modulus And sealing between the central portion of the semiconductor chip and the substrate with a sealing resin, and sealing between the outer peripheral portion surrounding the central portion of the semiconductor chip and the substrate with the sealing resin. Features.

半導体チップのプリント配線基板との対向面の中央部に形成されたバンプだけでプリント配線基板と電気接続したことによって、半導体チップの外周部にはプリント配線基板との電気接続のためのバンプが設けられていないので、半導体チップの基板が反っても半導体チップとプリント配線基板との電気接続が損なわれない。   Bumps for electrical connection with the printed wiring board are provided on the outer periphery of the semiconductor chip by making electrical connection with the printed wiring board only by the bumps formed at the center of the surface facing the printed wiring board of the semiconductor chip. Therefore, even if the substrate of the semiconductor chip is warped, the electrical connection between the semiconductor chip and the printed wiring board is not impaired.

また、半導体チップのプリント配線基板との対向面に形成されたバンプで半導体チップとプリント配線基板とを電気接続するとともに、半導体チップのプリント配線基板との対向面の中央部に形成されたバンプよりも、半導体チップの前記中央部を取り巻く外周部に形成されたバンプを低いヤング率に形成したことによって、半導体チップの基板が反っても半導体チップの前記中央部を取り巻く外周部に形成されたバンプが、前記反りの応力で伸びることによって電気接続の破損に至る事態の発生を食い止めることができ、半導体チップとプリント配線基板との電気接続が損なわれない。   In addition, the bump formed on the surface facing the printed wiring board of the semiconductor chip electrically connects the semiconductor chip and the printed wiring board, and the bump formed on the central portion of the surface facing the printed wiring board of the semiconductor chip. Also, bumps formed on the outer peripheral portion surrounding the central portion of the semiconductor chip even when the substrate of the semiconductor chip is warped by forming the bump formed on the outer peripheral portion surrounding the central portion of the semiconductor chip with a low Young's modulus. However, it is possible to prevent the occurrence of a situation in which the electrical connection is broken by stretching due to the warping stress, and the electrical connection between the semiconductor chip and the printed wiring board is not impaired.

以下、本発明の各実施の形態を図１〜図５に基づいて説明する。
（実施の形態１）
図１（ａ）（ｂ）は本発明の（実施の形態１）を示す。 Hereinafter, embodiments of the present invention will be described with reference to FIGS.
(Embodiment 1)
1A and 1B show (Embodiment 1) of the present invention.

半導体実装装置は、半導体チップ１とプリント配線基板３とを電気接続して構成されている。
半導体チップ１は、裏面の中央部５に限定してバンプ２ａが形成されており、この中央部５の周りの外周部６にはバンプ２ａが形成されていない。この半導体チップ１をプリント配線基板３の面上の配線パターンのパッドに当接させた状態で、加熱すると共に超音波振動を加えてパンプ２ａを介して半導体チップ１とプリント配線基板３とを連結して電気接続し、さらに、半導体チップ１の中央部５においてプリント配線基板３との間に封止樹脂４ａを充填して、この封止樹脂４ａを硬化させてバンプ２ａによる電気接続部分に水分などが侵入しないように処理されている。 The semiconductor mounting apparatus is configured by electrically connecting a semiconductor chip 1 and a printed wiring board 3.
In the semiconductor chip 1, the bump 2 a is formed only on the central portion 5 on the back surface, and the bump 2 a is not formed on the outer peripheral portion 6 around the central portion 5. In a state where the semiconductor chip 1 is in contact with the pad of the wiring pattern on the surface of the printed wiring board 3, the semiconductor chip 1 and the printed wiring board 3 are connected through the pump 2a by heating and applying ultrasonic vibration. In addition, the sealing resin 4a is filled between the central portion 5 of the semiconductor chip 1 and the printed wiring board 3, and the sealing resin 4a is cured so that moisture is applied to the electrical connection portion by the bumps 2a. It is processed to prevent intrusion.

封止樹脂４ａとしては、プリント配線基板３と半導体チップ１のゆがみ、反りを吸収できるように、半導体チップ１とプリント配線基板３よりヤング率の高い柔軟な樹脂である必要がある。   The sealing resin 4 a needs to be a flexible resin having a higher Young's modulus than the semiconductor chip 1 and the printed wiring board 3 so that the distortion and warpage of the printed wiring board 3 and the semiconductor chip 1 can be absorbed.

好適な封止樹脂としては、例えば、フェノール樹脂、ユリア樹脂、メラミン樹脂、エポキシ樹脂、不飽和ポリエステル樹脂、フタル酸ジアリル樹脂、ポリイミド樹脂、シリコン樹脂、ポリウレタン樹脂等を挙げることが出来る。これらの内でも、ビスフェノール系エポキシ樹脂、フェノールノボラック系エポキシ樹脂、クレゾールノボラック系エポキシ樹脂、ブロム化エポキシ樹脂、脂環式エポキシ樹脂等のエポキシ樹脂が特に好ましい。   Suitable examples of the sealing resin include phenol resin, urea resin, melamine resin, epoxy resin, unsaturated polyester resin, diallyl phthalate resin, polyimide resin, silicon resin, polyurethane resin and the like. Among these, epoxy resins such as bisphenol epoxy resin, phenol novolac epoxy resin, cresol novolac epoxy resin, brominated epoxy resin, and alicyclic epoxy resin are particularly preferable.

本発明において、特に好ましい硬化性樹脂の具体例として、フェノールノボラック型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂を挙げることができる。
半導体チップ１の基板１ａは、図６（ａ）に仮想線で示したように半導体チップ１の基板１ａに反りが発生するが、中央部を樹脂で封止し、無理に反りを防止しておらず、応力が残らないので、長期間安定な接続が確保できる。また、半導体チップ１の中央部５の基板１ａの反り量は、この外周部６の反り量に比べて小さいため、半導体チップ１の中央部５にだけパンプ２ａを設けたこの半導体実装装置では、基板１ａの反りに伴ってバンプ２ａに作用する応力は小さく、電気接続の信頼性が従来例に比べて高い。 In the present invention, specific examples of particularly preferred curable resins include phenol novolac epoxy resins and cresol novolac epoxy resins.
The substrate 1a of the semiconductor chip 1 warps the substrate 1a of the semiconductor chip 1 as indicated by the phantom line in FIG. 6A, but the central portion is sealed with resin to prevent the warp from being forced. Since no stress remains, a long-term stable connection can be secured. Further, since the warpage amount of the substrate 1a in the central portion 5 of the semiconductor chip 1 is smaller than the warpage amount of the outer peripheral portion 6, in this semiconductor mounting apparatus in which the pump 2a is provided only in the central portion 5 of the semiconductor chip 1, The stress acting on the bump 2a with the warp of the substrate 1a is small, and the reliability of electrical connection is higher than in the conventional example.

なお、図１の説明図ではパンプ２ａの数が、図６の場合のバンプ２の総数に比べて少ないが、バンプ２ａの形成位置を基板１ａの中央部５に限定した場合であっても、バンプ２ａのピッチを小さくすることで必要数を中央部５に形成できる。   In the explanatory view of FIG. 1, the number of bumps 2a is smaller than the total number of bumps 2 in the case of FIG. 6, but even when the formation position of the bumps 2a is limited to the central portion 5 of the substrate 1a, The required number can be formed in the central portion 5 by reducing the pitch of the bumps 2a.

また、半導体チップ１の中央部５とは、全体の１／２から１／４の範囲をいう。この領域が小さい方が、接続部分が小さくなり、ひずみによる応力を緩和しやすいが、接続領域が小さくなると、端子間の導通や、端子自身の接続強度が落ち、接続安定性に欠ける。半導体チップの製造プロセスにおいて、内部配線形成することにより、電極部であり、接合部であるバンプ形成部分を中央に集めた。   Further, the central portion 5 of the semiconductor chip 1 refers to a range from 1/2 to 1/4 of the whole. The smaller this region, the smaller the connection portion and the easier to relieve stress due to strain. However, when the connection region becomes smaller, the continuity between the terminals and the connection strength of the terminals themselves are lowered, resulting in poor connection stability. In the semiconductor chip manufacturing process, by forming internal wiring, bump forming portions which are electrode portions and bonding portions are collected in the center.

半導体チップは、薄型のもの、縦横２ｃｍ角で、厚みが０．５ｍｍのものを用いたが、さらに、薄くなると反りが大きくなり、従来のように全体を樹脂モールドすると、応力が残り、安定しない。薄型チップになればなるほど、本発明の効果が顕著である。特に、半導体メモリを用いた薄型のメモリ商品に用いることができる。   The semiconductor chip was thin, 2 cm in length and width, and 0.5 mm in thickness. However, the warpage increases as the thickness becomes thinner, and when the whole is resin-molded, stress remains and is not stable. . The thinner the chip, the more remarkable the effect of the present invention. In particular, it can be used for thin memory products using semiconductor memory.

また、本発明では、中央部のみを封止するので、封止領域が狭く、封止領域で発生する不良が低減できる。
別の変形例として、ヤング率の高いシリコン系樹脂で、半導体チップの下面全体を覆ってもよい。このことにより、半導体チップの反りを無理に抑えないので、応力ひずみが発生せず、長期の安定性が得られる。ヤング率としては、５００ｋｇｆ／ｍｍ２以上程度である。従来のようにヤング率の低い樹脂で全体を封止する場合、半導体チップが変形できず応力が残留した状態で固定されるので、長期の安定な接続性に欠如していたが、本発明では、中央部以外を反らせて、応力を残さないか、または、全体を反らせるので応力を緩和でき、長期の接続安定性が確保できる。 Moreover, in this invention, since only the center part is sealed, the sealing area | region is narrow and the defect which generate | occur | produces in a sealing area | region can be reduced.
As another modification, the entire lower surface of the semiconductor chip may be covered with a silicon-based resin having a high Young's modulus. As a result, the warp of the semiconductor chip is not forcibly suppressed, so that stress distortion does not occur and long-term stability is obtained. The Young's modulus is about 500 kgf / mm 2 or more. When the whole is sealed with a resin having a low Young's modulus as in the conventional case, the semiconductor chip cannot be deformed and is fixed in a state where stress remains, and thus it has lacked long-term stable connectivity. In addition, the stress other than the central portion is warped to leave no stress, or the whole is warped, so that the stress can be relaxed and long-term connection stability can be ensured.

プリント基板と半導体チップとの接続の例を示したが、各種メモリカードなどの半導体装置一般に用いることができる。基板と半導体チップとの接合に用いることができる。以下の実施形態でも同様に応用できる。   Although an example of connection between a printed circuit board and a semiconductor chip has been shown, it can be used in general semiconductor devices such as various memory cards. It can be used for bonding a substrate and a semiconductor chip. The following embodiments can be similarly applied.

（実施の形態２）
図２（ａ）（ｂ）は本発明の（実施の形態２）を示す。
図１の半導体実装装置では、封止樹脂４ａが半導体チップ１の中央部５だけに充填されて硬化していたが、この（実施の形態２）では半導体チップ１の中央部５に封止樹脂４ａを充填し、中央部５を取り巻く外周部６と前記プリント配線基板３との間には封止樹脂４ｂが充填されている。ここで封止樹脂４ｂの硬化した状態でのヤング率は、封止樹脂４ａの硬化した状態でのヤング率よりも低いものを使用した。 (Embodiment 2)
2A and 2B show (Embodiment 2) of the present invention.
In the semiconductor mounting apparatus of FIG. 1, the sealing resin 4 a is filled and cured only in the central portion 5 of the semiconductor chip 1. In this (Embodiment 2), the sealing resin is added to the central portion 5 of the semiconductor chip 1. A space between the outer peripheral portion 6 surrounding the central portion 5 and the printed wiring board 3 is filled with a sealing resin 4b. Here, the Young's modulus in the cured state of the sealing resin 4b was lower than the Young's modulus in the cured state of the sealing resin 4a.

このように半導体チップ１とプリント配線基板３の間にヤング率の異なる封止樹脂４ａ，４ｂを充填したため、（実施の形態１）の図１の場合と同様に基板１ａの反りを抑制でき、応力を緩和する。また、半導体チップ１とプリント配線基板３の間の全部に封止樹脂４ａを充填した場合に比べて、反りを緩やかにすることができる。つまり、実施形態１では、樹脂で覆われた部分とそうでない部分で、半導体チップの局所的な反りが発生するが、この実施形態では、その界面が緩やかになるので、応力の変化が少なくなり、より長期安定化される。   Since the sealing resins 4a and 4b having different Young's moduli are filled between the semiconductor chip 1 and the printed wiring board 3 as described above, the warping of the substrate 1a can be suppressed as in the case of FIG. 1 of (Embodiment 1). Relieve stress. Further, the warpage can be moderated as compared with the case where the entire space between the semiconductor chip 1 and the printed wiring board 3 is filled with the sealing resin 4a. That is, in the first embodiment, the semiconductor chip is locally warped between the portion covered with the resin and the portion not covered with the resin. However, in this embodiment, the interface becomes gentle, and the change in stress is reduced. , More stable for a long time.

ヤング率の異なる樹脂として、同じ種類の樹脂を用いる場合と、異なる樹脂を用いることがでできる。同じ樹脂のヤング率を制御するためには、樹脂に、石英ガラス、アルミナ、マイカ、ジルコニウムシリケート、リチウムシリケートなどの無機物を前記樹脂１００重量部に対して、５０〜３００重量部を配合して調整される。たくさん混入させると、ヤング率が高くなって柔軟になる。一方、樹脂の種類をかえる場合は、ヤング率の低いエポキシ系樹脂と、高いシリコン系樹脂など組み合わせることができる。   As resins having different Young's moduli, the same type of resin can be used, and different resins can be used. In order to control the Young's modulus of the same resin, 50 to 300 parts by weight of inorganic substances such as quartz glass, alumina, mica, zirconium silicate, lithium silicate, etc. are blended in the resin with respect to 100 parts by weight of the resin. Is done. When a lot is mixed, Young's modulus becomes high and becomes flexible. On the other hand, when changing the type of resin, an epoxy resin having a low Young's modulus and a silicon resin having a high Young's modulus can be combined.

（実施の形態３）
図３（ａ）（ｂ）は本発明の（実施の形態３）を示す。
半導体実装装置は、半導体チップ１と前記プリント配線基板とを電気接続して構成されている。 (Embodiment 3)
3A and 3B show (Embodiment 3) of the present invention.
The semiconductor mounting apparatus is configured by electrically connecting the semiconductor chip 1 and the printed wiring board.

半導体チップ１は、基板１ａの裏面の中央部５にバンプ２ａが形成されており、この中央部５の周りの外周部６にはバンプ２ｂが形成されている。ここでバンプ２ｂのヤング率は、バンプ２ａのヤング率よりも低いものを使用した。さらに具体的には、例えばバンプ２ａ，２ｂの材質は同じ場合には、バンプ２ｂの径をバンプ２ａの径よりも小さくしている。１割から数割だけ径を小さくできる。   In the semiconductor chip 1, bumps 2 a are formed on the central portion 5 on the back surface of the substrate 1 a, and bumps 2 b are formed on the outer peripheral portion 6 around the central portion 5. Here, the Young's modulus of the bump 2b is lower than that of the bump 2a. More specifically, for example, when the material of the bumps 2a and 2b is the same, the diameter of the bump 2b is made smaller than the diameter of the bump 2a. The diameter can be reduced by 10 to several percent.

この半導体チップ１をプリント配線基板３の面上の配線パターンのパッドに当接させた状態で、加熱すると共に超音波振動を加えてパンプ２ａ，２ｂを介して半導体チップ１とプリント配線基板３とを連結して電気接続し、さらに、半導体チップ１の中央部５においてプリント配線基板３との間に封止樹脂４ａを充填して、この封止樹脂４ａを硬化させてバンプ２ａによる電気接続部分に水分などが侵入しないように処理されている。   In a state where the semiconductor chip 1 is in contact with the pad of the wiring pattern on the surface of the printed wiring board 3, the semiconductor chip 1 and the printed wiring board 3 are heated via the pumps 2a and 2b by heating and applying ultrasonic vibration. Further, the sealing resin 4a is filled between the central portion 5 of the semiconductor chip 1 and the printed wiring board 3, and the sealing resin 4a is cured to be electrically connected by the bumps 2a. It is treated so that moisture does not enter.

バンプのヤング率を変えるには、（１）金バンプとインジウム系の合金バンプの組み合わせや、（２）金、白金、銀、銅、ニッケル、または、これらの合金のバンプとインジウム、鉛、スズ、ビスマス、または、これらの合金のバンプの組み合わせ、（３）半田材料の組成を変化させたものの組み合わせ、つまり、Ｓｎ−（２〜５ｗｔ％）Ａｇ−（０〜１ｗｔ％）Ｃｕ−（０〜１ｗｔ％）Ｂｉのバンプと、Ｓｎ−（５０〜９０ｗｔ％）Ｂｉのバンプの組み合わせを用いることができる。なお、これらに限られるわけではない。   To change the Young's modulus of the bump, (1) a combination of gold bump and indium alloy bump, or (2) gold, platinum, silver, copper, nickel, or a bump of these alloys and indium, lead, tin , Bismuth, or a combination of these alloy bumps, (3) a combination of solder material compositions changed, that is, Sn- (2-5 wt%) Ag- (0-1 wt%) Cu- (0 A combination of 1 wt%) Bi bumps and Sn- (50 to 90 wt%) Bi bumps can be used. However, the present invention is not limited to these.

（実施の形態４）
図４（ａ）（ｂ）は本発明の（実施の形態４）を示す。
図３の半導体実装装置では、封止樹脂４ａが半導体チップ１の中央部５だけに充填されて硬化していたが、この（実施の形態４）では半導体チップ１の中央部５に封止樹脂４ａを充填し、中央部５を取り巻く外周部６と前記プリント配線基板３との間には封止樹脂４ｂが充填されている。ここで封止樹脂４ｂの硬化した状態でのヤング率は、封止樹脂４ａの硬化した状態でのヤング率よりも低いものを使用した。 (Embodiment 4)
4A and 4B show (Embodiment 4) of the present invention.
In the semiconductor mounting apparatus of FIG. 3, the sealing resin 4a is filled and cured only in the central portion 5 of the semiconductor chip 1, but in this (Embodiment 4), the sealing resin is added to the central portion 5 of the semiconductor chip 1. A space between the outer peripheral portion 6 surrounding the central portion 5 and the printed wiring board 3 is filled with a sealing resin 4b. Here, the Young's modulus in the cured state of the sealing resin 4b was lower than the Young's modulus in the cured state of the sealing resin 4a.

このように半導体チップ１とプリント配線基板３の間にヤング率の異なる封止樹脂４ａ，４ｂを充填したため、（実施の形態３）と比べて、封止により接合安定性がある。つまり、外部からの物理的破壊、水分などの環境的影響を受けず、かつ、半導体チップの応力を緩和した状態での接続ができ、長期安定な接続ができる。   Since the sealing resins 4a and 4b having different Young's moduli are filled between the semiconductor chip 1 and the printed wiring board 3 as described above, the bonding stability is achieved by sealing as compared with (Embodiment 3). In other words, the connection can be made in a state in which the stress of the semiconductor chip is relaxed without being affected by external physical damage, moisture, or the like, and a long-term stable connection can be made.

（実施の形態５）
図５（ａ）（ｂ）は本発明の（実施の形態５）を示す。
（実施の形態１）を示す図１（ｂ）では、バンプ２ａは千鳥足配置されていたが、図５ではバンプ２ａが、半導体チップ１の真ん中を中心とした同心円状に配置されている点だけが異なっており、（実施の形態１）と比べて、バンプ部分とそれ以外のチップ部分の反りによる応力分布が均質になっている。つまり、四角形の場合、コーナー部分と辺の部分で応力に差があり、応力分布がひずんでいるため、長期の安定した接続ができない。本発明の同心円状の場合、円なので、円周辺の応力分布は均質である。 (Embodiment 5)
FIGS. 5A and 5B show (Embodiment 5) of the present invention.
In FIG. 1B showing (Embodiment 1), the bumps 2a are arranged in a staggered manner, but in FIG. 5, only the bumps 2a are arranged concentrically around the center of the semiconductor chip 1. As compared with the first embodiment, the stress distribution due to the warp of the bump portion and the other chip portion is uniform. That is, in the case of a quadrangle, there is a difference in stress between the corner portion and the side portion, and the stress distribution is distorted. In the case of the concentric circle of the present invention, since it is a circle, the stress distribution around the circle is uniform.

なお、（実施の形態２）〜（実施の形態４）においても、バンプ２ａ，２ｂを同心円状に配置することによって同様の効果を期待できる。
なお、同心円状に限定されず、対称性があり、応力分布が不均質にならなければよい。楕円であってもよい。同心円状の場合がもっともよい。 In (Embodiment 2) to (Embodiment 4), the same effect can be expected by arranging the bumps 2a and 2b concentrically.
In addition, it is not limited to a concentric circle shape, It is good if it is symmetrical and stress distribution does not become inhomogeneous. It may be oval. Concentric circles are best.

半導体チップの反りに伴うプリント配線基板との電気接続の信頼性を高めることができ、この半導体実装装置を搭載した各種電子機器の信頼性の向上を期待できる。   The reliability of the electrical connection with the printed wiring board accompanying the warp of the semiconductor chip can be improved, and the improvement of the reliability of various electronic devices equipped with this semiconductor mounting apparatus can be expected.

本発明の（実施の形態１）の半導体実装装置の側面図とＡ−Ａ断面図Side view and AA sectional view of the semiconductor mounting apparatus of (Embodiment 1) of the present invention 本発明の（実施の形態２）の半導体実装装置の中央断面図とＢ−Ｂ断面図Central sectional view and BB sectional view of the semiconductor mounting apparatus of (Embodiment 2) of the present invention 本発明の（実施の形態３）の半導体実装装置の中央断面図とＣ−Ｃ断面図Central sectional view and CC sectional view of the semiconductor mounting apparatus of (Embodiment 3) of the present invention 本発明の（実施の形態４）の半導体実装装置の中央断面図とＤ−Ｄ断面図Central sectional view and DD sectional view of the semiconductor mounting device of (Embodiment 4) of the present invention 本発明の（実施の形態５）の半導体実装装置の側面図とＥ−Ｅ断面図Side view and EE cross-sectional view of the semiconductor mounting device of (Embodiment 5) of the present invention 従来例の半導体実装装置の側面図とＦ−Ｆ断面図Side view and FF sectional view of a conventional semiconductor mounting device 別の従来例の半導体実装装置の半導体チップの底面図Bottom view of semiconductor chip of another conventional semiconductor mounting device

符号の説明Explanation of symbols

１ 半導体チップ
１ａ 半導体チップ１の基板
２ａ，２ｂ バンプ
３ プリント配線基板
４ａ，４ｂ 封止樹脂
５ 半導体チップ１の中央部
６ 半導体チップ１の外周部 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1a Substrate 2a, 2b of semiconductor chip 1 Bump 3 Printed wiring board 4a, 4b Sealing resin 5 Central part 6 of semiconductor chip 1 Outer peripheral part of semiconductor chip 1

Claims (4)

半導体チップを基板に実装した半導体実装装置であって、
前記半導体チップの前記基板との対向面に形成されたバンプで前記半導体チップと前記基板とを電気接続するとともに、
前記半導体チップの前記基板との対向面の中央部に形成されたバンプよりも、半導体チップの前記中央部を取り巻く外周部に形成されたバンプを低いヤング率に形成するとともに、
半導体チップの前記中央部と前記基板との間を封止樹脂で封止し、半導体チップの前記中央部を取り巻く外周部と前記基板との間を封止樹脂で封止していない
半導体実装装置。 A semiconductor mounting device in which a semiconductor chip is mounted on a substrate,
While electrically connecting the semiconductor chip and the substrate with bumps formed on the surface of the semiconductor chip facing the substrate,
The bump formed on the outer peripheral portion surrounding the central portion of the semiconductor chip is formed with a lower Young's modulus than the bump formed on the central portion of the surface of the semiconductor chip facing the substrate .
Between the central part of the semiconductor chip and the substrate is sealed with a sealing resin, and between the outer peripheral part surrounding the central part of the semiconductor chip and the substrate is not sealed with a sealing resin <br / > Semiconductor mounting equipment. 前記半導体チップの前記基板との対向面の中央部に形成されたバンプと、半導体チップの前記中央部を取り巻く外周部に形成されたバンプとが異なる材料で形成した
請求項１記載の半導体実装装置。 2. The semiconductor mounting apparatus according to claim 1, wherein a bump formed on a central portion of the surface of the semiconductor chip facing the substrate and a bump formed on an outer peripheral portion surrounding the central portion of the semiconductor chip are formed of different materials. . 前記異なる材料が、金とインジウム系の合金である
請求項２記載の半導体実装装置。 The semiconductor mounting apparatus according to claim 2, wherein the different material is an alloy of gold and indium. 前記異なる材料が、半田材料の組成が異なるものである
請求項２記載の半導体実装装置。 The semiconductor mounting apparatus according to claim 2, wherein the different materials have different solder material compositions.
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