JP4843978B2 - Method for forming thin film transistor - Google Patents
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- JP4843978B2 JP4843978B2 JP2005091478A JP2005091478A JP4843978B2 JP 4843978 B2 JP4843978 B2 JP 4843978B2 JP 2005091478 A JP2005091478 A JP 2005091478A JP 2005091478 A JP2005091478 A JP 2005091478A JP 4843978 B2 JP4843978 B2 JP 4843978B2
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Description
本発明は薄膜トランジスタの形成方法に関するものである。 The present invention relates to a method for forming a thin film transistor.
近年，フレキシブル化，軽量化，低コスト化などの観点から，湿式プロセスによる薄膜トランジスタの研究が盛んであり、有機ＥＬや電子ペーパーなどの駆動回路や電子タグなどへの応用が期待されている。湿式プロセスとしては、オフセット印刷によりレジストインキや遮光性インキを塗布し半導体パターンや回路基板を形成する方法（例えば、特許文献１）、スクリーン印刷やロールコーターにより導電ペーストを印刷し各種電極を形成する方法（例えば、特許文献２）、インクジェットにより金属微粒子溶液を塗布し各種電極を形成する方法（例えば、特許文献３）等が挙げられる。 In recent years, from the viewpoints of flexibility, weight reduction, cost reduction, etc., research on thin film transistors by a wet process has been active, and application to driving circuits such as organic EL and electronic paper, electronic tags, and the like is expected. As a wet process, a resist pattern or a light-shielding ink is applied by offset printing to form a semiconductor pattern or circuit board (for example, Patent Document 1), and a conductive paste is printed by screen printing or a roll coater to form various electrodes. Examples thereof include a method (for example, Patent Document 2) and a method for forming various electrodes by applying a metal fine particle solution by inkjet (for example, Patent Document 3).
以下に公知の文献を示す。
薄膜トランジスタの湿式プロセスにおいては、半導体層として溶媒に可溶な有機半導体が用いられることが多いが、一般に有機半導体はキャリア移動度が小さく、溶媒に可溶なタイプはとりわけ小さい。よって、実用上十分な動作周波数を得るにはソース・ドレイン電極間隔（チャネル長）をできるだけ短くする必要があり、いかにチャネル長を短く形成するかが技術的課題の一つとなっている。 In a wet process of a thin film transistor, an organic semiconductor that is soluble in a solvent is often used as a semiconductor layer. In general, an organic semiconductor has a low carrier mobility, and a type that is soluble in a solvent is particularly small. Therefore, in order to obtain a practically sufficient operating frequency, it is necessary to shorten the distance between the source and drain electrodes (channel length) as much as possible, and how to shorten the channel length is one of the technical problems.
ソース・ドレイン電極の形成方法としては、例えば、金属粉等の導電材が溶剤に分散した電極形成材を印刷する方法が挙げられるが、チャネル長を短くしようとするほど、電極形成材の印刷後の流動によるソース・ドレイン電極の短絡が生じやすくなる。印刷後の流動は電極形成材の高粘度化により抑制されるが、所望のチャネル長がある程度以下となると、チャネル形成と印刷適性を両立することは困難である。例えば、インクジェットにおいてはインクジェット可能なインク粘度範囲ではこれに対応できない。また、スクリーン印刷においても、ペーストを高粘度化すると印刷後のレベリング不足が生じやすくなり、レベリング不足によりスクリーンメッシュの格子状パターンが印刷後に残存してしまう問題が生じる。本発明はこれらの問題点を鑑みてなされたものであり、チャネル長が短い薄膜トランジスタの形成方法を提供することを課題とする。 Examples of the method for forming the source / drain electrode include a method of printing an electrode forming material in which a conductive material such as metal powder is dispersed in a solvent. The source / drain electrodes are likely to be short-circuited by the flow of. Although the flow after printing is suppressed by increasing the viscosity of the electrode forming material, it is difficult to achieve both channel formation and printability when the desired channel length is below a certain level. For example, in the case of ink jetting, the ink viscosity range that can be used for ink jetting cannot cope with this. Also in screen printing, if the viscosity of the paste is increased, insufficient leveling after printing is likely to occur, and there is a problem that the grid pattern of the screen mesh remains after printing due to insufficient leveling. The present invention has been made in view of these problems, and an object thereof is to provide a method for forming a thin film transistor having a short channel length.
本発明は上記課題を考慮してなされたもので、請求項１の発明は、ＵＶ光透過性の転写型用基板に、ＵＶ光透過性と硬化後のUV硬化性導電材料に対して剥離性を有する凹版底面材と、遮光性と前記硬化後のUV硬化性導電材料に対して離型性を有する凹版凸部材が積層された構成であり、凹部が少なくともソース・ドレイン電極のパターンを有する凹版転写型の版面全体に前記UV硬化性導電材料を塗布し乾燥した後、転写型用基板側からＵＶ光を照射することで凹部の導電材を硬化させ、続いて未硬化部分の導電材を現像除去した後、薄膜トランジスタ用基材を接着剤を介在させた状態で前記凹版転写型に重ね合わせてから、前記薄膜トランジスタ用基材を前記接着剤とともに凹版転写型から分離して、導電材を接着剤を介して薄膜トランジスタ用基材に転写させてソース・ドレイン電極を形成する工程を含むことを特徴とする薄膜トランジスタの形成方法である。
The present invention has been made in consideration of the above-mentioned problems. The invention of claim 1 is directed to a UV light transmission transfer mold substrate, UV light transmission and releasability from a cured UV curable conductive material. And an intaglio plate having a light-shielding property and an intaglio convex member having releasability with respect to the cured UV curable conductive material, wherein the concave portion has at least a pattern of the source / drain electrodes. After the UV curable conductive material is applied to the entire transfer mold plate and dried, the conductive material in the recesses is cured by irradiating UV light from the transfer mold substrate side, and then the uncured conductive material is developed. After the removal, the thin film transistor substrate is overlaid on the intaglio transfer mold with an adhesive interposed therebetween, and then the thin film transistor substrate is separated from the intaglio transfer mold together with the adhesive, and the conductive material is bonded to the adhesive. Through thin film transistor By transferring to the substrate a thin film transistor forming method which comprises a step of forming the source and drain electrodes.
請求項２の発明は、前記接着剤が絶縁性を有し、前記薄膜トランジスタ用基材としてゲ
ート電極が形成されたものを用いることを特徴とする請求項１に記載の薄膜トランジ
スタの形成方法である。
The invention according to claim 2 is the method for forming a thin film transistor according to claim 1 , wherein the adhesive has an insulating property, and a gate electrode is formed as the thin film transistor base material.
請求項３の発明は、前記薄膜トランジスタ用基材としてゲート電極とゲート絶縁膜が形
成されたものを用いることを特徴とする請求項１に記載の薄膜トランジスタの形成方
法である。
A third aspect of the present invention is the method of forming a thin film transistor according to the first aspect, wherein the thin film transistor base material is a substrate on which a gate electrode and a gate insulating film are formed.
本発明の薄膜トランジスタの形成方法は、凹部がソース・ドレイン電極のパターンを有する凹版転写型の凹部に導電材を充填し硬化させた後、硬化した導電材を薄膜トランジスタ用基材に転写する工程を含むので、従来の印刷法による流動性と高粘度化による不具合が解消され、よりチャネル長を短くソース・ドレイン電極を形成することができる。また、導電材の充填および硬化を、該凹版転写型の版面全体に塗布した導電材の露光現像により行うことで、導電材が精度良く充填され、より高精度でソース・ドレイン電極を形成することができる。また、該薄膜トランジスタ用基材として、ゲート電極あるいはゲート電極とゲート絶縁膜が予め形成された薄膜トランジスタ用基材を用いることで、ボトムゲート型薄膜トランジスタも形成することもできる。 The method for forming a thin film transistor of the present invention includes a step of filling an intaglio transfer type recess having a pattern of a source / drain electrode with a conductive material and curing, and then transferring the cured conductive material to a thin film transistor substrate. Therefore, the problems due to the fluidity and high viscosity due to the conventional printing method are eliminated, and the source / drain electrodes can be formed with a shorter channel length. Also, the conductive material is filled and cured by exposure and development of the conductive material applied to the entire plate surface of the intaglio transfer mold, so that the conductive material is filled with high accuracy and the source / drain electrodes can be formed with higher accuracy. Can do. Further, a bottom-gate thin film transistor can also be formed by using a thin film transistor substrate in which a gate electrode or a gate electrode and a gate insulating film are formed in advance as the thin film transistor substrate.
本発明は、凹部が少なくともソース・ドレイン電極のパターンを有する凹版転写型の凹部に導電材を充填し硬化させた後、薄膜トランジスタ用基材を接着剤を介在させた状態で前記凹版転写型に重ね合わせてから、前記薄膜トランジスタ用基材を前記接着剤とともに凹版転写型から分離して、導電材を接着剤を介して薄膜トランジスタ用基材に転写させてソース・ドレイン電極を形成する方法である。 In the present invention, the concave portion of the intaglio transfer mold having at least the pattern of the source / drain electrodes is filled with a conductive material and cured, and then the thin film transistor substrate is overlaid on the intaglio transfer mold with an adhesive interposed therebetween. Then, the thin film transistor base material is separated from the intaglio transfer mold together with the adhesive, and the conductive material is transferred to the thin film transistor base material through the adhesive to form the source / drain electrodes.
本発明では凹版転写型への導電材の充填方法として２種類提示している。 In the present invention, two types of methods for filling the intaglio transfer mold with the conductive material are presented.
第一の充填方法を図１に示す。図１は、本発明の薄膜トランジスタの形成方法の一例を、断面で示した部分説明図である。凹版転写型１１を用意し（図１（ａ））、その版面に導電材２１を塗布し（ｂ）、ドクターで掻きとることで導電材を充填する（ｃ）。続いて凹部に充填された導電材を硬化することで導電材が充填硬化された凹版転写型３１が得られる（ｄ）。 The first filling method is shown in FIG. FIG. 1 is a partial explanatory view showing an example of a method for forming a thin film transistor of the present invention in a cross section. An intaglio transfer mold 11 is prepared (FIG. 1A), a conductive material 21 is applied to the plate surface (b), and the conductive material is filled by scraping with a doctor (c). Subsequently, the intaglio transfer mold 31 in which the conductive material is filled and cured is obtained by curing the conductive material filled in the recesses (d).
凹版転写型１１はフォトリソグラフィーとエッチングを組み合わせるなどの通常用いられる方法で少なくともソース・ドレイン電極の形状を含むパターンを形成したものである。凹版転写型１１の材質としては、特に限定されるものではなく、例えば、ステンレス鋼、燐青銅、ガラスなどの材料が用いられる。また、必要に応じ、硬化後の導電材に対する離型性を付与するため、凹版転写型１１の表面に離型層が設けられる。 The intaglio transfer mold 11 is formed by forming a pattern including at least the shape of the source / drain electrodes by a commonly used method such as a combination of photolithography and etching. The material of the intaglio transfer mold 11 is not particularly limited, and for example, materials such as stainless steel, phosphor bronze, and glass are used. Further, if necessary, a release layer is provided on the surface of the intaglio transfer mold 11 in order to impart release properties to the cured conductive material.
導電材２１は、硬化性を有するものであれば特に限定されるものではなく、Nｉ、Ａｌ、Ｃu、Ａｇ、Ａｕ、カーボン等の微粉体、Ａｇ、Ｃｕ、Ａｕ等のナノ粒子、有機Ａｇ化合物等の導電材を含有する各種熱硬化性あるいは光硬化性導電性ペースト等の公知の材料を用いることができる。 The conductive material 21 is not particularly limited as long as it has curability, fine powders such as Ni, Al, Cu, Ag, Au, and carbon, nanoparticles such as Ag, Cu, and Au, and organic Ag compounds. Well-known materials, such as various thermosetting or photocurable conductive paste containing conductive materials, such as these, can be used.
第二の充填方法を図２に示す。図２は、本発明の薄膜トランジスタの形成方法の他の例を、断面で示した部分説明図である。凹版転写型１２を用意し（図２（ａ））、その版面全体に、ＵＶ硬化性導電材２１を塗布し乾燥する（ｂ）。その後版面と反対の面からＵＶ光を照射（裏面露光）し、凹部の導電材を硬化させた後（ｃ）、未硬化部を現像除去する（ｄ）ことで導電材２２が充填硬化された凹版転写型３２が得られる。裏面露光においてUV硬化性導電材が硬化する深さは裏面露光量により変化する。すなわち、裏面露光量によりUV硬化性導電材が硬化する深さを制御することが可能である。前記第一の充填方法は、凹部の導電材も一部はドクターにより掻きとられてしまうため充填物に膜厚分布が生じやすい。これに対し、この第二の充填方法は充填物の厚み精度が優れており、また、導電材の凹部以外における残存が少ないため、ソース・ドレイン電極をより精度良く形成することが可能である。 A second filling method is shown in FIG. FIG. 2 is a partial explanatory view showing in cross section another example of the method for forming a thin film transistor of the present invention. An intaglio transfer mold 12 is prepared (FIG. 2A), and a UV curable conductive material 21 is applied to the entire plate surface and dried (b). Thereafter, UV light was irradiated from the surface opposite to the plate surface (backside exposure) to cure the conductive material in the concave portion (c), and the uncured portion was developed and removed (d), whereby the conductive material 22 was filled and cured. An intaglio transfer mold 32 is obtained. The depth at which the UV curable conductive material is cured in the back exposure varies depending on the back exposure. That is, the depth at which the UV curable conductive material is cured can be controlled by the back surface exposure amount. In the first filling method, the conductive material in the recesses is partly scraped off by the doctor, so that the film thickness distribution is likely to occur in the filling. On the other hand, the second filling method is excellent in the thickness accuracy of the filling material, and since there is little remaining in the conductive material other than the recesses, the source / drain electrodes can be formed more accurately.
凹版転写型１２は、ＵＶ光透過性の転写型用基板１２１に、ＵＶ光透過性と硬化後の導電材料２２に対して剥離性を有する凹版底面材１２２と、遮光性と前記硬化後の導電材料２２に対して離型性を有する凹版凸部材１２３が積層された構成である。転写型用基板１２１はＵＶ光透過性を有するものであれば特に限定されるものはなく、例えば、ガラス基板が用いられる。凹版底面材１２２は、転写型用基板１２１の全面に形成され、ＵＶ光透過性および硬化後の導電材料に対して剥離性を有するものが用いられる。例えば、各種公知の光重合性アクリルモノマー（例えば、特許文献４の合成例１に開示されている感光性樹脂）と重合開始剤を適当な溶剤に溶かした組成物が用いられ、該組成物を転写型用基板１２１に均一塗布し乾燥した後、ＵＶ硬化することで形成可能である。凹版凸部材１２３は凹版底面材１２２上にパターン形成され、遮光性および硬化後の導電材料に対して離型性を有するものである。例えば、各種公知のカラーフィルタ用ブラックマトリクス用黒色感光性樹脂組成物（例えば、特許文献４の実施例１に記載されているもの）が用いられ、該組成物を凹版底面材１２２上に均一塗布し乾燥した後、パターン露光し現像することで形成可能である。凹版底面材１２２および凹版凸部材の塗布方法は、特に限定されるものではないが、例えば、スピンコートやダイコートが挙げられる。 The intaglio transfer mold 12 includes a UV light transmissive transfer mold substrate 121, a UV light transmissive and intaglio bottom surface material 122 having releasability from the cured conductive material 22, a light shielding property and the cured conductive material. An intaglio convex member 123 having releasability with respect to the material 22 is laminated. The transfer mold substrate 121 is not particularly limited as long as it has UV light transparency, and for example, a glass substrate is used. The intaglio bottom material 122 is formed on the entire surface of the transfer mold substrate 121 and has a UV light transmission property and a releasability with respect to the cured conductive material. For example, a composition in which various known photopolymerizable acrylic monomers (for example, the photosensitive resin disclosed in Synthesis Example 1 of Patent Document 4) and a polymerization initiator are dissolved in an appropriate solvent is used. It can be formed by uniformly applying to the transfer mold substrate 121 and drying, followed by UV curing. The intaglio convex member 123 is patterned on the intaglio bottom material 122 and has light-shielding properties and releasability from the cured conductive material. For example, various known black photosensitive resin compositions for black matrix for color filters (for example, those described in Example 1 of Patent Document 4) are used, and the composition is uniformly coated on the intaglio bottom material 122. It can be formed by pattern exposure and development after drying. The method for applying the intaglio bottom material 122 and the intaglio convex member is not particularly limited, and examples thereof include spin coating and die coating.
導電材２２はＵＶ硬化性を有するものであれば特に限定されるものではなく、Nｉ、Ａｌ、Ｃu、Ａｇ、Ａｕ、カーボン等の微粉体、Ａｇ、Ｃｕ、Ａｕ等のナノ粒子、有機Ａｇ化合物等の導電材を含有するＵＶ硬化性導電性ペースト等の公知の材料を用いることができる。 The conductive material 22 is not particularly limited as long as it has UV-curing properties. Fine powders such as Ni, Al, Cu, Ag, Au, and carbon, nanoparticles such as Ag, Cu, and Au, and organic Ag compounds A known material such as a UV curable conductive paste containing a conductive material such as the above can be used.
凹版転写型１１および１２の凹部パターンはソース・ドレイン電極の形状以外に配線パターンを含んでいても良いことがあり（配線抵抗が問題とならない場合）、この場合はソース・ドレイン電極と配線を同工程で形成することが可能である。また、本発明はソース・ドレイン電極の形成方法に関するものであるが、本発明において凹部パターンをゲート電極の形状とすることで、薄膜トラランジスタ用基材に予めゲート電極を形成する方法として、型を用い転写しても良い。すなわち全ての電極形成に転写方法を利用しても良い。 The concave pattern of the intaglio transfer molds 11 and 12 may include a wiring pattern in addition to the shape of the source / drain electrode (when wiring resistance does not matter). In this case, the source / drain electrode and the wiring are the same. It can be formed in a process. The present invention also relates to a method for forming a source / drain electrode. In the present invention, a mold is used as a method for forming a gate electrode in advance on a thin film transistor base material by forming a concave pattern in the shape of a gate electrode. May be used for transfer. That is, a transfer method may be used for all electrode formation.
次に、凹版転写型の凹部に前記の如く充填硬化した導電材を、薄膜トランジスタ用基材へ転写することでソース・ドレイン電極を形成する。図３は、本発明の薄膜トランジスタの形成方法にかかる転写の例を、断面で示した部分説明図である。 Next, the source / drain electrodes are formed by transferring the conductive material filled and cured as described above into the recesses of the intaglio transfer mold to the thin film transistor substrate. FIG. 3 is a partial explanatory view showing, in section, an example of transfer according to the method for forming a thin film transistor of the present invention.
すなわち、図３に示すように、導電材２２が充填硬化された凹版転写型３１または３２
（なお、以下の説明において、特にことわりの無い限り、凹版転写型３１は前記の一例またはその他の例の凹版転写型３１、３２とする。）と薄膜トランジスタ用基材４１を接着剤５を介した状態で重ね合わせ（図３（ａ））、接着材を硬化させた後、薄膜トランジスタ用基材を接着剤とともに凹版転写型から分離し、導電材を接着剤を介して薄膜トランジスタ用基材に転写させることでソース・ドレイン電極６が形成される（ｂ）。
That is, as shown in FIG. 3, the intaglio transfer mold 31 or 32 in which the conductive material 22 is filled and cured.
(In the following description, unless otherwise specified, the intaglio transfer mold 31 is the intaglio transfer mold 31 or 32 of the above example or other examples) and the thin film transistor substrate 41 through the adhesive 5. After overlapping in the state (FIG. 3A) and curing the adhesive, the thin film transistor substrate is separated from the intaglio transfer mold together with the adhesive, and the conductive material is transferred to the thin film transistor substrate via the adhesive. Thus, the source / drain electrodes 6 are formed (b).
接着剤５は、無溶剤熱硬化タイプが用いられるが、後述の薄膜トランジスタ用基材の種類よっては、無溶剤ＵＶ硬化タイプを用いることも可能である。熱硬化タイプの接着材としては、例えば各種エポキシ系接着剤、UV硬化タイプの接着剤としては、例えば各種アクリル系接着剤が挙げられ、硬化後の導電材に対する十分な接着性を有するものが適宜選択して用いられる。 As the adhesive 5, a solventless thermosetting type is used. However, depending on the type of a thin film transistor substrate described later, a solventless UV curing type can also be used. Examples of the thermosetting adhesive include various epoxy adhesives, and examples of the UV curable adhesive include various acrylic adhesives, and those having sufficient adhesion to the conductive material after curing are appropriately used. Select and use.
接着材５を凹版転写型３１と薄膜トランジスタ用基材４１に介在させる方法は、特に限定されるものではないが、例えば、凹版転写型の上に薄膜トランジスタ用基材を若干傾斜させて一端側を接触させるように位置させ、その接触している側で凹版転写型と薄膜トランジスタ用基材との間に接着剤を供給し、この状態で接触している側からプレスローラなどの圧着手段に通すことで、凹版転写型と薄膜トランジスタ用基材との間に接着材を展開することができる。 The method of interposing the adhesive 5 between the intaglio transfer mold 31 and the thin film transistor substrate 41 is not particularly limited. For example, the thin film transistor substrate is slightly tilted on the intaglio transfer mold to contact one end side. The adhesive is supplied between the intaglio transfer mold and the thin film transistor substrate on the contacted side, and is passed through a pressing means such as a press roller from the contacted side in this state. An adhesive can be developed between the intaglio transfer mold and the thin film transistor substrate.
この状態で、接着剤５を硬化させ、凹版転写型３１の凹部にて硬化済みの導電剤を接着剤と強固に接着させた後、凹版転写型と薄膜トランジスタ用基材４１を分離することで、凹部にて硬化済みの導電剤が接着剤を介して薄膜トランジスタ用基材に転写され、薄膜トランジスタ基材はソース・ドレイン電極６を有したものとなる。 In this state, after the adhesive 5 is cured and the conductive agent cured in the concave portion of the intaglio transfer mold 31 is firmly adhered to the adhesive, the intaglio transfer mold and the thin film transistor substrate 41 are separated, The conductive agent cured in the recess is transferred to the thin film transistor base material through the adhesive, and the thin film transistor base material has the source / drain electrodes 6.
薄膜トランジスタ用基材４１は特に限定されるものではないが、各種ガラス基板をはじめ適当な機械的剛性をもつ公知のプラスチックフィルムもしくはシートより耐熱性や可撓性などの観点から適宜選択して用いることができる。具体的には、ソーダライムガラス、石英、シリコンウエハーや、ポリエチレンテレフタレート（ＰＥＴ）、ポリエチレンナフタレート（ＰＥＮ）、ポリプロピレン、シクロオレフィンポリマー、ポリイミド、ポリエーテルスルホン（ＰＥＳ）、ポリメチルメタクリレート（ＰＭＭＡ）、ポリカーボネート、ポリアリルレートなどを使用することができる。これらのうちＵＶ透過性を有する基材であれば、前記接着剤５としてＵＶ硬化性のものを用いることが可能であり、凹版転写型３１と薄膜トランジスタ用基材４１を重ね合わせた状態で、薄膜トランジスタ基材４１側からＵＶ光を照射することで接着剤を硬化することができる。 The substrate 41 for the thin film transistor is not particularly limited, but may be appropriately selected and used from the viewpoint of heat resistance and flexibility from known plastic films or sheets having appropriate mechanical rigidity including various glass substrates. Can do. Specifically, soda lime glass, quartz, silicon wafer, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polypropylene, cycloolefin polymer, polyimide, polyethersulfone (PES), polymethyl methacrylate (PMMA), Polycarbonate, polyallylate and the like can be used. Of these, a UV curable substrate can be used as the adhesive 5 if it is a UV transmissive substrate, and the intaglio transfer mold 31 and the thin film transistor substrate 41 are superposed on each other. The adhesive can be cured by irradiating UV light from the substrate 41 side.
このように得られたソース・ドレイン電極６が形成された薄膜トランジスタ用基材４１に、半導体層９１、ゲート絶縁膜７１およびゲート電極８１を順次形成することで、図４に示すトップゲート型薄膜トランジスタが形成される。 The top gate type thin film transistor shown in FIG. 4 is formed by sequentially forming the semiconductor layer 91, the gate insulating film 71, and the gate electrode 81 on the thin film transistor base material 41 on which the source / drain electrodes 6 thus formed are formed. It is formed.
薄膜トランジスタ用基材４１は、予め薄膜トランジスタ用基材４１にゲート電極８２が形成されたもの（薄膜トランジスタ用基材４２、（図５（ａ））、あるいは、予め薄膜トランジスタ用基材４１にゲート電極８３とゲート絶縁膜７３が形成されたもの（薄膜トランジスタ用基材４３、（図５（ｂ）））としてもよい。これらの薄膜トランジスタ用基材４２（図５（ａ））ないし４３（図５（ｂ））を用い、ソース・ドレイン電極６を転写し半導体層９２、９３を形成することで、図６（ａ）および図６（ｂ）に示すボトムゲート型の薄膜トランジスタも形成することができる。 The thin film transistor base material 41 is obtained by previously forming a gate electrode 82 on the thin film transistor base material 41 (the thin film transistor base material 42 (FIG. 5A)) or the thin film transistor base material 41 and the gate electrode 83 in advance. A thin film transistor base material 43 (FIG. 5B) may be formed with the gate insulating film 73. These thin film transistor base materials 42 (FIG. 5A) to 43 (FIG. 5B). The bottom gate type thin film transistor shown in FIGS. 6A and 6B can also be formed by transferring the source / drain electrode 6 to form the semiconductor layers 92 and 93.
薄膜トランジスタ用基材４２を用いる場合は、接着剤５をゲート絶縁膜として機能させるため、ゲート絶縁膜を設ける工程が不要となる長所があるが、接着剤としてゲート絶縁膜に必要な絶縁性を有するものを用い、凹版転写型３１と薄膜トランジスタ用基材４２の
ギャップを制御する必要が生じる点が短所となる。一方、薄膜トランジスタ用基材４３を用いる場合は、ゲート絶縁膜７３を設ける工程は必要ではあるが、凹版転写型とのギャップについては薄膜トランジスタ用基材４３との密着性を確保すればよく、薄膜トランジスタ用基材４２において必要となるギャップの制御よりは容易である。
When the thin film transistor base material 42 is used, since the adhesive 5 functions as a gate insulating film, there is an advantage that a step of providing a gate insulating film is unnecessary, but the gate insulating film has an insulating property necessary for the adhesive. The disadvantage is that it is necessary to control the gap between the intaglio transfer mold 31 and the thin film transistor substrate 42. On the other hand, when the thin film transistor base material 43 is used, the step of providing the gate insulating film 73 is necessary, but the gap with the intaglio transfer type may be ensured by ensuring adhesion with the thin film transistor base material 43. It is easier than controlling the gap required in the substrate 42.
薄膜トランジスタ用基材４２ないし４３を用いる場合は、薄膜トランジスタ用基材４１と凹版転写型３１がＵＶ透過性を有し、かつソース・ドレイン電極とゲート電極の重なりが無い場合、前記接着剤５としてＵＶ硬化性のものを用いること可能であり、薄膜トランジスタ基材４１側と凹版転写型３１側の両側からＵＶ光を照射することで接着剤５を硬化することができる。 When the thin film transistor bases 42 to 43 are used, the thin film transistor base 41 and the intaglio transfer mold 31 have UV transparency, and the source / drain electrode and the gate electrode do not overlap with each other. A curable material can be used, and the adhesive 5 can be cured by irradiating UV light from both sides of the thin film transistor substrate 41 side and the intaglio transfer mold 31 side.
ゲート絶縁膜７１および７３は公知の材料を用いて形成することができる。具体的には、ＳｉＯ2、ＢａxＳｒ(1-x)ＴｉＯ3、ＢａＴｉxＺｒ(1-x)Ｏ3等の無機系材料や、ポリエステル／メラミン樹脂ペースト、ポリメチルメタクリレート、ポリ塩化ビニル、ポリビニルアルコール、ポリビニルフェノール、ポリスチレン、シアノエチルプルランなどの有機系材料を用いることができる。絶縁層の形成には、例えば、スピンコート、ディップコート、スプレーコート、スクリーン印刷、凸版印刷、凹版印刷、平版印刷、インクジェット、真空蒸着、ＣＶＤ等の公知の方法が用いられる。 The gate insulating films 71 and 73 can be formed using a known material. Specifically, inorganic materials such as SiO 2 , Ba x Sr (1-x) TiO 3 , BaTi x Zr (1-x) O 3 , polyester / melamine resin paste, polymethyl methacrylate, polyvinyl chloride, Organic materials such as polyvinyl alcohol, polyvinyl phenol, polystyrene, and cyanoethyl pullulan can be used. For forming the insulating layer, for example, a known method such as spin coating, dip coating, spray coating, screen printing, letterpress printing, intaglio printing, planographic printing, ink jet, vacuum deposition, or CVD is used.
ゲート電極８１〜８３は、例えば導電性インクをスクリーン印刷した後、必要に応じ熱処理することや、銅箔を貼った銅貼り基板のパターニングにより形成できるが、勿論、真空蒸着、スパッタ、ＣＶＤなどの気相法やその他の塗布法などで形成してもよい。ゲート電極８１〜８３の導電材料としてはNｉ、Ａｌ、Ｃｕ、Ａｇ、Ａｕなどの金属材料、あるいはNｉ、Ａｌ、Ｃu、Ａｇ、Ａｕ、カーボン等の微粉体、Ａｇ、Ｃｕ、Ａｕ等のナノ粒子、有機Ａｇ化合物等の導電材を含有する各種導電性ペーストないし導電性インク等の公知の材料を用いることができる。 The gate electrodes 81 to 83 can be formed, for example, by screen-printing conductive ink and then heat-treating as necessary, or by patterning a copper-clad substrate with a copper foil attached, but of course, vacuum deposition, sputtering, CVD, etc. It may be formed by a vapor phase method or other coating methods. As the conductive material of the gate electrodes 81 to 83, a metal material such as Ni, Al, Cu, Ag, or Au, or a fine powder such as Ni, Al, Cu, Ag, Au, or carbon, or a nanoparticle such as Ag, Cu, or Au In addition, known materials such as various conductive pastes or conductive inks containing a conductive material such as an organic Ag compound can be used.
半導体層９１〜９３は、各種公知の材料で形成可能である。例えは、ペンタセン、ポリチオフェン、ポリアリルアミン、フルオレンビオチオフェン共重合体などの有機系材料、カーボンナノチューブやフラーレンなどの炭素化合物材料、セレン化カドミウム粒子などの無機系の材料が挙げられる。さらに半導体層としては、ＩｎＧａＺｎＯ系、ＩｎＧａＯ系、ＺｎＧａＯ系、ＩｎＺｎＯ系、ＺｎＯ、ＳｎＯ2等の酸化物半導体が使用可能である。半導体層９１〜９３は、各種公知の方法で形成可能である。例えば、スピンコート、ディップコート、スクリーン印刷、凸版印刷、凹版印刷、平版印刷、インクジェット、真空蒸着などから半導体材料に応じ適宜選択して用いられる。 The semiconductor layers 91 to 93 can be formed of various known materials. Examples thereof include organic materials such as pentacene, polythiophene, polyallylamine, and fluorenebiothiophene copolymer, carbon compound materials such as carbon nanotubes and fullerenes, and inorganic materials such as cadmium selenide particles. Furthermore, as the semiconductor layer, an oxide semiconductor such as InGaZnO-based, InGaO-based, ZnGaO-based, InZnO-based, ZnO, or SnO 2 can be used. The semiconductor layers 91 to 93 can be formed by various known methods. For example, spin coating, dip coating, screen printing, letterpress printing, intaglio printing, planographic printing, ink jet, vacuum deposition, and the like are appropriately selected and used according to the semiconductor material.
＜実施例1＞
（凹版転写型作製と凹部への導電材の充填）
まず、前記図1に示した凹版転写型を作製し凹部へ導電材を充填した。
<Example 1>
(Production of intaglio transfer mold and filling of concave parts with conductive material)
First, the intaglio transfer mold shown in FIG. 1 was prepared, and a conductive material was filled in the recess.
厚さ０．５ｍｍ、大きさが１００ｍｍ×１００ｍｍのインバー合金の板を基板として、フォトリソグラフィーとエッチング法でチャネル長１０μｍのソース・ドレイン電極のパターンを形成し、凹部深さが２μｍの凹版転写型を得た。次に、前記凹版転写型に熱硬化性の銀ペースト（住友電工社製）を全面塗布しドクターリングした後、乾燥および熱硬化させ、導電材が凹部に充填された凹版転写型を得た。
（導電材の薄膜トランジスタ基材への転写）
薄膜トランジスタ用基材として厚さ０．７ｍｍ、大きさが１００ｍｍ×１００ｍｍのソーダライムガラス基材を用いた。前記で作製した導電材が充填された凹版転写型にＵＶ硬化型無溶剤タイプの接着材を塗布し、該薄膜トランジスタ用基材を重ねた後、ラミネータ
を通すことで、凹版転写型と薄膜トランジスタ基材との間に接着剤を展開した。続いて、薄膜トランジスタ用基材側からＵＶ照射し接着剤を硬化させた後、凹版転写型と薄膜トランジスタ用基材を引き剥がすことで、ソース・ドレイン電極が接着材を介して設けられた薄膜トランジスタ基材を得た。
（薄膜トランジスタの形成）
前記ソース・ドレイン電極が形成された薄膜トランジスタ基材に、半導体層、ゲート絶縁膜およびゲート電極を順次設け薄膜トランジスタを形成した。
・半導体層の形成
前記ソース・ドレイン電極が形成された薄膜トランジスタ基材に、ポリ（３−ヘキシルチオフェン）溶液をスピンコートした後乾燥させ半導体層を形成した。
・ ゲート絶縁膜の形成
ポリビニルフェノールをシクロヘキサノンに溶解した絶縁層形成溶液を、前記半導体層上にスピンコートした後熱硬化させ、膜厚１μｍのゲート絶縁膜を形成した。
・ゲート電極の形成
前記ゲート絶縁膜上にＡｇをマスク蒸着しゲート電極を形成した
最後に、ソース・ドレイン電極上にビアを形成しトップゲート型薄膜トランジスタを完成させた。ドレイン電圧Ｖとドレイン電流Ｉの相関（Ｖ−Ｉ特性）のゲート電圧依存性を評価した結果、ＦＥＴ特性が確認された。
＜実施例２＞
（凹版転写型作製と凹部への導電材の充填）
まず、前記図２に示した凹版転写型を作製し凹部へ導電材を充填した。
Using an Invar alloy plate having a thickness of 0.5 mm and a size of 100 mm × 100 mm as a substrate, an intaglio transfer type having a channel length of 10 μm formed by photolithography and etching, and a recess depth of 2 μm Got. Next, a thermosetting silver paste (manufactured by Sumitomo Electric Co., Ltd.) was applied over the entire surface of the intaglio transfer mold, followed by doctoring, followed by drying and thermosetting to obtain an intaglio transfer mold in which a conductive material was filled in the recess.
(Transfer of conductive material to thin film transistor substrate)
A soda lime glass substrate having a thickness of 0.7 mm and a size of 100 mm × 100 mm was used as a thin film transistor substrate. The intaglio transfer mold filled with the conductive material prepared above is coated with a UV curable solventless type adhesive, and after the thin film transistor base material is stacked, the intaglio transfer mold and the thin film transistor base material are passed through a laminator. An adhesive was developed between the two. Subsequently, after the adhesive is cured by UV irradiation from the thin film transistor substrate side, the intaglio transfer mold and the thin film transistor substrate are peeled off, whereby the thin film transistor substrate in which the source / drain electrodes are provided via the adhesive Got.
(Formation of thin film transistors)
A thin film transistor was formed by sequentially providing a semiconductor layer, a gate insulating film and a gate electrode on the thin film transistor substrate on which the source / drain electrodes were formed.
Formation of Semiconductor Layer A thin film transistor substrate on which the source / drain electrodes were formed was spin-coated with a poly (3-hexylthiophene) solution and then dried to form a semiconductor layer.
-Formation of Gate Insulating Film An insulating layer forming solution in which polyvinyl phenol was dissolved in cyclohexanone was spin-coated on the semiconductor layer and then thermally cured to form a gate insulating film having a thickness of 1 μm.
-Formation of gate electrode Ag was mask-deposited on the gate insulating film to form a gate electrode. Finally, vias were formed on the source / drain electrodes to complete a top gate type thin film transistor. As a result of evaluating the gate voltage dependency of the correlation (V-I characteristic) between the drain voltage V and the drain current I, FET characteristics were confirmed.
<Example 2>
(Production of intaglio transfer mold and filling of concave parts with conductive material)
First, the intaglio transfer mold shown in FIG. 2 was prepared, and a conductive material was filled in the recess.
厚さ０．７ｍｍ、大きさが１００ｍｍ×１００ｍｍのソーダライムガラス基板を転写型用基板とした。特許文献４の合成例１に開示されている感光性樹脂とペンタエリスリトールトリアクリレートと適当な光重合開始剤からなる下記組成物を該ガラス基板にスピンコートし乾燥した後ＵＶ硬化し、厚さ２μｍの凹版底面材を形成した。 A soda lime glass substrate having a thickness of 0.7 mm and a size of 100 mm × 100 mm was used as a transfer mold substrate. The following composition comprising a photosensitive resin, pentaerythritol triacrylate and a suitable photopolymerization initiator disclosed in Synthesis Example 1 of Patent Document 4 is spin-coated on the glass substrate, dried, UV cured, and 2 μm thick An intaglio bottom material was formed.
（凹版転写型用組成物）
感光性樹脂：１００重量部、ペンタエリスリトールトリアクリレート：４重量部
光重合開始剤：５重量部、ＰＧＭＡｃ：９００重量部。
(Intaglio transfer composition)
Photosensitive resin: 100 parts by weight, pentaerythritol triacrylate: 4 parts by weight Photopolymerization initiator: 5 parts by weight, PGMAc: 900 parts by weight.
次に、特許文献４の実施例１に記載の方法で調製した黒色のＵＶ感光性材料を、凹版底面材を形成したガラス基材にスピンコートし乾燥させた後、チャネル長１０μｍのソース・ドレイン電極のパターンを露光した。続いて、所定の条件で現像した後ベークすることで遮光性凹版凸部材を形成し、凹部深さが２μｍの凹版転写型を得た。 Next, the black UV photosensitive material prepared by the method described in Example 1 of Patent Document 4 is spin-coated on a glass substrate on which an intaglio bottom material has been formed and dried, and then a source / drain having a channel length of 10 μm The electrode pattern was exposed. Subsequently, development was performed under predetermined conditions, followed by baking to form a light-shielding intaglio convex member, and an intaglio transfer mold having a concave depth of 2 μm was obtained.
次に、前記凹版転写型にＵＶ硬化性の銀ペースト（東洋インキ社製）を全面塗布し乾燥させた後、凹版転写型の転写型用基材側からＵＶ照射し、凹部の銀ペーストを硬化させた。続いて、所定条件で現像した後ベークし、導電材が凹部に充填された凹版転写型を得た。 Next, a UV curable silver paste (manufactured by Toyo Ink Co., Ltd.) is applied to the intaglio transfer mold and dried, and then UV irradiation is performed from the transfer mold substrate side of the intaglio transfer mold to cure the silver paste in the recess. I let you. Subsequently, development was performed under predetermined conditions, followed by baking to obtain an intaglio transfer mold in which a conductive material was filled in the recesses.
（導電材の薄膜トランジスタ基材への転写）
薄膜トランジスタ用基材として厚さ０．７ｍｍ、大きさが１００ｍｍ×１００ｍｍのソーダライムガラス基材を用いた。前記で作製した導電材が充填された凹版転写型にＵＶ硬化型無溶剤タイプの接着材を塗布し、該薄膜トランジスタ用基材を重ねた後、ラミネータを通すことで、凹版転写型と薄膜トランジスタ基材との間に接着剤を展開した。続いて、薄膜トランジスタ用基材側からＵＶ照射し接着剤を硬化させた後、凹版転写型と薄膜トランジスタ用基材を引き剥がすことで、ソース・ドレイン電極が接着材を介して設けられた薄膜トランジスタ基材を得た。
(Transfer of conductive material to thin film transistor substrate)
A soda lime glass substrate having a thickness of 0.7 mm and a size of 100 mm × 100 mm was used as a thin film transistor substrate. The intaglio transfer mold filled with the conductive material prepared above is coated with a UV curable solventless type adhesive, and after the thin film transistor base material is stacked, the intaglio transfer mold and the thin film transistor base material are passed through a laminator. An adhesive was developed between the two. Subsequently, after the adhesive is cured by UV irradiation from the thin film transistor substrate side, the intaglio transfer mold and the thin film transistor substrate are peeled off, whereby the thin film transistor substrate in which the source / drain electrodes are provided via the adhesive Got.
（薄膜トランジスタの形成）
前記ソース・ドレイン電極が形成された薄膜トランジスタ基材に、半導体層、ゲート絶縁膜およびゲート電極を順次設け薄膜トランジスタを形成した。
・半導体層の形成
前記ソース・ドレイン電極が形成された薄膜トランジスタ基材に、ポリ（３−ヘキシルチオフェン）溶液をスピンコートした後乾燥させ半導体層を形成した。
・ゲート絶縁膜の形成
ポリビニルフェノールをシクロヘキサノンに溶解した絶縁層形成溶液を、前記半導体層上にスピンコートした後熱硬化させ、膜厚１μｍのゲート絶縁膜を形成した。
・ゲート電極の形成
前記ゲート絶縁膜上にＡｇをマスク蒸着しゲート電極を形成した。
(Formation of thin film transistors)
A thin film transistor was formed by sequentially providing a semiconductor layer, a gate insulating film and a gate electrode on the thin film transistor substrate on which the source / drain electrodes were formed.
Formation of Semiconductor Layer A thin film transistor substrate on which the source / drain electrodes were formed was spin-coated with a poly (3-hexylthiophene) solution and then dried to form a semiconductor layer.
Formation of gate insulating film An insulating layer forming solution in which polyvinylphenol was dissolved in cyclohexanone was spin-coated on the semiconductor layer and then thermally cured to form a gate insulating film having a thickness of 1 μm.
-Formation of gate electrode Ag was mask-deposited on the gate insulating film to form a gate electrode.
最後に、ソース・ドレイン電極上にビアを形成しトップゲート型薄膜トランジスタを完成させた。ドレイン電圧Ｖとドレイン電流Ｉの相関（Ｖ−Ｉ特性）のゲート電圧依存性を評価した結果、ＦＥＴ特性が確認された。 Finally, vias were formed on the source / drain electrodes to complete a top gate type thin film transistor. As a result of evaluating the gate voltage dependency of the correlation (V-I characteristic) between the drain voltage V and the drain current I, FET characteristics were confirmed.
＜比較例１＞
銀ペーストを用いスクリーン印刷によりチャネル長１０μｍのソース・ドレイン電極のガラス基材への形成を試みたところ、ペーストの流動によりチャネルを形成することができなかった。これに対し、より高粘度な銀ペーストを用いたところ、チャネル部は形成できたがペーストのレベリング不足が生じパターンが連続な電極は形成できなかった。
<Comparative Example 1>
When an attempt was made to form a source / drain electrode having a channel length of 10 μm on a glass substrate by screen printing using a silver paste, the channel could not be formed by the flow of the paste. On the other hand, when a silver paste having a higher viscosity was used, the channel portion could be formed, but the paste was insufficiently leveled and an electrode having a continuous pattern could not be formed.
１１・・・凹版転写型
１２・・・凹版転写型
１２１・・転写型用基板
１２２・・凹版底面材
１２３・・凹版凸部材
２１・・・ＵＶ硬化性導電材
２２・・・ＵＶ硬化した導電材
３１・・・導電材が充填硬化された凹版転写型
３２・・・導電材が充填硬化された凹版転写型
４１・・・薄膜トランジスタ用基材
４２・・・ゲート電極が形成された薄膜トランジスタ用基材
４３・・・ゲート電極とゲート絶縁膜が形成された薄膜トランジスタ用基材
５・・・・接着剤
６・・・・ソース・ドレイン電極
７１・・・ゲート絶縁膜
７３・・・ゲート絶縁膜
８１・・・ゲート電極
８２・・・ゲート電極
８３・・・ゲート電極
９１・・・半導体層
９２・・・半導体層
９３・・・半導体層
DESCRIPTION OF SYMBOLS 11 ... Intaglio transfer type 12 ... Intaglio transfer type 121 ... Transfer substrate 122 ... Intaglio bottom material 123 ... Intaglio convex member 21 ... UV curable conductive material 22 ... UV curable conductive material Material 31 ... Intaglio transfer mold filled and cured with conductive material 32 ... Intaglio transfer mold filled and cured with conductive material 41 ... Substrate for thin film transistor 42 ... Base for thin film transistor on which gate electrode is formed Material 43... Thin film transistor base material on which a gate electrode and a gate insulating film are formed 5... Adhesive 6... Source / drain electrode 71 ... Gate insulating film 73 ... Gate insulating film 81 ... Gate electrode 82 ... Gate electrode 83 ... Gate electrode 91 ... Semiconductor layer 92 ... Semiconductor layer 93 ... Semiconductor layer
Claims (3)
2. The method of forming a thin film transistor according to claim 1 , wherein a thin film transistor substrate having a gate electrode and a gate insulating film formed thereon is used.
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| WO2010117102A1 (en) * | 2009-04-09 | 2010-10-14 | 서강대학교 산학협력단 | Method for aligning colloidal crystals as single crystals |
| US9516749B2 (en) | 2012-07-04 | 2016-12-06 | Panasonic Intellectual Property Management Co., Ltd. | Electronic component-mounted structure, IC card and COF package |
| CN104157695B (en) * | 2014-07-14 | 2017-02-15 | 京东方科技集团股份有限公司 | Thin film transistor, as well as preparation method, array substrate and display device thereof |
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| JPH04135888A (en) * | 1990-09-28 | 1992-05-11 | Dainippon Printing Co Ltd | Pattern transfer method |
| JPH0775909B2 (en) * | 1990-09-28 | 1995-08-16 | 大日本印刷株式会社 | Alignment transfer method |
| JPH05147360A (en) * | 1991-11-27 | 1993-06-15 | Dainippon Printing Co Ltd | Forming method for fine pattern |
| JP2593995B2 (en) * | 1992-02-28 | 1997-03-26 | 株式会社ジーティシー | Method of forming fine pattern |
| JP3106690B2 (en) * | 1992-06-02 | 2000-11-06 | ソニー株式会社 | Film formation method |
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| JP4281324B2 (en) * | 2002-10-23 | 2009-06-17 | コニカミノルタホールディングス株式会社 | ORGANIC THIN FILM TRANSISTOR DEVICE, ITS MANUFACTURING METHOD, AND ORGANIC THIN FILM TRANSISTOR SHEET |
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