JP4816214B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4816214B2
JP4816214B2 JP2006110778A JP2006110778A JP4816214B2 JP 4816214 B2 JP4816214 B2 JP 4816214B2 JP 2006110778 A JP2006110778 A JP 2006110778A JP 2006110778 A JP2006110778 A JP 2006110778A JP 4816214 B2 JP4816214 B2 JP 4816214B2
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semiconductor
thickness dimension
spacer
igbt
heat sinks
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JP2007287784A (en
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憲司 河野
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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Abstract

<P>PROBLEM TO BE SOLVED: To reduce a manufacturing cost by reducing the number of elements to be mounted between a pair of heat sinks, and eliminating the necessity of highly accurately adjusting and controlling the thickness dimension of each of the elements. <P>SOLUTION: The semiconductor device 1 is configured so that a plurality of stacks of semiconductor elements 4, 5 and spacers 6, 7 are sandwiched between the pair of heat sinks 2, 3. The semiconductor device 1 is configured so that an element integrating an FWD with an IGBT is used as the semiconductor elements 2, 3; gate driving ICs 8, 9 of the IGBT are arranged between the pair of heat sinks 2, 3; and the semiconductor elements and the spacers of a combination in which (d1+d2) is a substantial constant value are selected and used from many semiconductor elements and many spacers, where d1 is the thickness of a semiconductor element and d2 is the thickness of a spacer. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

本発明は、半導体素子及びスペーサを積み重ねたものを複数個、一対のヒートシンクの間に挟んで構成された半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device configured by sandwiching a plurality of stacked semiconductor elements and spacers between a pair of heat sinks, and a method for manufacturing the same.

インバータ装置等に利用される両面放熱パワーモジュールは、一対のヒートシンクの間に複数個のＩＧＢＴ素子と複数個のＦＷＤ素子を挟むように実装して構成されており、一例として例えば特許文献１に記載のものが知られている。この構成の場合、ＩＧＢＴ素子のゲート駆動ＩＣは、パワーモジュールの外部に配設されており、パワーモジュールのリード端子と上記ゲート駆動ＩＣとを接続することにより、ＩＧＢＴ素子を駆動している。
アメリカ合衆国特許第６，０７２，２４０号 A double-sided heat dissipation power module used for an inverter device or the like is configured by mounting a plurality of IGBT elements and a plurality of FWD elements between a pair of heat sinks. Things are known. In this configuration, the gate drive IC of the IGBT element is arranged outside the power module, and the IGBT element is driven by connecting the lead terminal of the power module and the gate drive IC.
United States Patent No. 6,072,240

しかし、上記構成の場合、ゲート駆動ＩＣをパワーモジュールの外部に配設する構成であるため、接続用の配線も含めてシステム全体の構成が大きくなるという問題点や、配線の寄生インダクタンスによりスイッチ速度が遅くなって損失が増えるという問題点がある。また、多くのＩＧＢＴ素子及びＦＷＤ素子を一対のヒートシンクの間に実装するため、各素子の厚み寸法のばらつきにより各素子に作用する応力の大きさをばらつかせることから、各素子の接合部（半田付け部）の信頼性を低下させるという問題点もある。この対策としては、各素子の厚み寸法を高精度に調整・管理する必要があり、製造コストを増加させる要因になっていた。   However, in the case of the above configuration, since the gate drive IC is disposed outside the power module, the configuration of the entire system including the wiring for connection becomes large, and the switching speed due to the parasitic inductance of the wiring. However, there is a problem that the loss is increased due to the delay. In addition, since many IGBT elements and FWD elements are mounted between a pair of heat sinks, the magnitude of stress acting on each element varies due to variations in the thickness dimension of each element. There is also a problem that the reliability of the soldering part) is lowered. As a countermeasure, it is necessary to adjust and manage the thickness dimension of each element with high accuracy, which is a factor of increasing the manufacturing cost.

そこで、本発明の目的は、一対のヒートシンクの間に実装する素子の個数を削減すると共に、各素子の厚み寸法を高精度に調整・管理しなくてもすむようにして、製造コストを低減することができる半導体装置及びその製造方法を提供するにある。   Accordingly, an object of the present invention is to reduce the number of elements to be mounted between a pair of heat sinks and reduce the manufacturing cost by eliminating the need to adjust and manage the thickness dimension of each element with high accuracy. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same.

本発明の半導体装置は、半導体素子及びスペーサを積み重ねたものを複数個、一対のヒートシンクの間に挟んで構成されたものにおいて、前記半導体素子は、ＩＧＢＴにＦＷＤを一体化させた素子で構成され、前記ＩＧＢＴのゲート駆動用のＩＣチップであって、前記一対のヒートシンクの間に配設されたゲート駆動ＩＣを備え、前記半導体素子の厚み寸法ｄ１とし、前記スペーサの厚み寸法ｄ２としたときに、ｄ１＋ｄ２がほぼ一定値となると共に、前記スペーサの厚み寸法ｄ２が前記ゲート駆動ＩＣの厚み寸法よりも厚くなるように構成したところに特徴を有する。 In the semiconductor device of the present invention, a plurality of stacked semiconductor elements and spacers are sandwiched between a pair of heat sinks. The semiconductor element is configured by an element in which an FWD is integrated with an IGBT. , an IC chip for driving the gate of the IGBT, a gate drive IC disposed between the pair of heat sinks, and the thickness d1 of the previous SL semiconductor device, when the thickness d2 of the spacer Further, the present invention is characterized in that d1 + d2 has a substantially constant value and the thickness dimension d2 of the spacer is larger than the thickness dimension of the gate driving IC .

上記構成によれば、半導体素子として、ＩＧＢＴにＦＷＤを一体化させた素子を使用するので、一対のヒートシンクの間に実装する素子の個数を削減できる。また、多数の半導体素子及び多数のスペーサの中から、前記半導体素子の厚み寸法ｄ１とし、前記スペーサの厚み寸法ｄ２としたときに、ｄ１＋ｄ２がほぼ一定値となる組み合わせの前記半導体素子及び前記スペーサを選択して使用するように構成したので、各素子の厚み寸法を高精度に調整・管理しなくても、組み合わせた半導体素子及びスペーサの全体の厚み寸法がほぼ一定値となる。このため、各素子に作用する応力の大きさを均一にすることができ、各素子の接合部の信頼性を向上させることができる。更に、スペーサの厚み寸法ｄ２がゲート駆動ＩＣの厚み寸法よりも厚くなるように構成したので、ゲート駆動ＩＣが該ゲート駆動ＩＣを実装していない側のヒートシンクに設けられた配線層に接触することを防止できると共に、ゲート駆動ＩＣのボンディング用のワイヤを配線するための空間を確保することができる。 According to the above configuration, since the element in which the FWD is integrated with the IGBT is used as the semiconductor element, the number of elements mounted between the pair of heat sinks can be reduced. Further, the semiconductor element and the spacer are combined in such a combination that d1 + d2 becomes a substantially constant value when the thickness dimension d1 of the semiconductor element and the thickness dimension d2 of the spacer are selected from among a number of semiconductor elements and a number of spacers Since it is configured to be selected and used, the total thickness dimension of the combined semiconductor element and spacer becomes a substantially constant value without adjusting and managing the thickness dimension of each element with high accuracy. For this reason, the magnitude | size of the stress which acts on each element can be made uniform, and the reliability of the junction part of each element can be improved. Furthermore, since the spacer has a thickness d2 that is larger than the thickness of the gate drive IC, the gate drive IC is in contact with the wiring layer provided on the heat sink on the side where the gate drive IC is not mounted. Can be prevented, and a space for wiring bonding wires of the gate drive IC can be secured.

また、上記構成の場合、前記スペーサを、金属で構成することが好ましい。更に、前記スペーサを、半導体で構成することがより一層好ましい。
本発明の半導体素子の製造方法は、半導体素子及びスペーサを積み重ねたものを複数個、一対のヒートシンクの間に挟んで構成された半導体素子を製造する方法において、前記半導体素子として、ＩＧＢＴにＦＷＤを一体化させた素子を使用し、前記ＩＧＢＴのゲート駆動ＩＣを前記一対のヒートシンクの間に配設し、多数の前記半導体素子及び多数の前記スペーサの中から、前記半導体素子の厚み寸法ｄ１とし、前記スペーサの厚み寸法ｄ２としたときに、ｄ１＋ｄ２がほぼ一定値となる組み合わせの前記半導体素子及び前記スペーサを選択して使用すると共に、前記スペーサの厚み寸法ｄ２を前記ゲート駆動ＩＣの厚み寸法よりも厚くしたところに特徴を有する。 Moreover, in the case of the said structure, it is preferable to comprise the said spacer with a metal. Furthermore, it is even more preferable that the spacer is made of a semiconductor.
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a semiconductor device having a plurality of stacked semiconductor devices and spacers sandwiched between a pair of heat sinks; Using the integrated element, the gate drive IC of the IGBT is disposed between the pair of heat sinks, and the thickness dimension d1 of the semiconductor element is selected from among the multiple semiconductor elements and the multiple spacers, When the thickness dimension d2 of the spacer is set, the combination of the semiconductor element and the spacer in which d1 + d2 becomes a substantially constant value is selected and used , and the thickness dimension d2 of the spacer is made larger than the thickness dimension of the gate driving IC Characterized by thickening .

以下、本発明の第１の実施例について、図１ないし図４を参照しながら説明する。まず、図１は、本実施例のＩＧＢＴモジュール（半導体装置）１の縦断面図である。この図１に示すように、ＩＧＢＴモジュール１は、一対のヒートシンク２、３と、これらヒートシンク２、３間に配設される半導体素子４、５と、ヒートシンク２、３間に配設され半導体素子４、５に積み重ねられるスペーサ６、７と、ヒートシンク２、３間に配設されるゲート駆動ＩＣ８、９とを備えて構成されている。   A first embodiment of the present invention will be described below with reference to FIGS. First, FIG. 1 is a longitudinal sectional view of an IGBT module (semiconductor device) 1 of the present embodiment. As shown in FIG. 1, the IGBT module 1 includes a pair of heat sinks 2 and 3, semiconductor elements 4 and 5 disposed between the heat sinks 2 and 3, and semiconductor elements disposed between the heat sinks 2 and 3. Spacers 6 and 7 stacked on 4 and 5 and gate drive ICs 8 and 9 disposed between the heat sinks 2 and 3 are provided.

ヒートシンク２、３は、熱伝導性が良い絶縁部材である例えば窒化アルミニウム（ＡｌＮ）製の板材で構成されている。尚、ヒートシンク２、３を、例えばダイヤモンド製の板材で構成しても良い。   The heat sinks 2 and 3 are made of a plate material made of, for example, aluminum nitride (AlN), which is an insulating member having good thermal conductivity. In addition, you may comprise the heat sinks 2 and 3 with the board | plate material made from a diamond, for example.

半導体素子４、５は、図２に示すように、ＩＧＢＴ１０にＦＷＤ１１を一体化させたＩＧＢＴチップ（素子）１２で構成されており、その形状は矩形薄板状である。本実施例の場合、ＩＧＢＴチップ１２は、その厚み寸法が例えば１５０μｍ程度になるように製造されている。ＩＧＢＴチップ１２の厚み寸法の製造のばらつきは、図３に示すような度数分布となり、厚み寸法の中心（１５０μｍ）のものが最も多く、中心より薄いほどまたは厚いほど少なくなる。この場合、最も薄い厚み寸法をａ１とし、最も厚い厚み寸法をａｎとしている。   As shown in FIG. 2, each of the semiconductor elements 4 and 5 includes an IGBT chip (element) 12 in which an FWD 11 is integrated with an IGBT 10 and has a rectangular thin plate shape. In the case of the present embodiment, the IGBT chip 12 is manufactured so that its thickness dimension is, for example, about 150 μm. The variation in the manufacturing of the thickness dimension of the IGBT chip 12 has a frequency distribution as shown in FIG. 3, and is most often at the center (150 μm) of the thickness dimension, and decreases as the thickness is thinner or thicker. In this case, the thinnest thickness dimension is a1, and the thickest thickness dimension is an.

スペーサ６、７は、熱伝導性が良く且つ導電性の良い部材である例えば銅製のブロックで構成されている。本実施例の場合、スペーサ６、７は、その厚み寸法が例えば５００μｍ程度になるように製造されている。スペーサ６、７の厚み寸法の製造のばらつきは、図４に示すような度数分布となり、厚み寸法の中心（５００μｍ）のものが最も多く、中心より薄いほどまたは厚いほど少なくなる。この場合、最も薄い厚み寸法をｂ１とし、最も厚い厚み寸法をｂｎとしている。   The spacers 6 and 7 are made of, for example, copper blocks that are members having good thermal conductivity and good conductivity. In the case of the present embodiment, the spacers 6 and 7 are manufactured so that the thickness dimension thereof is, for example, about 500 μm. The variation in the manufacturing of the thickness dimension of the spacers 6 and 7 has a frequency distribution as shown in FIG. 4, and is most often at the center (500 μm) of the thickness dimension, and decreases as the thickness is thinner or thicker. In this case, the thinnest thickness dimension is b1, and the thickest thickness dimension is bn.

ゲート駆動ＩＣ８、９は、半導体素子４、５のＩＧＢＴ１０のゲート駆動用のＩＣチップである。尚、ゲート駆動ＩＣ８、９の厚み寸法は、例えば４００μｍ程度になるように製造されている。   The gate drive ICs 8 and 9 are IC chips for driving the gate of the IGBT 10 of the semiconductor elements 4 and 5. The gate drive ICs 8 and 9 are manufactured to have a thickness dimension of, for example, about 400 μm.

上記構成の場合、一方（図１中右方）の半導体素子４については、その下面に設けられたエミッタ電極を下方のヒートシンク２の上面に設けられたエミッタ接続用の配線層１３に半田付けしている。このとき、半導体素子４の下面の右端部に設けられたベース電極をヒートシンク２の上面に設けられたベース接続用の配線層１４に半田付けしている。   In the case of the above configuration, one (on the right side in FIG. 1) of the semiconductor element 4 is soldered to the emitter connection wiring layer 13 provided on the upper surface of the lower heat sink 2 with the emitter electrode provided on the lower surface thereof. ing. At this time, the base electrode provided at the right end of the lower surface of the semiconductor element 4 is soldered to the wiring layer 14 for base connection provided on the upper surface of the heat sink 2.

そして、半導体素子４の上面に設けられたコレクタ電極をスペーサ６の下面に半田付けしている。更に、スペーサ６の上面を、上方のヒートシンク３の下面に設けられたコレクタ接続用の配線層１５に半田付けしている。尚、この配線層１５は、他方（図１中左方）の半導体素子５の上面に設けられたエミッタ電極を接続するエミッタ接続用の配線層でもある。   The collector electrode provided on the upper surface of the semiconductor element 4 is soldered to the lower surface of the spacer 6. Further, the upper surface of the spacer 6 is soldered to a wiring layer 15 for collector connection provided on the lower surface of the upper heat sink 3. The wiring layer 15 is also an emitter connection wiring layer for connecting an emitter electrode provided on the upper surface of the other semiconductor element 5 (left side in FIG. 1).

即ち、他方の半導体素子５の上面のエミッタ電極をヒートシンク３の下面の上記配線層１５に半田付けしている。そして、上記半導体素子５の上面の左端部に設けられたベース電極を、ヒートシンク３の下面に設けられたベース接続用の配線層１６に半田付けしている。   That is, the emitter electrode on the upper surface of the other semiconductor element 5 is soldered to the wiring layer 15 on the lower surface of the heat sink 3. The base electrode provided at the left end of the upper surface of the semiconductor element 5 is soldered to the wiring layer 16 for base connection provided on the lower surface of the heat sink 3.

更に、半導体素子５の下面に設けられたコレクタ電極をスペーサ７の上面に半田付けしている。それから、スペーサ７の下面を、下方のヒートシンク２の上面に設けられたコレクタ接続用の配線層１７に半田付けしている。   Further, the collector electrode provided on the lower surface of the semiconductor element 5 is soldered to the upper surface of the spacer 7. Then, the lower surface of the spacer 7 is soldered to a collector connecting wiring layer 17 provided on the upper surface of the lower heat sink 2.

ここで、積み重ねる半導体素子４、５とスペーサ６、７の組み合わせについて説明する。半導体素子４、５の厚み寸法は、図３に示すような度数分布の製造ばらつきがある。スペーサ６、７の厚み寸法も、図４に示すような度数分布の製造ばらつきがある。そこで、半導体素子の厚み寸法ｄ１とし、スペーサの厚み寸法ｄ２としたときに、ｄ１＋ｄ２がほぼ一定値（この場合、例えば６５０μｍ）となる組み合わせの半導体素子及びスペーサを選択して組み合わせるように構成すれば、積み重ねたものの厚み寸法がほぼ一定になる。   Here, a combination of stacked semiconductor elements 4 and 5 and spacers 6 and 7 will be described. The thickness dimension of the semiconductor elements 4 and 5 has a manufacturing variation of a frequency distribution as shown in FIG. The thickness dimensions of the spacers 6 and 7 also have manufacturing variations in the frequency distribution as shown in FIG. Therefore, when the thickness dimension d1 of the semiconductor element and the thickness dimension d2 of the spacer are set, a combination of a semiconductor element and a spacer in which d1 + d2 is a substantially constant value (in this case, for example, 650 μm) is selected and combined. The thickness dimension of the stacked ones is almost constant.

具体的には、厚さ寸法がａ１の半導体素子と厚さ寸法がｂｎのスペーサとを組み合わせ、厚さ寸法がａ２の半導体素子と厚さ寸法がｂｎ−１のスペーサとを組み合わせ、厚さ寸法がａ３の半導体素子と厚さ寸法がｂｎ−２のスペーサとを組み合わせ、・・・、厚さ寸法がａｎの半導体素子と厚さ寸法がｂ１のスペーサとを組み合わせるように構成すれば良い。   Specifically, a semiconductor element having a thickness dimension of a1 and a spacer having a thickness dimension of bn are combined, and a semiconductor element having a thickness dimension of a2 and a spacer having a thickness dimension of bn-1 are combined to obtain a thickness dimension. May be configured such that a semiconductor element having a3 and a spacer having a thickness dimension of bn-2 are combined, and a semiconductor element having a thickness dimension of an and a spacer having a thickness dimension of b1 are combined.

また、一方（図１中右方）のゲート駆動ＩＣ８は、ヒートシンク２の配線層１４上に絶縁層１８を介して設けられた配線層１９上に半田付けされている。ゲート駆動ＩＣ８の各入出力電極は、配線層１４やリードフレーム２０にワイヤボンディングされている。そして、他方（図１中左方）のゲート駆動ＩＣ９は、ヒートシンク３の配線層１６上に絶縁層２１を介して設けられた配線層２２上に半田付けされている。ゲート駆動ＩＣ９の各入出力電極は、配線層１６やリードフレーム２３にワイヤボンディングされている。   One (right side in FIG. 1) gate drive IC 8 is soldered onto a wiring layer 19 provided on the wiring layer 14 of the heat sink 2 via an insulating layer 18. Each input / output electrode of the gate drive IC 8 is wire-bonded to the wiring layer 14 and the lead frame 20. The other (left side in FIG. 1) gate drive IC 9 is soldered onto a wiring layer 22 provided on the wiring layer 16 of the heat sink 3 via an insulating layer 21. Each input / output electrode of the gate drive IC 9 is wire-bonded to the wiring layer 16 and the lead frame 23.

そして、ヒートシンク２、３間には、図示しない樹脂が充填されており、この樹脂により半導体素子４、５、スペーサ６、７、ゲート駆動ＩＣ８、９がモールドされるように構成されている。   A resin (not shown) is filled between the heat sinks 2 and 3, and the semiconductor elements 4 and 5, the spacers 6 and 7, and the gate drive ICs 8 and 9 are molded by this resin.

このような構成の本実施例によれば、半導体素子４、５として、ＩＧＢＴ１０にＦＷＤ１１を一体化させたＩＧＢＴチップ１２を使用したので、一対のヒートシンク２、３の間に実装する素子の個数を削減することができる。そして、上記実施例においては、ＩＧＢＴ１０のゲート駆動ＩＣ８、９を一対のヒートシンク２、３の間に配設したので、ＩＧＢＴモジュール１全体の構成を小形化することができる。   According to the present embodiment having such a configuration, since the IGBT chip 12 in which the FWD 11 is integrated with the IGBT 10 is used as the semiconductor elements 4 and 5, the number of elements to be mounted between the pair of heat sinks 2 and 3 is set. Can be reduced. In the above embodiment, since the gate drive ICs 8 and 9 of the IGBT 10 are disposed between the pair of heat sinks 2 and 3, the entire configuration of the IGBT module 1 can be miniaturized.

また、上記実施例においては、多数の半導体素子及び多数のスペーサの中から、半導体素子の厚み寸法ｄ１とし、スペーサの厚み寸法ｄ２としたときに、ｄ１＋ｄ２がほぼ一定値となる組み合わせの半導体素子及びスペーサを選択して使用するように構成したので、各半導体素子の厚み寸法を高精度に調整・管理しなくても、各半導体素子に作用する応力の大きさを均一にすることができ、各半導体素子の接合部（半田付け部）の信頼性を向上させることができる。   Further, in the above-described embodiment, the combination of the semiconductor elements in which d1 + d2 has a substantially constant value when the thickness dimension d1 of the semiconductor element is set to the thickness dimension d2 of the spacer from among the large number of semiconductor elements and the plurality of spacers. Since the spacer is selected and used, the magnitude of the stress acting on each semiconductor element can be made uniform without adjusting and managing the thickness dimension of each semiconductor element with high accuracy. The reliability of the joining portion (soldering portion) of the semiconductor element can be improved.

図５は、本発明の第２の実施例を示すものである。尚、第１の実施例と同一構成には、同一符号を付している。この第２の実施例では、ゲート駆動ＩＣ８、９をワイヤボンディングで接続する代わりに、フリップチップで接続するように構成している。   FIG. 5 shows a second embodiment of the present invention. The same components as those in the first embodiment are denoted by the same reference numerals. In the second embodiment, the gate drive ICs 8 and 9 are connected by flip chip instead of being connected by wire bonding.

具体的には、図５に示すように、ゲート駆動ＩＣ８については、配線層１４の上に絶縁層２４を設け、この絶縁層２４の上に配線パターン２５を設け、この配線パターン２５にゲート駆動ＩＣ８をボール半田２６を介して接続している。尚、半導体素子４の下面のゲート電極は、上記配線パターン２５に半田付けされている。   Specifically, as shown in FIG. 5, for the gate driving IC 8, an insulating layer 24 is provided on the wiring layer 14, a wiring pattern 25 is provided on the insulating layer 24, and gate driving is performed on the wiring pattern 25. IC 8 is connected via ball solder 26. The gate electrode on the lower surface of the semiconductor element 4 is soldered to the wiring pattern 25.

同様にして、ゲート駆動ＩＣ９については、配線層１６の上に絶縁層２７を設け、この絶縁層２７の上に配線パターン２８を設け、この配線パターン２８にゲート駆動ＩＣ９をボール半田２９を介して接続している。尚、半導体素子５の上面のゲート電極は、上記配線パターン２８に半田付けされている。   Similarly, for the gate driving IC 9, an insulating layer 27 is provided on the wiring layer 16, a wiring pattern 28 is provided on the insulating layer 27, and the gate driving IC 9 is connected to the wiring pattern 28 via a ball solder 29. Connected. The gate electrode on the upper surface of the semiconductor element 5 is soldered to the wiring pattern 28.

上述した以外の第２の実施例の構成は、第１の実施例の構成と同じ構成となっている。従って、第２の実施例においても、第１の実施例とほぼ同じ作用効果を得ることができる。特に、第２の実施例では、ゲート駆動ＩＣ８、９をフリップチップで配線パターン２５、２８に接続するように構成したので、配線の寄生インダクタンスが小さくなり、ゲート駆動ＩＣ８、９からの出力信号の波形がシャープになり、ＩＧＢＴ１０のスイッチング損失を低減できる。また、ワイヤボンディングの実装余裕をなくすことが可能であるから、ヒートシンク２、３間の隙間を小さくすることができる。これにより、ヒートシンク２、３の熱抵抗を下げることができ、ＩＧＢＴチップをシュリンクできる。   The configuration of the second embodiment other than that described above is the same as the configuration of the first embodiment. Therefore, in the second embodiment, substantially the same operational effects as in the first embodiment can be obtained. In particular, in the second embodiment, since the gate driving ICs 8 and 9 are configured to be connected to the wiring patterns 25 and 28 by flip chip, the parasitic inductance of the wiring is reduced, and the output signals from the gate driving ICs 8 and 9 are reduced. The waveform becomes sharp and the switching loss of the IGBT 10 can be reduced. Moreover, since it is possible to eliminate the wire bonding mounting margin, the gap between the heat sinks 2 and 3 can be reduced. Thereby, the thermal resistance of the heat sinks 2 and 3 can be lowered, and the IGBT chip can be shrunk.

また、上記各実施例においては、スペーサ６、７を金属例えば銅で構成したが、これに代えて、半導体例えばシリコンで構成しても良い。このように構成すると、スペーサ６、７と半導体素子４、５の熱膨張率が同じになるので、熱に対する信頼性を向上できる。   In each of the above embodiments, the spacers 6 and 7 are made of a metal such as copper. However, instead of this, a semiconductor such as silicon may be used. If comprised in this way, since the thermal expansion coefficient of the spacers 6 and 7 and the semiconductor elements 4 and 5 becomes the same, the reliability with respect to a heat | fever can be improved.

更に、上記各実施例において、ゲート駆動ＩＣ８、９を、トレンチ・ＳＯＩ分離方式で構成するようにしても良い。このように、トレンチ・ＳＯＩ分離方式で絶縁分離すると、接合リーク電流が少なくなり、接合分離方式よりも高温動作に優れたものとなることから、パワー素子の発熱が多いインバータモジュールに最適である。尚、ゲート駆動ＩＣ８、９に、ＩＧＢＴやＦＷＤの温度、電流を常時監視する機能を付加するように構成することが好ましい。このように構成すると、ゲート駆動ＩＣ８、９の熱暴走を防止することができる。   Further, in each of the embodiments described above, the gate drive ICs 8 and 9 may be configured by a trench / SOI isolation system. Thus, insulation isolation by the trench / SOI isolation method reduces junction leakage current and is superior in operation at a higher temperature than the junction isolation method, and is optimal for an inverter module that generates a large amount of heat from the power element. It is preferable that the gate drive ICs 8 and 9 have a function of constantly monitoring the temperature and current of the IGBT and FWD. With this configuration, thermal runaway of the gate drive ICs 8 and 9 can be prevented.

更にまた、ゲート駆動ＩＣ８、９を、トレンチ・ＳＯＩ分離方式で構成した上で、低耐圧のＬＤＭＯＳを多段接続して構成することがより一層好ましい。尚、ＬＤＭＯＳを多段接続する構成を実現するに際しては、本出願人が先に出願した特願２００５−２２７０５８に記載されている構成を適宜用いれば良い。このように、ＬＤＭＯＳを多段接続するように構成すると、高耐圧を実現することができ、低電位、高電位間の電圧シフトが容易にできる。   Furthermore, it is more preferable that the gate drive ICs 8 and 9 are configured by trench / SOI separation and then are configured by connecting low-voltage LDMOS in multiple stages. When realizing a configuration in which LDMOSs are connected in multiple stages, the configuration described in Japanese Patent Application No. 2005-227058 filed earlier by the present applicant may be used as appropriate. Thus, when the LDMOS is configured to be connected in multiple stages, a high breakdown voltage can be realized, and a voltage shift between a low potential and a high potential can be easily performed.

また、上記各実施例の半導体素子４、５（ＦＷＤ１１を内蔵するＩＧＢＴチップ１２）において、ＩＧＢＴ１０のうちのエミッタ側の表面に、トレンチゲートとフロートｐｗｅｌｌ層とＧＮＤ（接地）ｐｗｅｌｌ層とを設けるように構成しても良い。この構成の一例を図６（第３の実施例）に示す。このように構成すると、ＩＧＢＴ１０及びＦＷＤ１１の総損失を最小にすることができるから、チップサイズを縮小することができる。   Further, in the semiconductor elements 4 and 5 (the IGBT chip 12 incorporating the FWD 11) of each of the above embodiments, a trench gate, a float pwell layer, and a GND (ground) pwell layer are provided on the surface of the IGBT 10 on the emitter side. You may comprise. An example of this configuration is shown in FIG. 6 (third embodiment). With this configuration, since the total loss of the IGBT 10 and the FWD 11 can be minimized, the chip size can be reduced.

また、上記第３の実施例の場合、ｐｗｅｌｌ濃度を最適化すると共に、全接地することにより、損失をより一層低減することができる。   Further, in the case of the third embodiment, the loss can be further reduced by optimizing the pwell concentration and grounding it all.

本発明の第１の実施例を示すＩＧＢＴモジュールの断面図Sectional drawing of IGBT module which shows 1st Example of this invention ＩＧＢＴモジュールの電気回路図Electrical circuit diagram of IGBT module 半導体素子の製造ばらつきを示す図Diagram showing manufacturing variations of semiconductor elements スペーサの製造ばらつきを示す図Diagram showing manufacturing variations of spacers 本発明の第２の実施例を示す図１相当図FIG. 1 equivalent view showing a second embodiment of the present invention. 本発明の第３の実施例を示す半導体素子の拡大部分断面図FIG. 4 is an enlarged partial cross-sectional view of a semiconductor device showing a third embodiment of the present invention.

符号の説明Explanation of symbols

図面中、１はＩＧＢＴモジュール（半導体装置）、２、３はヒートシンク、４、５は半導体素子、６、７はスペーサ、８、９はゲート駆動ＩＣ、１０はＩＧＢＴ、１１はＦＷＤ、１２はＩＧＢＴチップ（素子）を示す。   In the drawings, 1 is an IGBT module (semiconductor device), 2 and 3 are heat sinks, 4 and 5 are semiconductor elements, 6 and 7 are spacers, 8 and 9 are gate drive ICs, 10 is IGBT, 11 is FWD, and 12 is IGBT. A chip (element) is shown.

Claims (2)

半導体素子及びスペーサを積み重ねたものを複数個、一対のヒートシンクの間に挟んで
構成された半導体装置において、
前記半導体素子は、ＩＧＢＴにＦＷＤを一体化させた素子で構成され、
前記ＩＧＢＴのゲート駆動用のＩＣチップであって、前記一対のヒートシンクの間に配
設されたゲート駆動ＩＣを備え、
前記半導体素子の厚み寸法ｄ１とし、前記スペーサの厚み寸法ｄ２としたときに、ｄ１
＋ｄ２がほぼ一定値となると共に、前記スペーサの厚み寸法ｄ２が前記ゲート駆動ＩＣの
厚み寸法よりも厚くし、
前記スペーサは、半導体で構成されていることを特徴とする半導体装置。 In a semiconductor device configured by sandwiching a plurality of stacked semiconductor elements and spacers between a pair of heat sinks,
The semiconductor element is composed of an element in which FWD is integrated with an IGBT,
An IC chip for driving the gate of the IGBT, comprising a gate driving IC disposed between the pair of heat sinks;
When the thickness dimension d1 of the semiconductor element and the thickness dimension d2 of the spacer are d1,
+ D2 becomes a substantially constant value, and the thickness dimension d2 of the spacer is larger than the thickness dimension of the gate drive IC ,
The said spacer is comprised with the semiconductor, The semiconductor device characterized by the above-mentioned . 半導体素子及びスペーサを積み重ねたものを複数個、一対のヒートシンクの間に挟んで構成された半導体装置の製造方法において、
前記半導体素子として、ＩＧＢＴにＦＷＤを一体化させた素子を使用し、
前記ＩＧＢＴのゲート駆動ＩＣを前記一対のヒートシンクの間に配設し、
多数の前記半導体素子及び多数の前記スペーサの中から、前記半導体素子の厚み寸法ｄ
１とし、前記スペーサの厚み寸法ｄ２としたときに、ｄ１＋ｄ２がほぼ一定値となる組み
合わせの前記半導体素子及び前記スペーサを選択して使用すると共に、前記スペーサの厚
み寸法ｄ２を前記ゲート駆動ＩＣの厚み寸法よりも厚くし、
前記スペーサは、半導体で構成されていることを特徴とする半導体装置の製造方法。 In a manufacturing method of a semiconductor device configured by sandwiching a plurality of stacked semiconductor elements and spacers between a pair of heat sinks,
As the semiconductor element, an element in which FWD is integrated with IGBT is used,
The IGBT gate drive IC is disposed between the pair of heat sinks,
A thickness dimension d of the semiconductor element from among the plurality of semiconductor elements and the plurality of spacers.
1 and the thickness d2 of the spacer is selected and used in combination with the semiconductor element and the spacer in which d1 + d2 has a substantially constant value, and the thickness d2 of the spacer is the thickness of the gate driving IC. Thicker than the dimensions ,
The method of manufacturing a semiconductor device, wherein the spacer is made of a semiconductor .
JP2006110778A 2006-04-13 2006-04-13 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4816214B2 (en)

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