JP4731340B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4731340B2
JP4731340B2 JP2006026329A JP2006026329A JP4731340B2 JP 4731340 B2 JP4731340 B2 JP 4731340B2 JP 2006026329 A JP2006026329 A JP 2006026329A JP 2006026329 A JP2006026329 A JP 2006026329A JP 4731340 B2 JP4731340 B2 JP 4731340B2
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electrode
terminal
substrate
manufacturing
semiconductor device
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JP2007208082A (en
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延弘 今泉
誠志 中川
剛 石塚
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Fujitsu Ltd
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Description

本発明は、半導体装置の製造方法に関し、特に、半導体素子の端子と基板の電極とを接続させる方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for connecting a terminal of a semiconductor element and an electrode of a substrate.

近年のコンピュータシステムの回路基板は、高速化かつ大集積化に対応できることが要求されるため、その高密度化及び微細配線化が必要になってきている。そのため、従来のＩＣパッケージを基板に実装するのではなく、各半導体素子（ＬＳＩチップ）を基板に直接実装することが行われている。半導体素子と回路基板との接続手法として、半導体素子の金端子と回路基板の電極とのフリップチップ接合が提供されている。   In recent years, circuit boards of computer systems are required to be capable of high speed and large integration, so that their density and fine wiring have become necessary. Therefore, instead of mounting a conventional IC package on a substrate, each semiconductor element (LSI chip) is directly mounted on the substrate. As a method for connecting a semiconductor element and a circuit board, flip chip bonding between a gold terminal of the semiconductor element and an electrode of the circuit board is provided.

半導体素子の金端子と基板の電極とを接続するフリップチップ方式の接合の一つとして、接着剤を硬化させると同時に高荷重を印加し、半導体素子の金端子を押し潰すことによって基板の電極と接続させる圧接方式が提供されている。この接合方式は、接着剤を硬化させるときの収縮力と、金端子及び電極を押し潰したときの反発力とを利用して、接触を維持させることにより、両者の電気的接続を得る。   As one of the flip chip type joints connecting the gold terminal of the semiconductor element and the electrode of the substrate, the adhesive is cured and at the same time a high load is applied, and the gold terminal of the semiconductor element is crushed and the substrate electrode A pressure contact method for connection is provided. In this joining method, the electrical connection between the two is obtained by maintaining the contact by utilizing the contraction force when the adhesive is cured and the repulsive force when the gold terminal and the electrode are crushed.

なお、本発明に関連する技術として、半田バンプを用いてＩＣチップを実装する方法（（例えば、特許文献１参照）、複合金属粒子を利用して基板上にＬＳＩチップを実装する方法（例えば、特許文献２参照）、超微粒子を含む層を介在させて基板の配線パターンとボンディングワイヤとを接続する方法（例えば、特許文献３参照）などが知られている。
特開昭５３−７９４６２号公報 特開２００１−２９８０４９号公報 特開２００５−１５８７８５号公報 As a technique related to the present invention, a method of mounting an IC chip using a solder bump (for example, refer to Patent Document 1), a method of mounting an LSI chip on a substrate using composite metal particles (for example, Patent Document 2), a method of connecting a wiring pattern of a substrate and a bonding wire through a layer containing ultrafine particles (for example, refer to Patent Document 3), and the like are known.
JP-A-53-79462 JP 2001-298049 A JP 2005-158785 A

近年、半導体素子の高性能化に伴って、金端子のピッチが狭小化しており、これにより金端子のサイズも小さくなる傾向にある。したがって、接合時に高荷重を必要とする上述したような圧接方式では、狭ピッチ用の小さな金端子を潰すことにより、基板が反って電気的接続領域以外の領域において半導体素子及び基板間のクリアランスが狭くなるため、製造中のパーティクルが挟み込まれてチップ回路が破損するという問題が生じている。これを防止するために、接合時の荷重を低くしてクリアランスを確保する場合には、金端子と基板の電極とを押し潰したときの反発力が不足し、隣り合う電極間で断線するという問題が生じる。この結果、狭ピッチな金端子が形成されている半導体素子に圧接方式を適用した場合、接合が離れてしまう接合限界が生じる。   In recent years, with the increase in performance of semiconductor elements, the pitch of gold terminals has become narrower, and this tends to reduce the size of the gold terminals. Therefore, in the above-described pressure contact method that requires a high load at the time of bonding, the small gold terminal for narrow pitch is crushed, so that the substrate warps and the clearance between the semiconductor element and the substrate is increased in a region other than the electrical connection region. Since it becomes narrow, there is a problem that the chip circuit is damaged due to the particles being manufactured. In order to prevent this, when the clearance at the time of bonding is reduced to ensure the clearance, the repulsive force when the gold terminal and the electrode of the substrate are crushed is insufficient, and the adjacent electrodes are disconnected. Problems arise. As a result, when the pressure contact method is applied to a semiconductor element in which a narrow pitch gold terminal is formed, there is a bonding limit in which bonding is separated.

本発明は斯かる事情に鑑みてなされたものであり、半導体素子の端子と基板の電極との間に低温で焼結する金属ナノ粒子を介在させることにより、低荷重下においても、半導体素子の端子と基板の電極との間での良好な接合を得ることができる半導体装置の製造方法を提供することを目的とする。   The present invention has been made in view of such circumstances, and by interposing metal nanoparticles that are sintered at a low temperature between a terminal of a semiconductor element and an electrode of a substrate, the semiconductor element can be obtained even under a low load. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of obtaining good bonding between a terminal and an electrode of a substrate.

本発明に係る半導体装置の製造方法は、半導体素子の端子と基板の電極とを接続させる半導体装置の製造方法において、前記端子と前記電極との間に合成樹脂中に分散させたナノ粒径の金属粒子を介在させ、該金属粒子を焼結させ、前記合成樹脂を硬化させて前記端子と前記電極との電気的接続を得ることとし、前記端子と前記電極とを接続した後に、前記端子と前記電極との電気的接続が得られていない前記半導体素子と前記基板との間隙に封止用の合成樹脂を注入することを特徴とする。 A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a terminal of a semiconductor element and an electrode of a substrate are connected, and the nano particle size dispersed in a synthetic resin between the terminal and the electrode. Interposing metal particles, sintering the metal particles, curing the synthetic resin to obtain an electrical connection between the terminal and the electrode, and after connecting the terminal and the electrode, A sealing synthetic resin is injected into a gap between the semiconductor element that is not electrically connected to the electrode and the substrate .

本発明の半導体装置の製造方法にあっては、半導体素子の端子と基板の電極との間に、合成樹脂中に分散させた例えば銀、錫などのナノ粒径の金属粒子を介在させ、その金属粒子を焼結し、その合成樹脂を硬化して、半導体素子の端子と基板の電極とを接続させる。金属粒子が焼結したときの材料強度により、端子の狭ピッチ化に対して要求される低荷重下においても、良好な接合が得られる。合成樹脂中にナノ粒径の金属粒子を分散させた構成としたため、基板上に特別な処理を施す必要がなく、容易に金属粒子を介在することができ、また、狭ピッチの端子に対して均一な量の金属粒子の供給が可能となる。更に、金属粒子が焼結したときの材料強度だけでなく、合成樹脂の硬化時の強度も加わることになり、接合強度がより向上する。半導体素子の端子と基板の電極とを接続させた後に、端子と電極との電気的接続が得られていない半導体素子と基板との間隙に封止用の合成樹脂を注入する。よって、端子と電極との接続状態が安定する。 In the method for manufacturing a semiconductor device of the present invention, metal particles having a nano particle size such as silver or tin dispersed in a synthetic resin are interposed between a terminal of a semiconductor element and an electrode of a substrate. The metal particles are sintered, the synthetic resin is cured, and the terminals of the semiconductor element and the electrodes of the substrate are connected. Due to the material strength when the metal particles are sintered, good bonding can be obtained even under the low load required for narrowing the pitch of the terminals. Since the nano-sized metal particles are dispersed in the synthetic resin, it is not necessary to perform special treatment on the substrate, and the metal particles can be easily interposed. A uniform amount of metal particles can be supplied. Furthermore, not only the material strength when the metal particles are sintered, but also the strength when the synthetic resin is cured is added, so that the bonding strength is further improved. After connecting the terminal of the semiconductor element and the electrode of the substrate, a synthetic resin for sealing is injected into the gap between the semiconductor element and the substrate where electrical connection between the terminal and the electrode is not obtained. Therefore, the connection state between the terminal and the electrode is stabilized.

本発明に係る半導体装置の製造方法は、前記金属粒子として、前記端子及び／または前記電極と合金化する金属粒子を使用することを特徴とする。   The method for manufacturing a semiconductor device according to the present invention is characterized in that metal particles that are alloyed with the terminals and / or the electrodes are used as the metal particles.

本発明の半導体装置の製造方法にあっては、例えば金と合金化する錫などのナノ粒径の金属粒子を用いる。ナノ粒径の金属粒子の特徴は、金属の融点以下で粒子間が焼結し、バルク状に近い状態にできることにある。例えば、銀ナノ粒子を用いた場合、銀の融点９６０．８℃に対して、銀ナノ粒子の焼結温度は、接合温度と同等な２００℃である。ミクロンサイズの粒径の銀フィラーを用いた場合には、端子下に捕捉された粒子を、高荷重を与えることにより変形させ、粒子間の接触面積を大きくさせなければ良好な導通を確保することができない。これに対して、ナノ粒子を用いた場合は、接合温度下で粒子間が焼結することにより、荷重を与えなくても端子と良好な接触状態が得られる。また、端子または基板電極と合金化できる錫などの金属を用いた場合、２００℃の低温下で合金化層が形成できるため、半導体素子の端子と基板の電極との接合はより強固になる。   In the method for manufacturing a semiconductor device according to the present invention, metal particles having a nano particle size such as tin alloyed with gold are used. The feature of the metal particles having a nano particle size is that the particles are sintered at a temperature equal to or lower than the melting point of the metal, and can be brought into a bulk state. For example, when silver nanoparticles are used, the sintering temperature of silver nanoparticles is 200 ° C., which is equivalent to the bonding temperature, with respect to the melting point of silver of 960.8 ° C. When using a silver filler with a micron size particle size, the particles trapped under the terminals should be deformed by applying a high load, and good conduction should be ensured unless the contact area between the particles is increased. I can't. On the other hand, when nanoparticles are used, a good contact state with the terminals can be obtained without applying a load by sintering between the particles at the bonding temperature. Further, when a metal such as tin that can be alloyed with the terminal or the substrate electrode is used, an alloyed layer can be formed at a low temperature of 200 ° C., so that the bonding between the terminal of the semiconductor element and the electrode of the substrate becomes stronger.

本発明に係る半導体装置の製造方法は、前記合成樹脂は、エポキシ樹脂であることを特徴とする。 In the method of manufacturing a semiconductor device according to the present invention, the synthetic resin is an epoxy resin .

本発明の半導体装置の製造方法にあっては、金属粒子を分散させる合成樹脂としてエポキシ樹脂を使用する。よって、金属粒子が焼結したときの材料強度だけでなく、エポキシ樹脂の硬化時の強度も加わり、接合強度がより向上する。 In the method for manufacturing a semiconductor device of the present invention, an epoxy resin is used as a synthetic resin for dispersing metal particles. Therefore, not only the material strength when the metal particles are sintered but also the strength at the time of curing of the epoxy resin is added, and the bonding strength is further improved.

本発明に係る半導体装置の製造方法は、前記半導体素子の端子及び／または前記基板の電極は金であり、前記金属粒子として錫粒子を用いて、焼結時に金と錫との合金化層を形成することを特徴とする。
本発明の半導体装置の製造方法にあっては、錫粒子は金と合金化されながら焼結して合金化層を形成するため、より強力な接合が得られる。 In the method of manufacturing a semiconductor device according to the present invention, the terminal of the semiconductor element and / or the electrode of the substrate is gold, tin particles are used as the metal particles, and an alloying layer of gold and tin is formed during sintering. It is characterized by forming.
In the method of manufacturing a semiconductor device of the present invention, tin particles are sintered while being alloyed with gold to form an alloyed layer, so that stronger bonding can be obtained.

本発明の半導体装置の製造方法では、半導体素子の端子と基板の電極との間に合成樹脂中に分散させたナノ粒径の金属粒子を介在させ、金属粒子を焼結させ、合成樹脂を硬化させて、前記端子と前記電極との電気的接続を低荷重下で得るようにしたので、狭ピッチの端子を有する半導体素子についても、半導体素子及び基板間のクリアランスを損なうことなく、良好な電気的接続を実現することができる。また、合成樹脂中にナノ粒径の金属粒子を分散させた構成としたので、焼結した金属粒子による強度だけでなく、合成樹脂の硬化時の強度も加えることができ、半導体素子の端子と基板の電極との電気的接続をより良好にすることができる。また、半導体素子の端子と基板の電極とを接続した後に、端子と電極との電気的接続が得られていない半導体素子と基板との間隙に封止用の合成樹脂を注入するようにしたので、端子と電極との電気的接続状態を安定化することができる。 In the method for manufacturing a semiconductor device of the present invention, metal particles having a nano particle size dispersed in a synthetic resin are interposed between a terminal of a semiconductor element and an electrode of a substrate, the metal particles are sintered, and the synthetic resin is cured. As a result, the electrical connection between the terminal and the electrode is obtained under a low load. Therefore, even in a semiconductor element having a narrow pitch terminal, a good electrical property can be obtained without impairing the clearance between the semiconductor element and the substrate. Connection can be realized. In addition, since the nano-sized metal particles are dispersed in the synthetic resin, not only the strength due to the sintered metal particles but also the strength when the synthetic resin is cured can be added. The electrical connection with the electrode of the substrate can be made better. Also, after connecting the terminal of the semiconductor element and the electrode of the substrate, the sealing synthetic resin is injected into the gap between the semiconductor element and the substrate where the electrical connection between the terminal and the electrode is not obtained. The electrical connection state between the terminal and the electrode can be stabilized.

本発明の半導体装置の製造方法では、半導体素子の端子及び／または基板の電極と合金化するナノ粒径の金属粒子を使用するようにしたので、合金化層によって、半導体素子の端子と基板の電極との電気的接続をより良好にすることができる。   In the method of manufacturing a semiconductor device according to the present invention, metal particles having a nano particle size that is alloyed with the terminals of the semiconductor element and / or the electrodes of the substrate are used. The electrical connection with the electrode can be made better.

本発明の半導体装置の製造方法では、合成樹脂としてエポキシ樹脂を使用するようにしたので、金属粒子が焼結したときの材料強度だけでなく、エポキシ樹脂の硬化時の強度も加わり、接合強度をより向上することができる。 In the semiconductor device manufacturing method of the present invention, since an epoxy resin is used as a synthetic resin, not only the material strength when the metal particles are sintered, but also the strength at the time of curing of the epoxy resin, the bonding strength is increased. It can be improved further.

本発明の半導体装置の製造方法では、半導体素子の端子及び／または前記基板の電極は金であり、金属粒子として錫粒子を用いるようにしたので、錫粒子は金と合金化されながら焼結して合金化層を形成するため、より強力な接合を得ることができる。 In the method for manufacturing a semiconductor device of the present invention, the terminal of the semiconductor element and / or the electrode of the substrate is gold, and tin particles are used as the metal particles. Therefore, the tin particles are sintered while being alloyed with gold. Since the alloying layer is formed, stronger bonding can be obtained.

以下、本発明をその実施の形態を示す図面を参照して具体的に説明する。なお、本発明は以下の実施の形態に限定されるものではない。   Hereinafter, the present invention will be described in detail with reference to the drawings showing embodiments thereof. Note that the present invention is not limited to the following embodiments.

まず、本発明の半導体装置の製造方法における接合原理について説明する。図１（ａ），（ｂ）は、この接合原理を説明するための図である。   First, the bonding principle in the semiconductor device manufacturing method of the present invention will be described. FIGS. 1A and 1B are diagrams for explaining the joining principle.

図１（ａ）において、１は半導体素子としてのＬＳＩチップであり、ＬＳＩチップ１には端子としての金バンプ２が設けられている。この金バンプ２には、Ａｇナノ粒子またはＳｎナノ粒子からなるナノ粒径（５０〜２００ｎｍ程度）の金属粒子１１をエポキシ樹脂１２中に分散させてなる接合材料３が転写されている。また、４はシリコン製の基板であり、基板４には、Ｃｕ／Ｎｉ／Ａｕの３層構造からなる電極５が設けられている。   In FIG. 1A, reference numeral 1 denotes an LSI chip as a semiconductor element, and the LSI chip 1 is provided with gold bumps 2 as terminals. A bonding material 3 in which metal particles 11 having a nano particle diameter (about 50 to 200 nm) made of Ag nanoparticles or Sn nanoparticles are dispersed in an epoxy resin 12 is transferred to the gold bumps 2. Reference numeral 4 denotes a silicon substrate, and the substrate 4 is provided with an electrode 5 having a three-layer structure of Cu / Ni / Au.

このような構成の半導体素子１とを基板４とを、接合材料３と電極５とが対向するように位置決めして、２００℃で加熱しながら１９．６Ｎの荷重で接合させる（図１（ｂ）参照）。これにより、金属粒子１１はセラミックのように焼結し、粒子同士が結合して低温焼結による金属間結合が得られる。   The semiconductor element 1 having such a structure is positioned so that the bonding material 3 and the electrode 5 face each other and bonded with a load of 19.6 N while being heated at 200 ° C. (FIG. 1B). )reference). As a result, the metal particles 11 are sintered like a ceramic, and the particles are bonded to each other to obtain an intermetallic bond by low-temperature sintering.

本発明では、ナノ粒径の金属粒子１１の焼結によって、ＬＳＩチップ１の金バンプ２と基板４の電極との電気的接続を得るので、低荷重下にあっても良好な接合状態を容易に実現することが可能である。   In the present invention, since the metal bumps 11 of the LSI chip 1 are electrically connected to the electrodes of the substrate 4 by sintering the metal particles 11 having a nano particle size, a good bonded state can be easily obtained even under a low load. Can be realized.

次に、金属粒子１１としてＡｇナノ粒子を用いた場合とＳｎナノ粒子を用いた場合とにおける接合部の構造の違いについて説明する。図２（ａ）はＡｇナノ粒子を用いた場合の接合部の構造、図２（ｂ）はＳｎナノ粒子を用いた場合の接合部の構造をそれぞれ示している。   Next, the difference in the structure of the joint between the case where Ag nanoparticles are used as the metal particles 11 and the case where Sn nanoparticles are used will be described. FIG. 2 (a) shows the structure of the joint when Ag nanoparticles are used, and FIG. 2 (b) shows the structure of the joint when Sn nanoparticles are used.

Ａｇナノ粒子を用いた場合には、図２（ａ）に示すように、金バンプ２（端子）のＡｕ領域２１と電極５のＡｕ層２２との間に、Ａｇナノ粒子（金属粒子１１）が焼結したＡｇ領域２３が介在している。これに対して、Ｓｎナノ粒子を用いた場合には、図２（ｂ）に示すように、金バンプ２（端子）のＡｕ領域２１と電極５のＮｉ層２４との間に、電極５のＡｕ層２２及びＳｎナノ粒子（金属粒子１１）が合金化して焼結したＡｕＳｎ領域２５と、Ｓｎナノ粒子（金属粒子１１）単体が焼結したＳｎ領域２６とが混在している。   When Ag nanoparticles are used, as shown in FIG. 2A, Ag nanoparticles (metal particles 11) are disposed between the Au region 21 of the gold bump 2 (terminal) and the Au layer 22 of the electrode 5. An Ag region 23 is sintered. On the other hand, when Sn nanoparticles are used, as shown in FIG. 2B, between the Au region 21 of the gold bump 2 (terminal) and the Ni layer 24 of the electrode 5, the electrode 5 The AuSn region 25 in which the Au layer 22 and the Sn nanoparticles (metal particles 11) are alloyed and sintered, and the Sn region 26 in which the Sn nanoparticles (metal particles 11) alone are sintered are mixed.

このようにＳｎナノ粒子は、Ａｕと合金化してＡｕＳｎに変化しながら焼結する。Ｓｎナノ粒子を用いる場合には、合金化層を形成するため、Ａｕと合金化しないＡｇナノ粒子を用いる場合に比べて、より強力な接合を得ることができる。なお、上述した例では、Ｓｎナノ粒子が電極５のＡｕ層２２と合金化することとしたが、Ｓｎナノ粒子は焼結時に金バンプ２（端子）と合金化することも起こり得る。   As described above, the Sn nanoparticles are alloyed with Au and sintered while changing to AuSn. When Sn nanoparticles are used, an alloyed layer is formed, so that stronger bonding can be obtained as compared with the case where Ag nanoparticles that are not alloyed with Au are used. In the example described above, the Sn nanoparticles are alloyed with the Au layer 22 of the electrode 5, but the Sn nanoparticles may be alloyed with the gold bumps 2 (terminals) during sintering.

以下、本発明の半導体装置の製造方法の具体的な実施の形態について説明する。
（実施の形態１）
図３は、実施の形態１による製造方法の工程を示す図である。まず、粒子径：１００ｎｍの金属ナノ粒子（Ａｇナノ粒子またはＳｎナノ粒子）をエポキシ樹脂に分散させてなる接合材料３を、転写ステージ３１上に形成する（図３（ａ））。この転写ステージ３１には、スキージ（図示せず）が取り付けられており、転写ステージ３１とスキージとのギャップにより、接点材料３の厚さを制御できる。 Hereinafter, specific embodiments of the method for manufacturing a semiconductor device of the present invention will be described.
(Embodiment 1)
FIG. 3 is a diagram illustrating the steps of the manufacturing method according to the first embodiment. First, the bonding material 3 in which metal nanoparticles (Ag nanoparticles or Sn nanoparticles) having a particle size of 100 nm are dispersed in an epoxy resin is formed on the transfer stage 31 (FIG. 3A). A squeegee (not shown) is attached to the transfer stage 31, and the thickness of the contact material 3 can be controlled by a gap between the transfer stage 31 and the squeegee.

ＬＳＩチップ１（半導体素子）は、１辺８．５ｍｍの矩形状であって、５０μｍ間隔で６８０個の金バンプ２（端子）が形成されている。また、金バンプ２（端子）の高さは３０μｍである。このため、転写ステージ３１とスキージとの間隔を１０μｍに設定し、ＬＳＩチップ１を４．９Ｎの荷重で転写ステージ３１上に押しつけ、ＬＳＩチップ１の各金バンプ２に接点材料３を転写する（図３（ａ））。   The LSI chip 1 (semiconductor element) has a rectangular shape with a side of 8.5 mm, and 680 gold bumps 2 (terminals) are formed at intervals of 50 μm. The height of the gold bump 2 (terminal) is 30 μm. For this reason, the distance between the transfer stage 31 and the squeegee is set to 10 μm, the LSI chip 1 is pressed onto the transfer stage 31 with a load of 4.9 N, and the contact material 3 is transferred to each gold bump 2 of the LSI chip 1 ( FIG. 3 (a)).

そして、フリップチップボンダ（ＦＣＢ−２、パナソニックＦＳエンジニアリング製）を用いて、接点材料３が転写されたＬＳＩチップ１を、電極５が設けられた基板４（ＢＴレジン製、厚さ０．３５ｍｍ）と位置合せし、加熱温度２００℃、荷重１９．６Ｎの条件で１０秒間の接合を行う（図３（ｂ））。   Then, using a flip chip bonder (FCB-2, manufactured by Panasonic FS Engineering), the LSI chip 1 to which the contact material 3 has been transferred is transferred to the substrate 4 (made of BT resin, thickness 0.35 mm) on which the electrode 5 is provided. And bonding for 10 seconds under the conditions of a heating temperature of 200 ° C. and a load of 19.6 N (FIG. 3B).

その後、ＬＳＩチップ１と基板４との間隙に、封止用の合成樹脂である封止樹脂３２（Ｕ８４４３、ナミックス製）を、６０℃に加熱したホットプレート上で注入し（図３（ｃ））、注入した封止樹脂３２を１５０℃で２時間硬化させる（図３（ｄ））。   Thereafter, sealing resin 32 (U8443, manufactured by NAMICS), which is a synthetic resin for sealing, is injected into the gap between the LSI chip 1 and the substrate 4 on a hot plate heated to 60 ° C. (FIG. 3C). ), And the injected sealing resin 32 is cured at 150 ° C. for 2 hours (FIG. 3D).

（実施の形態２）
図４は、実施の形態２による製造方法の工程を示す図である。まず、実施の形態１と同一の条件にて、ＬＳＩチップ１の各金バンプ２に接点材料３を転写する（図４（ａ））。次に、１２０℃の温度で、接点材料３中の溶剤成分の除去と金属ナノ粒子の仮焼成とを行う（図４（ｂ））。 (Embodiment 2)
FIG. 4 is a diagram illustrating the steps of the manufacturing method according to the second embodiment. First, the contact material 3 is transferred to each gold bump 2 of the LSI chip 1 under the same conditions as in the first embodiment (FIG. 4A). Next, removal of the solvent component in the contact material 3 and temporary firing of the metal nanoparticles are performed at a temperature of 120 ° C. (FIG. 4B).

一方、電極５が設けられた基板４（ＢＴレジン製、厚さ０．３５ｍｍ）上に、塗布機（ＦＡＤ３２０ｓ、武蔵エンジニアリング製）を用いて、封止樹脂３３（ＵＦＲ１０７、ナガセケムテックス製）を塗布する（図４（ｃ））。   On the other hand, the sealing resin 33 (UFR107, manufactured by Nagase ChemteX) is applied to the substrate 4 (made of BT resin, thickness: 0.35 mm) provided with the electrode 5 using a coating machine (FAD320s, manufactured by Musashi Engineering). Apply (FIG. 4C).

そして、フリップチップボンダ（ＦＣＢ−２、パナソニックＦＳエンジニアリング製）を用いて、接点材料３が転写されたＬＳＩチップ１と、封止樹脂３３が塗布された基板４とを位置合せし、加熱温度２００℃、荷重１９．６Ｎの条件で１０秒間の接合を行った後、恒温槽を用いて１５０℃で２時間、封止樹脂３３を硬化させる（図４（ｄ））。この封止樹脂３３の硬化時に、同時に金属ナノ粒子が焼成される。   Then, using a flip chip bonder (FCB-2, manufactured by Panasonic FS Engineering), the LSI chip 1 to which the contact material 3 is transferred and the substrate 4 to which the sealing resin 33 is applied are aligned, and the heating temperature is 200. After joining for 10 seconds under the conditions of ° C. and a load of 19.6 N, the sealing resin 33 is cured at 150 ° C. for 2 hours using a thermostatic bath (FIG. 4D). At the same time as the sealing resin 33 is cured, the metal nanoparticles are fired.

上記第１実施の形態では、ＬＳＩチップ１（半導体素子）と基板４とを接合した後に、封止樹脂を注入するようにしているが、封止樹脂を注入して硬化させるまでの間、ＬＳＩチップ１（半導体素子）と基板４との熱膨張係数の差から生じる応力をサイズが小さい金バンプ２（端子）のみで支えなければならず、金バンプ２（端子）が破断する可能性が皆無とは言えない。これに対して、上記第２実施の形態では、予め基板４上に封止樹脂を塗布し、封止樹脂の硬化と金属ナノ粒子の焼結とを同時に行うようにしているので、接合部に加わる応力を封止樹脂内に分散させることにより、接合信頼性を向上することができる。   In the first embodiment, the sealing resin is injected after the LSI chip 1 (semiconductor element) and the substrate 4 are joined, but the LSI is injected until the sealing resin is injected and cured. The stress generated from the difference in thermal expansion coefficient between the chip 1 (semiconductor element) and the substrate 4 must be supported only by the small-sized gold bumps 2 (terminals), and there is no possibility of the gold bumps 2 (terminals) breaking. It can not be said. On the other hand, in the second embodiment, the sealing resin is applied on the substrate 4 in advance, and the sealing resin is cured and the metal nanoparticles are simultaneously sintered. By dispersing the applied stress in the sealing resin, the bonding reliability can be improved.

（比較例）
金バンプ（端子）に荷重をかけると同時に、合成樹脂（接着剤）の硬化を行う圧接方式を用いて、比較例を製造する。塗布機（ＦＡＤ３２０ｓ、武蔵エンジニアリング製）を用いて、実施の形態１，２と同様の基板上に封止樹脂（ＵＦＲ１０７、ナガセケムテックス製）を塗布し、フリップチップボンダ（ＦＣＢ−２、パナソニックＦＳエンジニアリング製）を用いて、実施の形態１，２と同様のＬＳＩチップ（半導体素子）と封止樹脂が塗布された基板とを位置合せし、加熱温度２００℃、荷重１９．６Ｎまたは荷重７８．４Ｎの条件で１０秒間の接合を行った後、恒温槽を用いて１５０℃で２時間、封止樹脂を硬化させる。 (Comparative example)
A comparative example is manufactured using a pressure contact method in which a load is applied to the gold bump (terminal) and at the same time the synthetic resin (adhesive) is cured. Using a coating machine (FAD320s, manufactured by Musashi Engineering Co., Ltd.), a sealing resin (UFR107, manufactured by Nagase ChemteX) is applied on the same substrate as in the first and second embodiments, and a flip chip bonder (FCB-2, Panasonic FS). The LSI chip (semiconductor element) similar to that of the first and second embodiments and the substrate coated with the sealing resin are aligned using the engineering), the heating temperature is 200 ° C., the load is 19.6 N, or the load is 78. After bonding for 10 seconds under the condition of 4N, the sealing resin is cured for 2 hours at 150 ° C. using a thermostatic bath.

次に、以上のような実施の形態１，２及び比較例の製造方法によって製造した各半導体装置の特性を評価するために行った各種の評価試験の内容と結果とについて説明する。なお、以下では、実施の形態１の製造方法によって製造した半導体装置を実施例１、実施の形態２の製造方法によって製造した半導体装置を実施例２、接合時の荷重を１９．６Ｎとして比較例によって製造した半導体装置を比較例１、接合時の荷重を７８．４Ｎとして比較例によって製造した半導体装置を比較例２と略記する。   Next, the contents and results of various evaluation tests performed for evaluating the characteristics of the semiconductor devices manufactured by the manufacturing methods of the first and second embodiments and the comparative example as described above will be described. In the following, the semiconductor device manufactured by the manufacturing method of the first embodiment is in Example 1, the semiconductor device manufactured by the manufacturing method of the second embodiment is in Example 2, and the load at the time of bonding is 19.6 N as a comparative example. The semiconductor device manufactured by the above method is abbreviated as Comparative Example 1, and the semiconductor device manufactured by the Comparative Example with a load at the time of bonding of 78.4 N is abbreviated as Comparative Example 2.

接合信頼性の評価には、接合信頼性試験項目である吸湿−リフロー性評価を模擬的に行う模擬吸湿リフロー試験を実施した。模擬吸湿−リフローの評価方法は、実装後の各サンプルを温度８５℃、湿度８５％、時間１２時間で吸湿させた後、リフロー工程の最大温度である２５０℃に維持したホットプレート上で２分間放置した。調査方法は、実装後及び模擬吸湿−リフロー後の電気的導通の変化を測定した。このときの合否判定は、導通抵抗の上昇率が５％以下とした。実施例１、実施例２、比較例１及び比較例２のそれぞれについて、５０サンプルずつ、この接合信頼性の評価を行った。   For the evaluation of the bonding reliability, a simulated moisture absorption reflow test was performed in which a moisture absorption-reflow property evaluation, which is a bonding reliability test item, was simulated. The simulated moisture absorption-reflow evaluation method was as follows: each sample after mounting was absorbed at a temperature of 85 ° C. and a humidity of 85% for 12 hours and then kept on a hot plate maintained at 250 ° C., the maximum temperature of the reflow process, for 2 minutes I left it alone. The investigation method measured changes in electrical continuity after mounting and after simulated moisture absorption and reflow. In the pass / fail judgment at this time, the increase rate of the conduction resistance was set to 5% or less. For each of Example 1, Example 2, Comparative Example 1 and Comparative Example 2, this bonding reliability was evaluated for 50 samples.

この結果、実施例１及び実施例２に関しては、すべてのサンプルで導通抵抗の上昇率が５％以下であり、良好な接合信頼性が得られた。これに対して、比較例１に関しては、５０サンプル中２８サンプルが不良となり、比較例２に関しては、５０サンプル中３サンプルが不良となった。   As a result, with respect to Example 1 and Example 2, the increase rate of the conduction resistance was 5% or less in all the samples, and good bonding reliability was obtained. On the other hand, regarding Comparative Example 1, 28 samples out of 50 samples were defective, and regarding Comparative Example 2, 3 samples out of 50 samples were defective.

上記各サンプルについて、超音波映像装置（ＦＳ２００、日立建機ファインテック製）を用いて接合部の状態を観察した。比較例２のサンプルでは、接合部のＬＳＩチップ（半導体素子）中央部に剥離が観察できた。このサンプルを断面研磨し、ＳＥＭを用いて観察した結果、接合部の中央に、異物（シリコンウェハをダイシングした際に生じる屑など）を起点とした剥離が生じていた。このときのＬＳＩチップ（半導体素子）と基板とのクリアランスは、４μｍしかなかった。   About each said sample, the state of the junction part was observed using the ultrasonic imaging device (FS200, Hitachi Construction Machinery Finetech). In the sample of Comparative Example 2, peeling was observed at the center of the LSI chip (semiconductor element) at the joint. As a result of cross-sectional polishing of this sample and observation using an SEM, peeling occurred from a foreign material (such as dust generated when a silicon wafer was diced) at the center of the joint. At this time, the clearance between the LSI chip (semiconductor element) and the substrate was only 4 μm.

比較例１の不良サンプルを断面研磨し、観察した結果、金バンプ（端子）と基板の電極との接触部に浮きが見られた。金バンプの潰れ量が少なかったため、接合荷重不足により、接合部が断線したものと考えられる。また、このときのＬＳＩチップ（半導体素子）と基板とのクリアランスは平均で１３μｍであった。   As a result of observing the cross section of the defective sample of Comparative Example 1 and observing it, floating was observed at the contact portion between the gold bump (terminal) and the electrode of the substrate. Since the amount of collapse of the gold bumps was small, it is considered that the joint was disconnected due to insufficient joint load. The clearance between the LSI chip (semiconductor element) and the substrate at this time was 13 μm on average.

接合信頼性が良好であった実施例１及び実施例２のサンプルについても、断面研磨した後に観察したが、剥離は発生しておらず良好な接合を維持できていた。また、このときのＬＳＩチップ（半導体素子）と基板とのクリアランスは約１４μｍであり、接合信頼性と半導体素及び基板のクリアランスとの確保を両立できた。   The samples of Examples 1 and 2 that had good bonding reliability were also observed after cross-sectional polishing, but no peeling occurred and good bonding could be maintained. In addition, the clearance between the LSI chip (semiconductor element) and the substrate at this time was about 14 μm, and it was possible to ensure both the junction reliability and the clearance between the semiconductor element and the substrate.

なお、上述した例では、ナノ粒子径の金属粒子としてナノＡｇ粒子またはナノＳｎ粒子を用いることとしたが、これらのナノＡｇ粒子及びナノＳｎ粒子を混有させても良く、Ａｇ，Ｓｎ以外に、Ｂｉ，Ｚｎ，Ｎｉ，Ｉｎなどの金属製のナノ粒子を使用するようにしても良い。   In the above-described example, nano Ag particles or nano Sn particles are used as the metal particles having a nano particle diameter. However, these nano Ag particles and nano Sn particles may be mixed, and other than Ag and Sn. Metal nanoparticles such as Bi, Zn, Ni, and In may be used.

以上の本発明の実施の形態に関し、更に以下の付記を開示する。
（付記１） 半導体素子の端子と基板の電極とを接続させる半導体装置の製造方法において、前記端子と前記電極との間にナノ粒径の金属粒子を介在させ、該金属粒子を焼結させて前記端子と前記電極との電気的接続を得ることを特徴とする半導体装置の製造方法。 Regarding the above-described embodiment of the present invention, the following additional notes are disclosed.
(Additional remark 1) In the manufacturing method of the semiconductor device which connects the terminal of a semiconductor element, and the electrode of a board | substrate, interposing the metal particle of a nano particle size between the said terminal and the said electrode, and sintering this metal particle A method of manufacturing a semiconductor device, wherein electrical connection between the terminal and the electrode is obtained.

（付記２） 前記金属粒子として、前記端子及び／または前記電極と合金化する金属粒子を使用することを特徴とする付記１記載の半導体装置の製造方法。   (Supplementary note 2) The semiconductor device manufacturing method according to supplementary note 1, wherein metal particles that are alloyed with the terminals and / or the electrodes are used as the metal particles.

（付記３） 前記金属粒子を合成樹脂中に分散させた材料を前記端子に転写することを特徴とする付記１または２記載の半導体装置の製造方法。   (Additional remark 3) The material which disperse | distributed the said metal particle in a synthetic resin is transcribe | transferred to the said terminal, The manufacturing method of the semiconductor device of Additional remark 1 or 2 characterized by the above-mentioned.

（付記４） 前記端子と前記電極とを接続した後に、前記半導体素子と前記基板との間に封止用の合成樹脂を注入することを特徴とする付記１乃至３の何れかに記載の半導体装置の製造方法。   (Additional remark 4) After connecting the said terminal and the said electrode, the synthetic resin for sealing is inject | poured between the said semiconductor element and the said board | substrate, The semiconductor in any one of additional remark 1 thru | or 3 characterized by the above-mentioned. Device manufacturing method.

（付記５） 前記基板上に封止用の合成樹脂を予め形成しておき、前記端子と前記電極との接続、及び前記合成樹脂の硬化とを同時的に行うことを特徴とする付記１乃至３の何れかに記載の半導体装置の製造方法。   (Additional remark 5) The synthetic resin for sealing is previously formed on the said board | substrate, the connection of the said terminal and the said electrode, and the hardening of the said synthetic resin are performed simultaneously, Additional remark 1 thru | or 1 characterized by the above-mentioned. 4. A method for manufacturing a semiconductor device according to any one of 3 above.

（付記６） 前記金属粒子の構成金属は、銀，錫，ビスマス，亜鉛，ニッケル，インジウムからなる群から選ばれた金属を少なくとも１種類含むことを特徴とする付記１乃至５の何れかに記載の半導体装置の製造方法。   (Supplementary note 6) The constituent metal of the metal particles includes at least one metal selected from the group consisting of silver, tin, bismuth, zinc, nickel, and indium. Semiconductor device manufacturing method.

（付記７） 前記金属粒子の焼結温度は２５０℃以下であることを特徴とする付記１乃至６の何れかに記載の半導体装置の製造方法。   (Additional remark 7) The sintering temperature of the said metal particle is 250 degrees C or less, The manufacturing method of the semiconductor device in any one of Additional remark 1 thru | or 6 characterized by the above-mentioned.

（付記８） 付記１乃至７の何れかに記載の半導体装置の製造方法によって製造されたことを特徴とする半導体装置。   (Appendix 8) A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of appendices 1 to 7.

本発明の半導体装置の製造方法における接合原理を説明するための図である。It is a figure for demonstrating the joining principle in the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法における接合部の構造を示す図である。It is a figure which shows the structure of the junction part in the manufacturing method of the semiconductor device of this invention. 実施の形態１による製造方法の工程を示す図である。5 is a diagram showing a process of the manufacturing method according to Embodiment 1. FIG. 実施の形態２による製造方法の工程を示す図である。It is a figure which shows the process of the manufacturing method by Embodiment 2. FIG.

符号の説明Explanation of symbols

１ ＬＳＩチップ（半導体素子）
２ 金バンプ（端子）
３ 接合材料
４ 基板
５ 電極
１１ 金属粒子
１２ エポキシ樹脂（合成樹脂）
３１ 転写ステージ
３２，３３ 封止樹脂 1 LSI chip (semiconductor element)
2 Gold bump (terminal)
3 Bonding Material 4 Substrate 5 Electrode 11 Metal Particle 12 Epoxy Resin (Synthetic Resin)
31 Transfer stage 32, 33 Sealing resin

Claims (4)

半導体素子の端子と基板の電極とを接続させる半導体装置の製造方法において、
前記端子と前記電極との間に合成樹脂中に分散させたナノ粒径の金属粒子を介在させ、該金属粒子を焼結させ、前記合成樹脂を硬化させて前記端子と前記電極との電気的接続を得ることとし、前記端子と前記電極とを接続した後に、前記端子と前記電極との電気的接続が得られていない前記半導体素子と前記基板との間隙に封止用の合成樹脂を注入することを特徴とする半導体装置の製造方法。 In a manufacturing method of a semiconductor device for connecting a terminal of a semiconductor element and an electrode of a substrate,
Nano-sized metal particles dispersed in a synthetic resin are interposed between the terminal and the electrode, the metal particle is sintered, and the synthetic resin is cured to electrically connect the terminal and the electrode. After connecting the terminal and the electrode, a synthetic resin for sealing is injected into the gap between the semiconductor element and the substrate where electrical connection between the terminal and the electrode is not obtained. A method of manufacturing a semiconductor device. 前記金属粒子として、前記端子及び／または前記電極と合金化する金属粒子を使用することを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein metal particles that are alloyed with the terminals and / or the electrodes are used as the metal particles. 前記合成樹脂は、エポキシ樹脂であることを特徴とする請求項１または２記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the synthetic resin is an epoxy resin. 前記半導体素子の端子及び／または前記基板の電極は金であり、前記金属粒子として錫粒子を用いて、焼結時に金と錫との合金化層を形成することを特徴とする請求項１乃至３の何れかに記載の半導体装置の製造方法。 The terminal of the said semiconductor element and / or the electrode of the said board | substrate are gold | metal | money, The alloying layer of gold | metal | money and tin is formed at the time of sintering using the tin particle as the said metal particle, The 1 thru | or characterized by the above-mentioned. 4. A method for manufacturing a semiconductor device according to any one of 3 above.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4361572B2 (en) 2007-02-28 2009-11-11 株式会社新川 Bonding apparatus and method
JP5151584B2 (en) * 2008-03-17 2013-02-27 富士通株式会社 Semiconductor device and manufacturing method of semiconductor device
JP5363839B2 (en) * 2008-05-12 2013-12-11 田中貴金属工業株式会社 Bump, method for forming bump, and method for mounting substrate on which bump is formed
KR101004843B1 (en) 2008-09-05 2010-12-28 삼성전기주식회사 Ceramic multi-layer circuit substrate and manufacturing method thereof
JP5322774B2 (en) * 2009-05-25 2013-10-23 パナソニック株式会社 Mounting structure and manufacturing method thereof
KR101051045B1 (en) 2009-06-02 2011-07-21 중앙대학교 산학협력단 Terminal connection method using conductive adhesive
CN101593712B (en) * 2009-06-26 2012-01-04 天津大学 Low-temperature sintering method for high-power chip connection and nano silver paste thickness control device
JP5664028B2 (en) * 2010-08-31 2015-02-04 富士通株式会社 Manufacturing method of electronic device
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JP2016157707A (en) * 2013-07-09 2016-09-01 株式会社ダイセル Semiconductor device arranged by use of silver nanoparticles, and manufacturing method thereof
JP6262968B2 (en) 2013-09-09 2018-01-17 Ｄｏｗａメタルテック株式会社 Electronic component mounting substrate and manufacturing method thereof
JP6255949B2 (en) * 2013-11-29 2018-01-10 富士通株式会社 Bonding method and semiconductor device manufacturing method
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FR3047111B1 (en) * 2016-01-26 2018-03-23 Commissariat A L'energie Atomique Et Aux Energies Alternatives ASSEMBLY COMPRISING MIXED INTERCONNECT MEANS COMPRISING INTERMEDIATE INTERCONNECTION ELEMENTS AND METAL SINTERED JOINTS AND METHOD OF MANUFACTURE
US20190011497A1 (en) * 2017-07-09 2019-01-10 Texas Instruments Incorporated Test Fixture with Sintered Connections Between Mother Board and Daughter Board
JP7199921B2 (en) * 2018-11-07 2023-01-06 ローム株式会社 semiconductor equipment
JP2020107711A (en) * 2018-12-27 2020-07-09 日東電工株式会社 Semiconductor device manufacturing method
WO2023153163A1 (en) * 2022-02-09 2023-08-17 パナソニックＩｐマネジメント株式会社 Flip-chip mounting structure and flip-chip mounting method

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10150073A (en) * 1996-11-15 1998-06-02 Sony Corp Manufacture of printed circuit board
JPH1167839A (en) * 1997-08-22 1999-03-09 Seiko Epson Corp Manufacture of electronic equipment
JP2002329958A (en) * 2001-04-27 2002-11-15 Casio Comput Co Ltd Method of joining circuit board
JP2004146731A (en) * 2002-10-28 2004-05-20 Mitsubishi Electric Corp Manufacturing method of multilayer wiring substrate
JP2004297001A (en) * 2003-03-28 2004-10-21 Nippon Steel Chem Co Ltd Method of manufacturing electronic device
JP2005136399A (en) * 2003-10-07 2005-05-26 Matsushita Electric Ind Co Ltd Semiconductor device mounting method and mounting substrate of semiconductor device
JP2005203468A (en) * 2004-01-14 2005-07-28 Seiko Epson Corp Electronic device and its manufacturing method
JP2005302877A (en) * 2004-04-08 2005-10-27 Denso Corp Method for manufacturing electronic device
JP2007184408A (en) * 2006-01-06 2007-07-19 Nec Corp Electrode bonding method
JP2008235926A (en) * 2004-11-11 2008-10-02 Seiko Epson Corp Mounting board and electronic equipment

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10150073A (en) * 1996-11-15 1998-06-02 Sony Corp Manufacture of printed circuit board
JPH1167839A (en) * 1997-08-22 1999-03-09 Seiko Epson Corp Manufacture of electronic equipment
JP2002329958A (en) * 2001-04-27 2002-11-15 Casio Comput Co Ltd Method of joining circuit board
JP2004146731A (en) * 2002-10-28 2004-05-20 Mitsubishi Electric Corp Manufacturing method of multilayer wiring substrate
JP2004297001A (en) * 2003-03-28 2004-10-21 Nippon Steel Chem Co Ltd Method of manufacturing electronic device
JP2005136399A (en) * 2003-10-07 2005-05-26 Matsushita Electric Ind Co Ltd Semiconductor device mounting method and mounting substrate of semiconductor device
JP2005203468A (en) * 2004-01-14 2005-07-28 Seiko Epson Corp Electronic device and its manufacturing method
JP2005302877A (en) * 2004-04-08 2005-10-27 Denso Corp Method for manufacturing electronic device
JP2008235926A (en) * 2004-11-11 2008-10-02 Seiko Epson Corp Mounting board and electronic equipment
JP2007184408A (en) * 2006-01-06 2007-07-19 Nec Corp Electrode bonding method

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