JP4701085B2 - シリコン・オン・インシュレータ・ウェハを製造するための方法 - Google Patents
シリコン・オン・インシュレータ・ウェハを製造するための方法 Download PDFInfo
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- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/005—Bulk micromachining
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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Description
リソグラフィ・プロセス・ウィンドウは、重大な中心からエッジへのデルタ(center-to-edge delta)を示すウェハ・トポグラフィによる影響を最も受ける。また、リソグラフィ・プロセスは、通常、ウェハの中心領域内でレジストをいくらか薄く残すコーティング中に上部中心のフォトレジスト位置による影響も受ける。中心領域がより薄いことにより、形状が収縮するか、ゲートの反転を生じるか、または不完全なレジスト側壁プロファイルを残し、注入の危険、したがって、デバイスの不正確さの危険を冒すことになる。
様々な製造ステップ中にシリコン・オン・インシュレータ・ウェハ10内の埋め込み絶縁体層2内およびそのシリコン境界面の両方に閉じ込められ蓄積された電荷により、最終的に電圧破壊が引き起こされる。このような破壊の厳しさは、絶縁体層2自体の厚さに依存する。電圧破壊の問題に対処するために、均一に輪郭形成された凹形上面8cを有する埋め込み絶縁体層2が提供される。このような構造は図6に図示されている。上面8cは、任意の直径のSOIウェハ10のエッジで任意の最大厚さを有することができる。輪郭形成された凹形上面8cは、ウェハ10の残りの部分と同じ数のチップが印刷されているわけではないウェハ10のエッジに向かって不要な電荷を流すのに役に立つ。
上述の様々な問題に対処するために、被制御厚さおよび混合プロファイル変動のパターン付きトポグラフィを有する埋め込み絶縁体層2が提供される。このような構造は図8に図示されている。絶縁体層2の上面8eは、凸形部分と凹形部分と実質的に平らな部分の任意の組み合わせを有することができる。同様に、絶縁体層2の底面12eは、凸形部分と凹形部分と実質的に平らな部分の任意の組み合わせを有することができる。絶縁体層2の上面8eおよび底面12eは、絶縁体層2の変動する厚さを両者の間で確定する。上面8eおよび底面12eの特定の輪郭形成された部分の特定の位置および長さは、ウェハ10に関する所望のパフォーマンス・パラメータを達成するように選択される。
特に、技術が成熟するにつれて、ウェハ全域にまたはウェハのチップ周期性マップに基づく反復パターンでSOIウェハの絶縁体層上に所定のトポグラフィを選択的に生成するプロセスは、いくつかの適用例において非常に有用である可能性がある。本発明は、半導体処理における伝統的な適用例および新しい適用例の両方をサポートすることができる。具体的には、本発明は、CMOS、バイオチップ、その他の半導体デバイスに関する利点を提供することができる。さらに、より具体的には、本発明は、ゲート長のさらなる低減を可能にすることができる。
Claims (4)
- シリコン・オン・インシュレータ・ウェハ(10)を製造するための方法であって、
(a)シリコン基板(4)を準備するステップと、
(b)酸素注入器(50)により前記シリコン基板(4)内に酸素を注入することにより、前記シリコン基板(4)内に埋め込まれ、上部シリコン層(6)から前記シリコン基板(4)を分離し、上面(8)と底面(12)とを有する酸化物絶縁体層(2)を前記ウェハ(10)全域に形成するステップと、
(c)前記酸素注入器(50)の酸素注入のエネルギー、用量、または温度を調整することにより、前記ウエハ(10)の全域で前記酸化物絶縁体層(2)を厚くするステップと、
(d)前記ウェハ(10)に関するチップ周期性を生成し、前記酸化物絶縁体層(2)の所定のトポグラフィが望まれる座標を設定するステップと、
(e)前記酸素注入器(50)に前記座標を転送するステップと、
(f)前記チップ周期性マップからの前記座標に応じて、前記酸素注入器の酸素注入のエネルギー、用量、又は温度を調整し、前記ウエハ(10)を傾斜又は回転させると共に、イオン注入ビーム(42)を走査することにより、上面全体が凸型形状であり底面が平らである酸化物絶縁体層、上面が凸型領域と平らな領域とを交互に有する形状であり底面が平らである酸化物絶縁体層、上面全体が凹形形状であり底面が平らである酸化物絶縁体層、上面が凹形領域と平らな領域とを交互に有する形状であり底面が平らである酸化物絶縁体層、及び上面が凸形部分と凹形部分と平らな部分とを組み合わせた形状であり底面が凸形部分と凹形部分と平らな部分とを組み合わせた形状である酸化物絶縁体層のうちの1つを形成するステップと、
(g)アニールすることにより、前記酸化物絶縁体層(2)をさらに厚くするステップとを含む、方法。 - 前記ステップ(g)が、酸素環境でのアニールである、請求項1に記載の方法。
- シリコン・オン・インシュレータ・ウェハ(10)を製造するための方法であって、
(a)シリコン基板(4)を準備するステップと、
(b)酸素注入器(50)により前記シリコン基板(4)内に酸素を注入することにより、前記シリコン基板(4)内に埋め込まれ、上部シリコン層(6)から前記シリコン基板(4)を分離し、上面(8)と底面(12)とを有する酸化物絶縁体層(2)を前記ウェハ(10)全域に形成するステップと、
(c)前記酸素注入器(50)の酸素注入のエネルギー、用量、または温度を調整することにより、前記ウエハ(10)の全域で前記酸化物絶縁体層(2)を厚くするステップと、
(d)前記ウェハ(10)に関するチップ周期性を生成し、前記酸化物絶縁体層(2)の所定のトポグラフィが望まれる座標を設定するステップと、
(e)前記酸素注入器(50)に前記座標を転送するステップと、
(f)前記チップ周期性マップからの前記座標に応じて、前記酸素注入器の酸素注入のエネルギー、用量、又は温度を調整し、前記ウエハ(10)を傾斜又は回転させると共に、イオン注入ビーム(42)を走査することにより、上面全体が凸型形状であり底面が平らである酸化物絶縁体層を形成するステップと、
(g)酸素環境でアニールすることにより、前記酸化物絶縁体層(2)をさらに厚くするステップとを含む、方法。 - シリコン・オン・インシュレータ・ウェハ(10)を製造するための方法であって、
(a)シリコン基板(4)を準備するステップと、
(b)酸素注入器(50)により前記シリコン基板(4)内に酸素を注入することにより、前記シリコン基板(4)内に埋め込まれ、上部シリコン層(6)から前記シリコン基板(4)を分離し、上面(8)と底面(12)とを有する酸化物絶縁体層(2)を前記ウェハ(10)全域に形成するステップと、
(c)前記酸素注入器(50)の酸素注入のエネルギー、用量、または温度を調整することにより、前記ウエハ(10)の全域で前記酸化物絶縁体層(2)を厚くするステップと、
(d)前記ウェハ(10)に関するチップ周期性を生成し、前記酸化物絶縁体層(2)の所定のトポグラフィが望まれる座標を設定するステップと、
(e)前記酸素注入器(50)に前記座標を転送するステップと、
(f)前記チップ周期性マップからの前記座標に応じて、前記酸素注入器の酸素注入のエネルギー、用量、又は温度を調整し、前記ウエハ(10)を傾斜又は回転させると共に、イオン注入ビーム(42)を走査することにより、上面全体が凹形形状であり底面が平らである酸化物絶縁体層を形成するステップと、
(g)酸素環境でアニールすることにより、前記酸化物絶縁体層(2)をさらに厚くするステップとを含む、方法。
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PCT/US2003/040079 WO2005062364A1 (en) | 2003-12-16 | 2003-12-16 | Contoured insulator layer of silicon-on-onsulator wafers and process of manufacture |
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US (2) | US7935613B2 (ja) |
EP (1) | EP1695379B1 (ja) |
JP (1) | JP4701085B2 (ja) |
KR (1) | KR100956711B1 (ja) |
CN (1) | CN100466203C (ja) |
AU (1) | AU2003297191A1 (ja) |
WO (1) | WO2005062364A1 (ja) |
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KR100956711B1 (ko) | 2003-12-16 | 2010-05-06 | 인터내셔널 비지네스 머신즈 코포레이션 | 실리콘-온-절연체 웨이퍼의 컨투어화 된 절연체 층 및 이의제조 프로세스 |
DE102007015504B4 (de) | 2007-03-30 | 2014-10-23 | Advanced Micro Devices, Inc. | SOI-Transistor mit Drain- und Sourcegebieten mit reduzierter Länge und einem dazu benachbarten verspannten dielektrischen Material und Verfahren zur Herstellung |
US7955887B2 (en) * | 2008-06-03 | 2011-06-07 | International Business Machines Corporation | Techniques for three-dimensional circuit integration |
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Also Published As
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JP2007524981A (ja) | 2007-08-30 |
US20110101490A1 (en) | 2011-05-05 |
CN1879206A (zh) | 2006-12-13 |
US8405150B2 (en) | 2013-03-26 |
US20100013044A1 (en) | 2010-01-21 |
AU2003297191A1 (en) | 2005-07-14 |
WO2005062364A1 (en) | 2005-07-07 |
EP1695379B1 (en) | 2012-12-05 |
EP1695379A1 (en) | 2006-08-30 |
EP1695379A4 (en) | 2008-06-04 |
US7935613B2 (en) | 2011-05-03 |
KR100956711B1 (ko) | 2010-05-06 |
CN100466203C (zh) | 2009-03-04 |
KR20060118548A (ko) | 2006-11-23 |
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