JP4699311B2 - Chip resistor - Google Patents

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JP4699311B2
JP4699311B2 JP2006224907A JP2006224907A JP4699311B2 JP 4699311 B2 JP4699311 B2 JP 4699311B2 JP 2006224907 A JP2006224907 A JP 2006224907A JP 2006224907 A JP2006224907 A JP 2006224907A JP 4699311 B2 JP4699311 B2 JP 4699311B2
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洋泰 馬場
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太陽社電気株式会社
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本発明はチップ抵抗器に関し、より詳しくは放熱性の向上を図ることのできるチップ抵抗器の構造に関する。   The present invention relates to a chip resistor, and more particularly to a structure of a chip resistor capable of improving heat dissipation.

チップ抵抗器の一形式として、特開２００１−３５７０２号公報には耐熱性絶縁体の表面に一対の電極層を形成し、両電極層を接続するように抵抗体層を形成し、この抵抗体層を両電極層に隣接する高抵抗部分とそれ以外の低抵抗部分から構成したチップ抵抗器が記載されている。
このチップ抵抗器は、配線基板のランドに電極層が対向接触するように実装して使用する。 As a type of chip resistor, Japanese Patent Application Laid-Open No. 2001-35702 discloses a method in which a pair of electrode layers is formed on the surface of a heat-resistant insulator and a resistor layer is formed so as to connect both electrode layers. A chip resistor is described in which the layer is composed of a high resistance portion adjacent to both electrode layers and other low resistance portions.
This chip resistor is mounted and used so that the electrode layer is in opposed contact with the land of the wiring board.

かかる構造のチップ抵抗器によれば、抵抗体のうち発熱量の大きい高抵抗部分を電極層に隣接して設け、電極層をランドに対向接触させることにより、高抵抗部分における発熱を電極層を伝ってランドへと効果的に放熱することができる。
特開２００１−３５７０２号公報 According to the chip resistor having such a structure, the high resistance portion of the resistor having a large calorific value is provided adjacent to the electrode layer, and the electrode layer is brought into contact with the land so as to prevent the heat generation in the high resistance portion from the electrode layer. It is possible to effectively dissipate heat to the land.
JP 2001-35702 A

上記した従来のチップ抵抗器は電極層と抵抗体層の高抵抗部分を隣接して設けているものの、電極層と高抵抗部分は耐熱性絶縁体の表面上で並列に配置されているため、伝熱作用という観点からは熱的に離間している。そのため高抵抗部分の発熱が速やかに電極層へ伝わらないので、放熱効果が不十分である。
本発明はかかる問題点に鑑み、より放熱効果に優れたチップ抵抗器を提供することを目的とする。 Although the above-described conventional chip resistor is provided with the high resistance portion of the electrode layer and the resistor layer adjacent to each other, the electrode layer and the high resistance portion are arranged in parallel on the surface of the heat resistant insulator, It is thermally separated from the viewpoint of heat transfer action. For this reason, the heat generation in the high resistance portion is not quickly transmitted to the electrode layer, so that the heat dissipation effect is insufficient.
The present invention has been made in view of such a problem, and an object of the present invention is to provide a chip resistor having a more excellent heat dissipation effect.

上記目的を達成するために請求項１に記載の発明は、耐熱性絶縁体の表面に一対の主電極層を形成すると共に両電極層を接続するように抵抗体層を形成し、かつ該抵抗体層を前記両主電極層又は少なくとも一方の主電極層に隣接する高発熱部分とそれ以外の低発熱部分で構成したチップ抵抗器であって、前記抵抗体層を絶縁性保護膜で被覆し、かつ該絶縁性保護膜の上から前記抵抗体層の前記主電極層に隣接する部分を補助電極層で被覆したチップ抵抗器であって、
前記補助電極層を第１補助電極層、第２補助電極層、第３補助電極層及び第４補助電極層から構成し、
第１補助電極層と第２補助電極層を一方の主電極層に接続するとともに該主電極層を第１補助電極層と第２補助電極層の間に露出させ、
第３補助電極層と第４補助電極層を他方の主電極層に接続するとともに該主電極層を第３補助電極層と第４補助電極層の間に露出させたことを特徴とする。 In order to achieve the above object, the invention according to claim 1 is characterized in that a pair of main electrode layers are formed on the surface of the heat-resistant insulator, a resistor layer is formed so as to connect both electrode layers, and the resistance A chip resistor comprising a body layer composed of a high heat generating portion adjacent to both the main electrode layers or at least one of the main electrode layers and another low heat generating portion, wherein the resistor layer is covered with an insulating protective film. And a chip resistor in which a portion of the resistor layer adjacent to the main electrode layer is covered with an auxiliary electrode layer from above the insulating protective film,
The auxiliary electrode layer comprises a first auxiliary electrode layer, a second auxiliary electrode layer, a third auxiliary electrode layer, and a fourth auxiliary electrode layer,
Connecting the first auxiliary electrode layer and the second auxiliary electrode layer to one main electrode layer and exposing the main electrode layer between the first auxiliary electrode layer and the second auxiliary electrode layer;
The third auxiliary electrode layer and the fourth auxiliary electrode layer are connected to the other main electrode layer, and the main electrode layer is exposed between the third auxiliary electrode layer and the fourth auxiliary electrode layer.

上記目的を達成するため請求項２に記載の発明は、請求項２に記載のチップ抵抗器において、
前記抵抗体層を一対の幅狭辺と一対の幅広辺から成る四角形の枠形に形成し、
一方の主電極層を一方の幅狭辺の中間部に接続し、他方の主電極層を他方の幅狭辺の中間部に接続し、
前記第１補助電極層で一方の幅狭辺の略半分を被覆するとともに該第１補助電極層を一方の主電極に接続し、
前記第２補助電極層で一方の幅狭辺の残り半分を被覆するとともに該第２補助電極層を一方の主電極層に接続し、
前記第３補助電極層で他方の幅狭辺の略半分を被覆するとともに該第３補助電極層を他方の主電極層に接続し、
前第４補助電極層で他方の幅狭辺の残り半分を被覆するとともに該第４補助電極層を他方の主電極層に接続したことを特徴とする。 In order to achieve the above object, a second aspect of the present invention provides the chip resistor according to the second aspect,
Forming the resistor layer in a rectangular frame shape comprising a pair of narrow sides and a pair of wide sides;
One main electrode layer is connected to the middle part of one narrow side, the other main electrode layer is connected to the middle part of the other narrow side,
Covering approximately half of one narrow side with the first auxiliary electrode layer and connecting the first auxiliary electrode layer to one main electrode;
Covering the other half of one narrow side with the second auxiliary electrode layer and connecting the second auxiliary electrode layer to one main electrode layer;
Covering approximately half of the other narrow side with the third auxiliary electrode layer and connecting the third auxiliary electrode layer to the other main electrode layer,
The front fourth auxiliary electrode layer covers the remaining half of the other narrow side and the fourth auxiliary electrode layer is connected to the other main electrode layer .

請求項１に記載の本願発明に係るチップ抵抗器は、補助電極層がランドに対向するように配線基板に載置し、半田付けして実装する。
而して本発明によれば、抵抗体層のうち高発熱部分若しくは発熱量の大きい高抵抗部分を主電極層に隣接して設け、かつ高発熱部分若しくは高抵抗部分の少なくとも一部を絶縁性保護膜を介して補助電極層で被覆し、補助電極層をランドに対向するように配線基板に載置して実装するので、抵抗体層の高発熱部分若しくは高抵抗部分の発熱が高発熱部分若しくは高抵抗部分の上層を成す補助電極層に直接的に伝熱し、補助電極層からランドへと速やかに放熱される。このため、高抵抗部分に対し並列配置された主電極層を通してランドへ放熱する従来のチップ抵抗器に比べ、高い放熱効果を得ることができる。 The chip resistor according to the first aspect of the present invention is mounted on the wiring board and soldered and mounted so that the auxiliary electrode layer faces the land.
Thus, according to the present invention, a high heat generation portion or a high resistance portion having a large heat generation amount is provided adjacent to the main electrode layer, and at least a part of the high heat generation portion or the high resistance portion is insulative. Since the auxiliary electrode layer is covered with a protective film and mounted on the wiring board so as to face the land, the high heat generation part of the resistor layer or the heat generation of the high resistance part is the high heat generation part. Alternatively, heat is transferred directly to the auxiliary electrode layer that forms the upper layer of the high resistance portion, and heat is quickly radiated from the auxiliary electrode layer to the land. For this reason, compared with the conventional chip resistor which radiates heat to the land through the main electrode layer arranged in parallel with the high resistance portion, a high heat radiation effect can be obtained.

請求項２に記載の発明によれば、抵抗体を一対の幅狭辺と一対の幅広辺から成る四角形の枠形に形成したので、幅狭辺が高抵抗部分となり、幅広辺が低抵抗部分となる。そして、第１補助電極層と第２補助電極層で一方の幅狭辺を被覆し、第３補助電極層と第４補助電極層で他方の幅狭辺を被覆するので、高抵抗部分となる幅狭辺の発熱を第１〜第４補助電極層を通してランドへと効果的に放熱できる。
また、請求項１及び２記載の発明によれば、補助電極層を４分割して第１と第２補助電極層の間に一方の主電極層を露出させ、第３補助電極層と第４補助電極層との間に他方の主電極層を露出したので、主電極層を配線基板のランドに対向接触するように実装できる。このため、抵抗体層の抵抗値が低い場合における補助電極層の抵抗値に対する悪影響を抑制しつつ、補助電極層による放熱効果の向上を図ることができる。 According to the second aspect of the present invention, since the resistor is formed in a rectangular frame shape composed of a pair of narrow sides and a pair of wide sides, the narrow side becomes the high resistance portion and the wide side becomes the low resistance portion. It becomes. The first auxiliary electrode layer and the second auxiliary electrode layer cover one narrow side, and the third auxiliary electrode layer and the fourth auxiliary electrode layer cover the other narrow side, so that a high resistance portion is obtained. Heat generated in the narrow side can be effectively radiated to the land through the first to fourth auxiliary electrode layers.
According to the first and second aspects of the invention, the auxiliary electrode layer is divided into four parts, and one main electrode layer is exposed between the first and second auxiliary electrode layers, and the third auxiliary electrode layer and the fourth auxiliary electrode layer are exposed. Since the other main electrode layer is exposed between the auxiliary electrode layers, the main electrode layer can be mounted so as to be opposed to the land of the wiring board. For this reason, the heat dissipation effect by the auxiliary electrode layer can be improved while suppressing adverse effects on the resistance value of the auxiliary electrode layer when the resistance value of the resistor layer is low.

以下に本発明を添付図面に基づき説明する。図１は本発明と密接な関連を有する参考例に係るチップ抵抗器の構造を示す模式的断面図である。当該チップ抵抗器１０は、耐熱性絶縁体から成る基板１１、一対の主電極層１２，１３、一対の下面電極層１４，１５、抵抗体層１６、一次コート層１７、二次コート層（絶縁性保護膜）１８、補助電極層１９，２０、側面電極層２１，２２、銅めっき層２３，２４、中間電極層２５，２６及び外部電極層２７，２８から構成される。以下にその製造工程を説明する。 The present invention will be described below with reference to the accompanying drawings. FIG. 1 is a schematic cross-sectional view showing the structure of a chip resistor according to a reference example closely related to the present invention . The chip resistor 10 includes a substrate 11 made of a heat-resistant insulator, a pair of main electrode layers 12 and 13, a pair of lower surface electrode layers 14 and 15, a resistor layer 16, a primary coat layer 17, and a secondary coat layer (insulation). Protective protective film 18, auxiliary electrode layers 19 and 20, side electrode layers 21 and 22, copper plating layers 23 and 24, intermediate electrode layers 25 and 26, and external electrode layers 27 and 28. The manufacturing process will be described below.

一次（主電極間方向と直角の方向）、二次（主電極間方向）の２種類の分割用スリット（図示せず）を形成した高純度アルミナから成る基板１１の表面に銀系の電極ペーストを印刷し、焼成して一対の主電極層１２，１３を形成する。同様にして基板１１の裏面に一対の下面電極層１４，１５を印刷、焼成により形成する。この銀系の電極ペーストの焼成温度は８５０℃とする。   A silver-based electrode paste on the surface of a substrate 11 made of high-purity alumina on which two types of slits (not shown) for primary (direction perpendicular to the direction between main electrodes) and secondary (direction between main electrodes) are formed. Is printed and fired to form the pair of main electrode layers 12 and 13. Similarly, a pair of lower surface electrode layers 14 and 15 are formed on the back surface of the substrate 11 by printing and baking. The firing temperature of this silver-based electrode paste is 850 ° C.

次ぎに、一対の主電極層間を接続するように、酸化ルテニウム系の抵抗ペーストを印刷し、焼成して抵抗体層１６を形成する。   Next, the resistor layer 16 is formed by printing and baking a ruthenium oxide-based resistor paste so as to connect the pair of main electrode layers.

続いて、抵抗体層１６の上にホウ珪酸鉛ガラス系のガラスペーストを印刷し、焼成して一次コート層１７を形成する。この一次コート層１７は次ぎに行う抵抗体層のトリミング時の熱衝撃を緩和し、トリミング溝先端の微少クラックの発生を防止するために形成される。   Subsequently, a lead borosilicate glass-based glass paste is printed on the resistor layer 16 and baked to form the primary coat layer 17. The primary coat layer 17 is formed to alleviate thermal shock during the subsequent trimming of the resistor layer and to prevent the occurrence of minute cracks at the end of the trimming groove.

続いて、一次コート層１７の上から抵抗体層１６にレーザを放射して２本の平行に延びるトリミング溝１６ａを形成し、これにより抵抗値を目標値に修正する。   Subsequently, a laser is emitted from above the primary coating layer 17 to the resistor layer 16 to form two parallel trimming grooves 16a, thereby correcting the resistance value to a target value.

図２に、主電極層１２，１３、抵抗体層１６、一次コート層１７及びトリミング溝１６ａが形成されたチップ片一個分の基板１１を示す。一方のトリミング溝１６ａは抵抗体層１６の一方の主電極層１２に隣接する部位に形成され、長方形の抵抗体層１６の一方の長辺から内部へと延びている。また、他方のトリミング溝１６ａは他方の主電極１３に隣接する部位に形成され、長方形の他方の長辺から内部へと延びている。これにより、抵抗体層１６は、各主電極層１２，１３に隣接する高抵抗部分１６ｂと、両高抵抗部分１６ｂ間の低抵抗部分１６ｃに区分される。   FIG. 2 shows the substrate 11 for one chip piece on which the main electrode layers 12 and 13, the resistor layer 16, the primary coating layer 17 and the trimming groove 16 a are formed. One trimming groove 16a is formed in a portion of the resistor layer 16 adjacent to one main electrode layer 12, and extends from one long side of the rectangular resistor layer 16 to the inside. The other trimming groove 16a is formed in a portion adjacent to the other main electrode 13, and extends from the other long side of the rectangle to the inside. Thus, the resistor layer 16 is divided into a high resistance portion 16b adjacent to each of the main electrode layers 12 and 13 and a low resistance portion 16c between the high resistance portions 16b.

次ぎに、図３に示すように、一次コート層１７の上から抵抗体層１６を被覆するようにホウ珪酸鉛ガラス系のガラスペーストを印刷し、焼成して二次コート層（絶縁性保護膜）１８を形成する。この二次コート層１８によって抵抗体層１６は外部環境から絶縁され、機械的衝撃から保護される。   Next, as shown in FIG. 3, a borosilicate glass-based glass paste is printed on the primary coating layer 17 so as to cover the resistor layer 16, and baked to form a secondary coating layer (insulating protective film). ) 18 is formed. The secondary coating layer 18 insulates the resistor layer 16 from the external environment and protects it from mechanical impact.

続いて、図４に示すように、電極ペースト（例えば焼成温度が６００℃の低温焼成の銀ペースト）を抵抗体層１６の高抵抗部分１６ｂとそれに隣接する主電極１２，１３を二次コート層１８の上から被覆するように印刷し、焼成して補助電極層１９，２０を形成する。補助電極層１９，２０は抵抗体層１６からは二次コート層１８によって絶縁されるものの、二次コート層１８から露出している主電極層１２，１３の一端と電気的に接続される。   Subsequently, as shown in FIG. 4, an electrode paste (for example, a low-temperature firing silver paste having a firing temperature of 600 ° C.) is applied to the high resistance portion 16 b of the resistor layer 16 and the main electrodes 12 and 13 adjacent to the high resistance portion 16 b. The auxiliary electrode layers 19 and 20 are formed by printing so as to cover 18 and baking. Although the auxiliary electrode layers 19 and 20 are insulated from the resistor layer 16 by the secondary coat layer 18, they are electrically connected to one end of the main electrode layers 12 and 13 exposed from the secondary coat layer 18.

次に、一次スリットから基板１１を短冊状に分割する。短冊状の基板１１には二次スリットで区画された多数のチップ片が並列形成されている。この短冊状の基板１１の両分割面に電極ペーストを印刷し、焼成して側面電極層２１，２２を形成する。側面電極層２１，２２により主電極層１２，１３と下面電極層１４，１５が接続される。そして、短冊状の基板１１を二次スリットに沿って分割し、個々のチップ片１０にする。   Next, the substrate 11 is divided into strips from the primary slit. On the strip-shaped substrate 11, a large number of chip pieces partitioned by secondary slits are formed in parallel. The electrode paste is printed on both divided surfaces of the strip-shaped substrate 11 and fired to form the side electrode layers 21 and 22. The main electrode layers 12 and 13 and the bottom electrode layers 14 and 15 are connected by the side electrode layers 21 and 22. Then, the strip-shaped substrate 11 is divided along the secondary slits to form individual chip pieces 10.

二次スリットから分割した個々のチップ片１０は、続いて、銅めっき、ニッケルめっき及び錫めっきを順に施し、補助電極層１９，２０、側面電極層２１，２２、下面電極層１４，１５を被覆する銅めっき層２３，２４、中間電極層（ニッケルめっき層）２５，２６、外部電極層（錫めっき層）２７，２８を形成する。ここに、銅めっき層２３，２４は補助電極層１９，２０の熱を補助電極層１９，２０全面に効果的に拡散させるため、中間電極層２５，２６は側面電極層２１，２２のはんだ喰われを防止するため、また、外部電極層２７，２８ははんだ付け性を良好にするため施される。   Each chip piece 10 divided from the secondary slit is subsequently subjected to copper plating, nickel plating and tin plating in order to cover the auxiliary electrode layers 19 and 20, the side electrode layers 21 and 22, and the bottom electrode layers 14 and 15. Copper plating layers 23 and 24, intermediate electrode layers (nickel plating layers) 25 and 26, and external electrode layers (tin plating layers) 27 and 28 are formed. Here, since the copper plating layers 23 and 24 effectively diffuse the heat of the auxiliary electrode layers 19 and 20 over the entire surface of the auxiliary electrode layers 19 and 20, the intermediate electrode layers 25 and 26 are soldered to the side electrode layers 21 and 22. In order to prevent cracking, the external electrode layers 27 and 28 are applied to improve solderability.

参考例に係るチップ抵抗器１０の構造及び製造工程は以上の通りであって、配線基板２９に実装するには図５に示すように、補助電極層１９，２０が配線基板２９のランド３０に対向するように載置し、はんだ３１で固着する。 The structure and manufacturing process of the chip resistor 10 according to the reference example are as described above. To mount the chip resistor 10 on the wiring board 29, the auxiliary electrode layers 19 and 20 are formed on the lands 30 of the wiring board 29 as shown in FIG. They are placed so as to face each other and fixed with solder 31.

参考例のチップ抵抗器１０は、抵抗体層１６のうち発熱量の大きい高抵抗部分１６ｂを主電極層１２，１３に隣接して設け、かつ高抵抗部分１６ｂを絶縁性保護膜１８を介して補助電極層１９，２０で被覆し、補助電極層１９，２０をランド３０に対向配置するので、高抵抗部分１６ｂの発熱が高抵抗部分１６ｂの上層を成す補助電極層１９，２０に直接的に伝熱する。このため、補助電極層１９，２０からランド３０へと速やかに放熱されるので、高い放熱効果を得ることができる。 In the chip resistor 10 of the reference example, the high resistance portion 16b having a large calorific value in the resistor layer 16 is provided adjacent to the main electrode layers 12 and 13, and the high resistance portion 16b is provided via the insulating protective film 18. Since the auxiliary electrode layers 19 and 20 are covered and the auxiliary electrode layers 19 and 20 are disposed opposite to the lands 30, the heat generated in the high resistance portion 16b is directly applied to the auxiliary electrode layers 19 and 20 forming the upper layer of the high resistance portion 16b. Heat transfer. For this reason, since heat is rapidly radiated from the auxiliary electrode layers 19 and 20 to the land 30, a high heat radiation effect can be obtained.

また、補助電極層１９，２０に熱伝導率の高い銅メッキ２３，２４を施したので、補助電極層１９，２０に伝わる抵抗体層１６の高抵抗部分１６ｂの発熱が補助電極層１９，２０全体に速やかに拡散する。このため、より一層放熱効果を高めることができる。   In addition, since the auxiliary electrode layers 19 and 20 are provided with the copper platings 23 and 24 having high thermal conductivity, the heat generated in the high resistance portion 16b of the resistor layer 16 transmitted to the auxiliary electrode layers 19 and 20 is generated by the auxiliary electrode layers 19 and 20. Spreads quickly throughout. For this reason, the heat dissipation effect can be further enhanced.

本発明の実施例に係るチップ抵抗器４０を図６に示す。当該チップ抵抗器４０も参考例に係るチップ抵抗器１０と同じように、耐熱性絶縁体から成る基板４１、主電極層４２，４３、下面電極層４４，４５、抵抗体層４６、二次コート層（絶縁性保護膜）４７、補助電極層４８、側面電極層５０，５１、銅めっき層５２，５３、中間電極層５４，５５及び外部電極層５６，５７から構成される。ただし、このチップ抵抗器４０では抵抗体層４６の抵抗値調整のためのレーザトリミングを行わないので、一次コート層が省略されている。なお、各層は参考例のチップ抵抗器１０の対応層と同じ材料から成る。   A chip resistor 40 according to an embodiment of the present invention is shown in FIG. Similarly to the chip resistor 10 according to the reference example, the chip resistor 40 also includes a substrate 41 made of a heat-resistant insulator, main electrode layers 42 and 43, lower electrode layers 44 and 45, a resistor layer 46, and a secondary coat. A layer (insulating protective film) 47, an auxiliary electrode layer 48, side electrode layers 50 and 51, copper plating layers 52 and 53, intermediate electrode layers 54 and 55, and external electrode layers 56 and 57. However, since the chip resistor 40 does not perform laser trimming for adjusting the resistance value of the resistor layer 46, the primary coat layer is omitted. Each layer is made of the same material as the corresponding layer of the chip resistor 10 of the reference example.

このチップ抵抗器４０では、図７に示すように、抵抗体層４６として幅の狭い一対の幅狭長辺４６ａと幅の広い一対の幅広短辺４６ｂから成る四角形の枠形を有する抵抗体層４６を基板４１の表面に印刷、焼成して形成する。続いて、一対の主電極層４２，４３をそれぞれ幅狭長辺４６ａの中間部に接続するように形成する。尚、主電極層４２，４３は中央部が突出した略Ｔ字形をしており、突出部がそれぞれ幅狭長辺４６ａの中間部に接続するように形成する。また、各主電極層４２，４３の抵抗体層の側端部４６ａは基板４１の長辺端部４１ａに沿って形成する。   In this chip resistor 40, as shown in FIG. 7, the resistor layer 46 has a rectangular frame shape composed of a narrow pair of narrow long sides 46a and a wide pair of wide short sides 46b. Is printed and fired on the surface of the substrate 41. Subsequently, the pair of main electrode layers 42 and 43 are formed so as to be connected to the middle part of the narrow long side 46a. The main electrode layers 42 and 43 are substantially T-shaped with the central portion protruding, and are formed so that the protruding portions are respectively connected to the intermediate portion of the narrow long side 46a. The side end portions 46 a of the resistor layers of the main electrode layers 42 and 43 are formed along the long side end portions 41 a of the substrate 41.

次ぎに、図８に示すように、二次コート層（絶縁性保護膜）４７で抵抗体層４６を被覆する。このとき、主電極層４２，４３が二次コート層４７から露出するように二次コート層４７に切欠部４７ａが形成される。   Next, as shown in FIG. 8, the resistor layer 46 is covered with a secondary coat layer (insulating protective film) 47. At this time, a notch 47 a is formed in the secondary coat layer 47 so that the main electrode layers 42 and 43 are exposed from the secondary coat layer 47.

続いて、抵抗体層４６を二次コート層４７の上から補助電極層４８で被覆する。図９に示すように、この補助電極層４８は第１〜第４の四つの補助電極層４８ａ，４８ｂ，４８ｃ，４８ｄから構成される。そして一方の幅狭長辺４６ａの半分と、その残り半分をそれぞれ第１補助電極層４８ａと第２補助電極層４８ｂで被覆し、両補助電極層４８ａ，４８ｂの間から一方の主電極層４２を露出させる。第１補助電極層４８ａと第２補助電極層４８ｂはそれぞれ一方の主電極層４２に接続する。
同様に、他方の幅狭長辺４６ａの略半分と、その残り半分をそれぞれ第３補助電極層４８ｃと第４補助電極層４８ｄで被覆し、両補助電極層４８ｃ，４８ｄの間から他方の主電極層４３を露出させる。第３補助電極層４８ｃと第４補助電極層４８ｄはそれぞれ他方の主電極層４３に接続する。 Subsequently, the resistor layer 46 is covered with the auxiliary electrode layer 48 from above the secondary coat layer 47. As shown in FIG. 9, the auxiliary electrode layer 48 includes first to fourth auxiliary electrode layers 48a, 48b, 48c, and 48d. One half of the narrow long side 46a and the other half are covered with the first auxiliary electrode layer 48a and the second auxiliary electrode layer 48b, respectively, and one main electrode layer 42 is formed between the auxiliary electrode layers 48a and 48b. Expose. The first auxiliary electrode layer 48a and the second auxiliary electrode layer 48b are connected to one main electrode layer 42, respectively.
Similarly, approximately half of the other narrow long side 46a and the other half are covered with a third auxiliary electrode layer 48c and a fourth auxiliary electrode layer 48d, respectively, and the other main electrode is interposed between the auxiliary electrode layers 48c and 48d. Layer 43 is exposed. The third auxiliary electrode layer 48c and the fourth auxiliary electrode layer 48d are connected to the other main electrode layer 43, respectively.

続いて、第１スリットから基板を短冊状に分割し、分割面に側面電極層５０，５１を形成する。その後、第２スリットから基板を分割して個々のチップ片４１を形成し、各チップ片４１に銅めっき５２，５３、ニッケルめっき（中間電極層）５４，５５、錫めっき（外部電極層）５６，５７を形成する。   Subsequently, the substrate is divided into strips from the first slit, and the side electrode layers 50 and 51 are formed on the dividing surface. Thereafter, the substrate is divided from the second slit to form individual chip pieces 41. Copper plating 52, 53, nickel plating (intermediate electrode layer) 54, 55, tin plating (external electrode layer) 56 is applied to each chip piece 41. , 57 are formed.

実施例に係るチップ抵抗器４０の構造は以上の通りであって、配線基板２９に実装するには図１０に示すように、補助電極層４８が配線基板２９のランド３０に対向するように載置し、はんだ３１で固着する。 The structure of the chip resistor 40 according to the embodiment is as described above. To mount the chip resistor 40 on the wiring board 29, the auxiliary electrode layer 48 is mounted so as to face the land 30 of the wiring board 29 as shown in FIG. And fix with solder 31.

実施例に係るチップ抵抗器４１は、抵抗体層４６を一対の幅狭長辺４６ａと一対の幅広短辺４６ｂから成る四角形の枠形にしたので、幅狭長辺４６ａが高抵抗部分となり、幅広短辺４６ｂが低抵抗部分となる。そして、第１補助電極層４８ａと第２補助電極層４８ｂで一方の幅狭長辺４６ａを被覆し、第３補助電極層４８ｃと第４補助電極層４８ｄで他方の幅狭長辺４６ａを被覆するので、高抵抗部分となる幅狭長辺４６ａの発熱を第１〜第４補助電極層４８ａ，４８ｂ，４８ｃ，４８ｄを通して効果的に放熱できる。 In the chip resistor 41 according to the embodiment , the resistor layer 46 is formed in a rectangular frame shape including a pair of narrow long sides 46a and a pair of wide short sides 46b. The side 46b becomes a low resistance portion. The first auxiliary electrode layer 48a and the second auxiliary electrode layer 48b cover one narrow long side 46a, and the third auxiliary electrode layer 48c and the fourth auxiliary electrode layer 48d cover the other narrow long side 46a. The heat of the narrow long side 46a that becomes the high resistance portion can be effectively radiated through the first to fourth auxiliary electrode layers 48a, 48b, 48c, and 48d.

また、補助電極層を４分割して第１補助電極層４８ａと第２補助電極層４８ｂの間に一方の主電極４２を露出させ、第３補助電極層４８ｃと第４補助電極層４８ｄとの間に他方の主電極層４３を露出したので、主電極層４２，４３を配線基板２９のランド３０に対向接触するように実装できる。このため、抵抗体層４６の抵抗値が低い場合における補助電極層４８の抵抗値に対する悪影響を抑制しつつ、補助電極層４８による放熱効果の向上を図ることができる。   Further, the auxiliary electrode layer is divided into four so that one main electrode 42 is exposed between the first auxiliary electrode layer 48a and the second auxiliary electrode layer 48b, and the third auxiliary electrode layer 48c and the fourth auxiliary electrode layer 48d are separated. Since the other main electrode layer 43 is exposed in the middle, the main electrode layers 42 and 43 can be mounted so as to be opposed to the land 30 of the wiring board 29. For this reason, the heat dissipation effect by the auxiliary electrode layer 48 can be improved while suppressing adverse effects on the resistance value of the auxiliary electrode layer 48 when the resistance value of the resistor layer 46 is low.

尚、実施例において抵抗体の幅狭部を高抵抗部とし、抵抗体の幅広部を低抵抗部としたが、これに限らず抵抗体の幅を同一にして、抵抗率の高い抵抗材料を使用して高抵抗部とし、抵抗率の低い抵抗材料を使用して低抵抗部としてもよい。
また、参考例及び実施例において補助電極は高抵抗部全体を被覆するとしたが、これに限らず高抵抗部の一部分を被覆してもよい。 In the examples , the narrow portion of the resistor is a high resistance portion, and the wide portion of the resistor is a low resistance portion. A high resistance portion may be used, and a low resistance portion may be formed using a resistance material having a low resistivity.
In the reference examples and examples , the auxiliary electrode covers the entire high resistance portion. However, the present invention is not limited to this, and a part of the high resistance portion may be covered.

本発明の参考例に係るチップ抵抗器の構造を模式的に示す中央部横断断面図である。It is a center part cross-sectional view which shows typically the structure of the chip resistor which concerns on the reference example of this invention. 同チップ抵抗器の主電極層と抵抗体層及び一次コートを示す模式的斜視図である。It is a typical perspective view which shows the main electrode layer of the same chip resistor, a resistor layer, and a primary coat. 同チップ抵抗器の主電極層と二次コートを示す模式的斜視図である。It is a typical perspective view which shows the main electrode layer and secondary coating of the chip resistor. 同チップ抵抗器の補助電極層を示す模式的斜視図である。It is a typical perspective view which shows the auxiliary electrode layer of the same chip resistor. 同チップ抵抗器と配線基板を示す模式的断面図である。It is typical sectional drawing which shows the chip resistor and wiring board. 本発明の実施例に係るチップ抵抗器の構造を模式的に示す中央部横断断面図である。It is a center section cross-sectional view which shows typically the structure of the chip resistor which concerns on the Example of this invention. 同チップ抵抗器の主電極層と抵抗体層を示す模式的斜視図である。It is a typical perspective view which shows the main electrode layer and resistor layer of the chip resistor. 同チップ抵抗器の主電極層と二次コートを示す模式的斜視図である。It is a typical perspective view which shows the main electrode layer and secondary coating of the chip resistor. 同チップ抵抗器の補助電極層を示す模式的斜視図である。It is a typical perspective view which shows the auxiliary electrode layer of the same chip resistor. 同チップ抵抗器と配線基板を示す模式的断面図である。It is typical sectional drawing which shows the chip resistor and wiring board.

１０，４０…チップ抵抗器
１１，４１…耐熱絶縁体
１２，１３，４２，４３…主電極層
１６，４６…抵抗体層
１６ｂ，４６ａ…高抵抗部分
１８，４７…二次コート（絶縁性保護膜）
１９，２０，４８…補助電極層
２３，２４，５２，５３…銅めっき。 DESCRIPTION OF SYMBOLS 10, 40 ... Chip resistor 11, 41 ... Heat-resistant insulator 12, 13, 42, 43 ... Main electrode layer 16, 46 ... Resistor layer 16b, 46a ... High resistance part 18, 47 ... Secondary coating (insulation protection) film)
19, 20, 48 ... auxiliary electrode layers 23, 24, 52, 53 ... copper plating.

Claims (2)

耐熱性絶縁体の表面に一対の主電極層を形成すると共に両電極層を接続するように抵抗体層を形成し、かつ該抵抗体層を前記両主電極層又は少なくとも一方の主電極層に隣接する高発熱部分とそれ以外の低発熱部分で構成したチップ抵抗器であって、前記抵抗体層を絶縁性保護膜で被覆し、かつ該絶縁性保護膜の上から前記抵抗体層の前記主電極層に隣接する部分を補助電極層で被覆したチップ抵抗器であって、
前記補助電極層を第１補助電極層、第２補助電極層、第３補助電極層及び第４補助電極層から構成し、
第１補助電極層と第２補助電極層を一方の主電極層に接続するとともに該主電極層を第１補助電極層と第２補助電極層の間に露出させ、
第３補助電極層と第４補助電極層を他方の主電極層に接続するとともに該主電極層を第３補助電極層と第４補助電極層の間に露出させたことを特徴とするチップ抵抗器。 A pair of main electrode layers are formed on the surface of the heat-resistant insulator and a resistor layer is formed so as to connect both electrode layers, and the resistor layers are formed on the main electrode layers or at least one of the main electrode layers. A chip resistor composed of an adjacent high heat generation portion and other low heat generation portions, wherein the resistor layer is covered with an insulating protective film, and the resistor layer is formed on the insulating protective film from above. A chip resistor in which a portion adjacent to the main electrode layer is covered with an auxiliary electrode layer ,
The auxiliary electrode layer comprises a first auxiliary electrode layer, a second auxiliary electrode layer, a third auxiliary electrode layer, and a fourth auxiliary electrode layer,
Connecting the first auxiliary electrode layer and the second auxiliary electrode layer to one main electrode layer and exposing the main electrode layer between the first auxiliary electrode layer and the second auxiliary electrode layer;
A chip resistor characterized in that the third auxiliary electrode layer and the fourth auxiliary electrode layer are connected to the other main electrode layer and the main electrode layer is exposed between the third auxiliary electrode layer and the fourth auxiliary electrode layer. vessel. 前記抵抗体層を一対の幅狭辺と一対の幅広辺から成る四角形の枠形に形成し、
一方の主電極層を一方の幅狭辺の中間部に接続し、他方の主電極層を他方の幅狭辺の中間部に接続し、
前記第１補助電極層で一方の幅狭辺の略半分を被覆するとともに該第１補助電極層を一方の主電極に接続し、
前記第２補助電極層で一方の幅狭辺の残り半分を被覆するとともに該第２補助電極層を一方の主電極層に接続し、
前記第３補助電極層で他方の幅狭辺の略半分を被覆するとともに該第３補助電極層を他方の主電極層に接続し、
前第４補助電極層で他方の幅狭辺の残り半分を被覆するとともに該第４補助電極層を他方の主電極層に接続したことを特徴とする請求項２に記載のチップ抵抗器。 Forming the resistor layer in a rectangular frame shape comprising a pair of narrow sides and a pair of wide sides;
One main electrode layer is connected to the middle part of one narrow side, the other main electrode layer is connected to the middle part of the other narrow side,
Covering approximately half of one narrow side with the first auxiliary electrode layer and connecting the first auxiliary electrode layer to one main electrode;
Covering the other half of one narrow side with the second auxiliary electrode layer and connecting the second auxiliary electrode layer to one main electrode layer;
Covering approximately half of the other narrow side with the third auxiliary electrode layer and connecting the third auxiliary electrode layer to the other main electrode layer,
3. The chip resistor according to claim 2, wherein the other half of the other narrow side is covered with the front fourth auxiliary electrode layer and the fourth auxiliary electrode layer is connected to the other main electrode layer .
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JP2004119500A (en) * 2002-09-24 2004-04-15 Kamaya Denki Kk Chip resistor, its manufacturing method and method for packaging same
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JPS639959A (en) * 1986-07-01 1988-01-16 New Japan Radio Co Ltd Manufacture of high resistor of polysilicon
JPH0864403A (en) * 1994-08-26 1996-03-08 Matsushita Electric Ind Co Ltd Square chip resistor with circuit inspection terminal
JP2003045702A (en) * 2001-07-31 2003-02-14 Koa Corp Chip resistor and manufacturing method therefor
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