JP4610633B2 - Wiring board manufacturing method - Google Patents

Wiring board manufacturing method Download PDF

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JP4610633B2
JP4610633B2 JP2008127142A JP2008127142A JP4610633B2 JP 4610633 B2 JP4610633 B2 JP 4610633B2 JP 2008127142 A JP2008127142 A JP 2008127142A JP 2008127142 A JP2008127142 A JP 2008127142A JP 4610633 B2 JP4610633 B2 JP 4610633B2
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layer
wiring board
metal foil
core substrate
shows
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JP2008193132A (en
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貴志 首藤
憲治 高野
憲司 飯田
健一郎 阿部
啓二 新居
清隆 瀬山
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item

Description

本発明は配線基板の製造方法に関し、より詳細には高密度、低熱膨張、高剛性を備えた配線基板の製造方法に関する。   The present invention relates to a method for manufacturing a wiring board, and more particularly to a method for manufacturing a wiring board having high density, low thermal expansion, and high rigidity.

図１２、１３はコア基板の両面にビルドアップ法により配線パターンを形成した配線基板の一般的な製造方法を示す。   12 and 13 show a general manufacturing method of a wiring board in which wiring patterns are formed on both surfaces of the core board by a build-up method.

図１２は、両面に配線パターンが形成されるコア基板２２の製造工程を示す。図１２（ａ）は、銅張り積層板からなる基板１０を示す。この基板１０は、ガラスクロス入りのエポキシ樹脂からなる基材１０ａの両面に銅箔１１を被着したものである。図１２（ｂ）は、基板１０にドリル加工を施し、貫通孔１２を形成した状態を示す。図１２（ｃ）は、基板１０の表裏面に形成される配線パターンの電気的導通をとるために、スルーホールめっき（銅めっき）を施した状態を示す。１４がスルーホールめっきによって形成された銅めっき層である。   FIG. 12 shows a manufacturing process of the core substrate 22 on which wiring patterns are formed on both sides. FIG. 12A shows a substrate 10 made of a copper-clad laminate. This board | substrate 10 adhere | attaches the copper foil 11 on both surfaces of the base material 10a which consists of an epoxy resin containing a glass cloth. FIG. 12B shows a state where the substrate 10 is drilled to form the through hole 12. FIG. 12C shows a state in which through-hole plating (copper plating) is performed in order to establish electrical continuity of the wiring pattern formed on the front and back surfaces of the substrate 10. 14 is a copper plating layer formed by through-hole plating.

図１２（ｄ）は、貫通孔１２を孔埋め用の樹脂１６によって充填した状態を示す。図１２（ｅ）は、次に、蓋めっきとして銅めっきを基板１０の表面に施した状態を示す。この蓋めっきにより、樹脂１６の端面を含む基板１０の両面の全面が銅めっき層１８によって被覆される。図１２（ｆ）は、基板１０の両面に被着している銅めっき層１８、１４および銅箔１１をエッチングして基板１０の両面に配線パターン２０を形成し、コア基板２２を形成した状態を示す。   FIG. 12D shows a state in which the through hole 12 is filled with the resin 16 for filling the hole. FIG. 12E shows a state in which copper plating is applied to the surface of the substrate 10 as lid plating. By this lid plating, the entire surface of both surfaces of the substrate 10 including the end surface of the resin 16 is covered with the copper plating layer 18. FIG. 12F shows a state in which the copper plating layers 18 and 14 and the copper foil 11 deposited on both surfaces of the substrate 10 are etched to form the wiring patterns 20 on both surfaces of the substrate 10 and the core substrate 22 is formed. Indicates.

図１３は、コア基板２２の両面に配線パターンを形成して配線基板を製造するまでの製造工程を示す。図１３（ａ）は、コア基板２２の両面にビルドアップ法によって配線パターン２４を形成した状態を示す。２６が絶縁層、２８が層間で配線パターン２４を電気的に接続するビアである。図１３（ｂ）は、ビルドアップ層の表面に感光性のソルダーレジスト３０を塗布し、露光および現像した状態を示す。図１３（ｃ）は、配線パターン２４の表面に、表面処理として無電解ニッケルめっきと無電解金めっきを施し、配線パターン２４の露出面を保護めっき３２によって被覆した状態を示す。図１３（ｄ）は、配線パターン２４の電極にはんだバンプ３４を形成し、コア基板２２の両面に配線パターン２４が積層して形成された配線基板３６を得た状態を示す。   FIG. 13 shows a manufacturing process until a wiring board is manufactured by forming a wiring pattern on both surfaces of the core substrate 22. FIG. 13A shows a state in which the wiring pattern 24 is formed on both surfaces of the core substrate 22 by the build-up method. 26 is an insulating layer, and 28 is a via for electrically connecting the wiring pattern 24 between the layers. FIG. 13B shows a state in which a photosensitive solder resist 30 is applied to the surface of the buildup layer, and is exposed and developed. FIG. 13C shows a state where the surface of the wiring pattern 24 is subjected to electroless nickel plating and electroless gold plating as surface treatment, and the exposed surface of the wiring pattern 24 is covered with the protective plating 32. FIG. 13D shows a state in which the solder bumps 34 are formed on the electrodes of the wiring pattern 24 and the wiring board 36 is obtained by laminating the wiring patterns 24 on both surfaces of the core substrate 22.

こうして得られた配線基板３６は、基板１０の基材に剛性の高いガラスクロス入りの樹脂材を使用しているから、高剛性に形成することが可能である。しかしながら、コア基板２２を支持体としてビルドアップ法によって配線パターン２４を形成する方法では、コア基板２２に形成する貫通孔１２を一定間隔以下に配置することができないため、配線基板の高密度化が制約される。   The wiring board 36 obtained in this way can be formed with high rigidity because a highly rigid resin material containing glass cloth is used as the base material of the substrate 10. However, in the method of forming the wiring pattern 24 by the build-up method using the core substrate 22 as a support, the through holes 12 formed in the core substrate 22 cannot be arranged at a predetermined interval or less. Be constrained.

また、配線基板を薄型に形成すると配線基板の電気的特性を改善することが可能であることから、最近は配線基板を薄型に形成することが求められている。しかしながら、配線基板を薄型にするためにコア基板を薄くしたとすると、薄いコア基板を搬送するために特殊な製造ラインが必要になるといった問題、コア基板を薄くすると基板全体としての剛性が低下するから、絶縁層や配線パターンを形成する加工工程で発生する応力によって基板の収縮やうねりといった変形が生じやすくなり、配線パターンを高密度に形成することが難しくなるという問題がある。また、コア基板を薄くすると、基板全体としての熱膨張係数が半導体チップの熱膨張係数からさらに隔たるようになり、配線基板に搭載された半導体チップとの間で熱応力が大きくあらわれるようになるという問題がある。配線基板の熱膨張係数を半導体チップの熱膨張係数に近づけるため、コア基板として半導体チップの熱膨張係数に近い低熱膨張係数の金属コアを使用することも考えられるが、この場合は、コア基板とビルドアップ層との間で熱応力が作用してビルドアップ層にクラックが生じるといった問題が生じる。   Further, since it is possible to improve the electrical characteristics of the wiring board when the wiring board is formed thin, it has recently been required to form the wiring board thin. However, if the core substrate is made thin in order to make the wiring board thin, there is a problem that a special production line is necessary for transporting the thin core substrate, and if the core substrate is made thin, the rigidity of the whole substrate is lowered. Therefore, there is a problem that deformation such as shrinkage and undulation of the substrate is likely to occur due to stress generated in the processing step for forming the insulating layer and the wiring pattern, and it becomes difficult to form the wiring pattern at a high density. In addition, when the core substrate is thinned, the thermal expansion coefficient of the entire substrate is further separated from the thermal expansion coefficient of the semiconductor chip, and a large thermal stress appears between the semiconductor chip mounted on the wiring board. There is a problem. In order to bring the thermal expansion coefficient of the wiring board closer to that of the semiconductor chip, it is possible to use a metal core having a low thermal expansion coefficient close to that of the semiconductor chip as the core board. There arises a problem that a thermal stress acts between the build-up layer and a crack occurs in the build-up layer.

本発明は上記の課題を解決すべくなされたものであり、基板の低熱膨張化を図ること、あるいは基板の高剛性化を図ることによって、半導体チップとの間での熱応力を抑制しあるいは熱応力に耐えることができる配線基板の製造方法を提供することを目的とする。   The present invention has been made to solve the above-mentioned problems, and by suppressing the thermal expansion of the substrate or by increasing the rigidity of the substrate, the thermal stress between the semiconductor chip and the semiconductor chip can be suppressed. An object of the present invention is to provide a method of manufacturing a wiring board that can withstand stress.

本発明は、以下に記載するような解決手段により、前記課題を解決する。   The present invention solves the above-described problems by the solving means described below.

本発明は、コア基板の両面にビルドアップ層を形成してなる配線基板の製造方法において、前記ビルドアップ層を形成する際に、銅よりも小さな熱膨張係数を有する金属箔を、ビルドアップ層の中間層に形成される配線パターンと干渉しない配置で該ビルドアップ層の中間層に組み込むことを特徴とする。
また、金属箔の片面に接着剤層が被着された接着剤付金属箔を前記ビルドアップ層の中間層に積層することにより、該ビルドアップ層の中間層に金属箔を組み込むことを特徴とする。
また、前記ビルドアップ層の中間層は、複数の中間層であることを特徴とする。
The present invention relates to a method of manufacturing a wiring board in which build-up layers are formed on both surfaces of a core substrate. When forming the build-up layer, a metal foil having a smaller thermal expansion coefficient than copper is used as the build-up layer. characterized in an arrangement of not interfering with the wiring patterns formed on the intermediate layer be incorporated into the intermediate layer of the build-up layer.
Further, by laminating the adhesive coated metal foil on which the adhesive layer has been deposited on one surface of the metal foil to the intermediate layer of the buildup layer, and characterized by incorporating a metallic foil to the intermediate layer of the build-up layer To do.
Further, the intermediate layer of the buildup layer is a plurality of intermediate layers.

本発明によれば、ビルドアップ層に低熱膨張係数の金属箔を組み込むことによって、配線基板の熱膨張係数を下げることができ、半導体チップとの間で発生する熱応力を抑えた配線基板が得られる。   According to the present invention, by incorporating a metal foil having a low thermal expansion coefficient into the build-up layer, the thermal expansion coefficient of the wiring board can be lowered, and a wiring board that suppresses the thermal stress generated with the semiconductor chip is obtained. It is done.

（実施形態１）
図１〜４は、本発明に係る配線基板の製造方法を示す説明図である。図１（ａ）は、本発明方法において特徴的な製造工程であり、支持体１００の両面に接着フィルム４０を介して、第１の金属層４１と第２の金属層４２を積層して被覆する工程を示す。 (Embodiment 1)
1-4 is explanatory drawing which shows the manufacturing method of the wiring board based on this invention. FIG. 1A shows a characteristic manufacturing process in the method of the present invention, in which a first metal layer 41 and a second metal layer 42 are laminated and coated on both surfaces of a support 100 via an adhesive film 40. The process to perform is shown.

支持体１００はビルドアップ法によって配線パターンを形成するための支持材として使用するもので、ビルドアップ層を形成した際に収縮や反りといった変形が生じない十分な強度を備えている材料によって形成する。本実施形態では、支持体１００の基材１００ａとして０．３〜０．４ｍｍの厚さのガラスクロス入りエポキシ樹脂基板を使用し、この樹脂基板の両面に厚さ９μｍの銅箔１１を被着したものを支持体１００とした。この支持体１００は配線基板を多数個取りするため大判の平板状に形成したものを使用する。   The support body 100 is used as a support material for forming a wiring pattern by a build-up method, and is formed of a material having sufficient strength that does not cause deformation such as shrinkage and warping when the build-up layer is formed. . In this embodiment, a glass cloth-containing epoxy resin substrate having a thickness of 0.3 to 0.4 mm is used as the base material 100a of the support 100, and a copper foil 11 having a thickness of 9 μm is attached to both surfaces of the resin substrate. This was used as a support 100. The support 100 is formed in a large flat plate shape in order to take a large number of wiring boards.

接着フィルム４０は第１の金属層４１を支持体１００の表面に接着して固定する作用をなすとともに、第２の金属層４２の外周縁部を支持体１００に接着する作用をなす。このため、接着フィルム４０は支持体１００の両面を各々全面にわたって被覆するように設けるとともに、第１の金属層４１の外周縁の位置が第２の金属層４２の外周縁の位置よりも若干内側に位置するように、第１の金属層４１と第２の金属層４２の外形寸法を設定して接着する。   The adhesive film 40 functions to adhere and fix the first metal layer 41 to the surface of the support 100, and also functions to adhere the outer peripheral edge of the second metal layer 42 to the support 100. For this reason, the adhesive film 40 is provided so as to cover both surfaces of the support 100 over the entire surface, and the position of the outer peripheral edge of the first metal layer 41 is slightly inside the position of the outer peripheral edge of the second metal layer 42. The outer dimensions of the first metal layer 41 and the second metal layer 42 are set and bonded so as to be positioned at each other.

本実施形態においては、第１の金属層４１には厚さ１８μｍからなる銅箔を使用し、第２の金属層４２にはＣｒ、Ｔｉ、Ｎｉ等の銅をエッチングするエッチング液によって侵されない金属を中間バリア層として厚さ１８μｍの銅箔を貼り合わせたものを使用している。   In the present embodiment, a copper foil having a thickness of 18 μm is used for the first metal layer 41, and the second metal layer 42 is a metal that is not affected by an etchant that etches copper such as Cr, Ti, and Ni. Is used as an intermediate barrier layer and a 18 μm thick copper foil bonded together.

図１（ｂ）は、支持体１００の両面で、接着フィルム４０を介して第１の金属層４１と第２の金属層４２を真空熱プレスした状態を示す。真空熱プレスとは、図１（ａ）に示すワーク全体を真空吸引しながら、接着フィルム４０を介して第１の金属層４１と第２の金属層４２を重ねて加熱および加圧する操作である。この真空熱プレスにより、第１の金属層４１は接着層４０ａを介して支持体１００の銅箔１１の表面に接着され、第２の金属層４２はその外周縁部で接着層４０ａを介して銅箔１１０に接着される。また、このときに、第１の金属層４１と第２の金属層４２とは互いに真空吸着する。真空吸着とは、第１の金属層４１と第２の金属層４２の真空吸着部分の真空が破れた場合に、第１の金属層４１と第２の金属層４２が剥離する吸着状態にあるということである。   FIG. 1B shows a state in which the first metal layer 41 and the second metal layer 42 are vacuum-pressed on both surfaces of the support 100 via the adhesive film 40. The vacuum hot press is an operation in which the first metal layer 41 and the second metal layer 42 are stacked and heated and pressed through the adhesive film 40 while the whole workpiece shown in FIG. . By this vacuum hot press, the first metal layer 41 is bonded to the surface of the copper foil 11 of the support 100 via the adhesive layer 40a, and the second metal layer 42 is bonded to the outer peripheral edge portion of the first metal layer 42 via the adhesive layer 40a. Bonded to the copper foil 110. At this time, the first metal layer 41 and the second metal layer 42 are vacuum-adsorbed to each other. The vacuum adsorption is an adsorption state in which the first metal layer 41 and the second metal layer 42 are separated when the vacuum of the vacuum adsorption portion of the first metal layer 41 and the second metal layer 42 is broken. That's what it means.

図１（ｃ）は、第２の金属層４２の表面側の銅箔をエッチングして配線パターン４３を形成した状態を示す。第２の金属層４２には銅のエッチング液によっては侵されない中間バリア層４２ａが設けられているから、サブトラクト法によって銅箔をエッチングすることによって、容易に配線パターン４３を形成することができる。   FIG. 1C shows a state in which the wiring pattern 43 is formed by etching the copper foil on the surface side of the second metal layer 42. Since the second metal layer 42 is provided with the intermediate barrier layer 42a that is not affected by the copper etching solution, the wiring pattern 43 can be easily formed by etching the copper foil by the subtracting method.

図１（ｄ）は、次に、配線パターン４３が形成されている支持体１００の両面にビルドアップ法によって配線パターン４４を形成した状態を示す。４６が絶縁層、４８がビアである。本実施形態では、図のようにビア４８をフィルドビアとし、鉛直方向に柱状にビア４８が連なるように形成している。   Next, FIG. 1D shows a state in which the wiring pattern 44 is formed on both surfaces of the support body 100 on which the wiring pattern 43 is formed by the build-up method. 46 is an insulating layer and 48 is a via. In the present embodiment, as shown in the figure, the via 48 is a filled via, and the via 48 is formed in a column shape in the vertical direction.

図２は、支持体１００の両面にビルドアップ層６０が形成された積層体１２０の両面に、図１２に示した方法によって形成したコア基板２２を接合する工程を示す。前述したように、コア基板２２は基板１０にドリル加工等によって貫通孔を形成し、スルーホールめっきを施し、基板１０の両面に配線パターン２０を形成したものである。   FIG. 2 shows a step of bonding the core substrate 22 formed by the method shown in FIG. 12 to both surfaces of the laminate 120 in which the buildup layers 60 are formed on both surfaces of the support 100. As described above, the core substrate 22 is obtained by forming through holes in the substrate 10 by drilling or the like, performing through-hole plating, and forming the wiring patterns 20 on both surfaces of the substrate 10.

５０は積層体１２０の両面にコア基板２２を接合するために使用するプリプレグである。プリプレグ５０にはビルドアップ層６０とコア基板２２とを電気的に接続するための導電性ペースト５２を収容する収容孔が形成され、この収容孔に導電性ペースト５２が充填されている。なお、プリプレグ５０にかえて熱可塑性樹脂等からなる接着性を有する接着用フィルムを使用することができ、導電性ペースト５２にかえてはんだ等の導電材を使用することも可能である。   Reference numeral 50 denotes a prepreg used for bonding the core substrate 22 to both surfaces of the laminate 120. The prepreg 50 is formed with an accommodation hole for accommodating a conductive paste 52 for electrically connecting the buildup layer 60 and the core substrate 22, and the accommodation hole is filled with the conductive paste 52. Note that an adhesive film made of a thermoplastic resin or the like can be used instead of the prepreg 50, and a conductive material such as solder can be used instead of the conductive paste 52.

積層体１２０の両面にプリプレグ５０とコア基板２２とを位置合わせし（図２（ａ））、プリプレグ５０を介して積層体１２０とコア基板２２とを接合する（図２（ｂ））。この接合操作により、導電性ペースト５２を介して積層体１２０の配線パターン４４とコア基板２２の配線パターン２０とが電気的に接続された状態になる。   The prepreg 50 and the core substrate 22 are aligned on both surfaces of the laminate 120 (FIG. 2A), and the laminate 120 and the core substrate 22 are joined via the prepreg 50 (FIG. 2B). By this joining operation, the wiring pattern 44 of the laminate 120 and the wiring pattern 20 of the core substrate 22 are electrically connected via the conductive paste 52.

図３は、積層体１２０とコア基板２２とを接合した接合体から、コア基板２２の片面にビルドアップ層６０が接合された基板１３０を分離する工程を示す。図３（ａ）は、積層体１２０とコア基板２２との接合体に対して、積層体１２０のコア部分である支持体１００の外周縁部を切断して、コア基板２２とビルドアップ層６０とを積層体１２０から分離した状態を示す。第１の金属層４１の外形線位置よりも若干内側に入った位置で接合体を切断することにより、第１の金属層４１と第２の金属層４２との間の真空吸着が破られ、第１の金属層４１と第２の金属層４２がその当接面から簡単に分離させることができる。ビルドアップ層６０はプリプレグ５０によってコア基板２２に接合しているから、図３（ｂ）に示すように、コア基板２２にビルドアップ層６０が接合された基板１３０が得られる。   FIG. 3 shows a process of separating the substrate 130 in which the buildup layer 60 is bonded to one side of the core substrate 22 from the bonded body in which the laminate 120 and the core substrate 22 are bonded. FIG. 3A shows the joined body of the laminate 120 and the core substrate 22 by cutting the outer peripheral edge portion of the support body 100 that is the core portion of the laminate 120, and the core substrate 22 and the buildup layer 60. Are separated from the laminate 120. By cutting the joined body at a position slightly inside the outline line position of the first metal layer 41, the vacuum adsorption between the first metal layer 41 and the second metal layer 42 is broken, The first metal layer 41 and the second metal layer 42 can be easily separated from the contact surface. Since the buildup layer 60 is bonded to the core substrate 22 by the prepreg 50, as shown in FIG. 3B, a substrate 130 in which the buildup layer 60 is bonded to the core substrate 22 is obtained.

次に、基板１３０の表面に露出している第２の金属層４２の銅箔４２ｂをエッチングによりすべて除去し（図３（ｃ））、銅箔４２ｂを除去することによって露出した中間バリア層４２ａもすべて除去する（図３（ｄ））。中間バリア層４２ａには銅のエッチング液によって侵されない金属を使用しているから、銅箔４２ｂあるいは中間バリア層４２ａは、各々選択的にエッチングして除去することができる。   Next, the copper foil 42b of the second metal layer 42 exposed on the surface of the substrate 130 is completely removed by etching (FIG. 3C), and the intermediate barrier layer 42a exposed by removing the copper foil 42b. Are also removed (FIG. 3D). Since the intermediate barrier layer 42a is made of a metal that is not affected by the copper etchant, the copper foil 42b or the intermediate barrier layer 42a can be selectively etched and removed.

図４は、コア基板２２に接合されたビルドアップ層６０の外面に接続電極を形成して配線基板を形成する工程を示す。図４（ａ）は、ビルドアップ層６０の外表面に感光性のソルダーレジスト５４を塗布し、露光および現像して接続電極を形成するためのランド部５６およびコア基板２２の下面の配線パターン２０を露出させた状態を示す。図４（ｂ）は、ランド部５６およびコア基板２２の下面の配線パターン２０の表面に無電解ニッケルめっきおよび無電解金めっきによる保護めっき５８を形成した状態、図４（ｃ）は、ランド部５６にはんだを印刷し、はんだリフローにより接続電極としてのはんだバンプ５９を形成した状態を示す。   FIG. 4 shows a step of forming a wiring substrate by forming connection electrodes on the outer surface of the buildup layer 60 bonded to the core substrate 22. FIG. 4A shows a land pattern 56 for forming a connection electrode by applying a photosensitive solder resist 54 to the outer surface of the buildup layer 60, exposing and developing, and the wiring pattern 20 on the lower surface of the core substrate 22. The state where is exposed. 4B shows a state in which a protective plating 58 by electroless nickel plating and electroless gold plating is formed on the surface of the land portion 56 and the wiring pattern 20 on the lower surface of the core substrate 22, and FIG. 4C shows the land portion. 56 shows a state in which solder is printed and solder bumps 59 are formed as connection electrodes by solder reflow.

図４（ｃ）は大判の基板の状態のものであり、この大判の基板を切断することによって個片の配線基板が得られる。   FIG. 4C shows a state of a large-sized substrate, and an individual wiring substrate can be obtained by cutting the large-sized substrate.

本実施形態の配線基板の製造方法は、配線基板の配線層となるビルドアップ層６０と配線基板のコアとなるコア基板２２とを別個に製作し、後工程でビルドアップ層６０とコア基板２２とを組み合わせて配線基板を形成するものである。このようにビルドアップ層６０とコア基板２２とを各々別個に独立した工程で作成する方法であれば、ビルドアップ層６０を形成する際には、コア基板２２の制約を受けることなく配線パターン４４を形成することが可能であり、高密度配線が可能なビルドアップ法の特徴を生かして配線パターン４４を形成することができる。一方、コア基板２２についても、基材として所要の剛性を備える素材や厚さを選択することができる。すなわち、本実施形態の配線基板の製造方法によれば、半導体チップを搭載する配線基板に求められる高密度化と高剛性化をともに満足する配線基板を確実に製造することが可能になる。   In the method of manufacturing the wiring board according to the present embodiment, the buildup layer 60 that becomes the wiring layer of the wiring board and the core board 22 that becomes the core of the wiring board are separately manufactured, and the buildup layer 60 and the core board 22 are manufactured in a later process. Are combined to form a wiring board. In this way, if the build-up layer 60 and the core substrate 22 are each formed by a separate and independent process, the wiring pattern 44 is not limited by the core substrate 22 when the build-up layer 60 is formed. The wiring pattern 44 can be formed by taking advantage of the feature of the build-up method capable of high-density wiring. On the other hand, for the core substrate 22, a material or thickness having a required rigidity can be selected as a base material. That is, according to the method for manufacturing a wiring board of the present embodiment, it is possible to reliably manufacture a wiring board that satisfies both high density and high rigidity required for a wiring board on which a semiconductor chip is mounted.

なお、上記実施形態においてはコア基板２２にスルーホールと配線パターン２０を形成したが、コア基板２２はスルーホールと配線パターンがないものであってもよい。したがって、プリプレグ５０に導電性ペースト５２等の導電材を設けなくてもよい。   In the above embodiment, the through hole and the wiring pattern 20 are formed in the core substrate 22. However, the core substrate 22 may have no through hole and a wiring pattern. Therefore, the prepreg 50 may not be provided with a conductive material such as the conductive paste 52.

図５は、上述した方法によって形成した配線基板７０に半導体チップ７２を搭載した半導体装置の例を示す。この半導体装置は、半導体チップ７２の搭載位置に合わせて素子搭載孔１０ｂを設けたコア基板２２を使用し、半導体チップ７２を搭載した直下に回路部品７４を搭載可能としたものである。コア基板２２にこのような素子搭載孔１０ｂを形成しておけば、キャパシター等の回路部品７４はビルドアップ層６０のみを介して半導体チップ７２と電気的に接続されることになり、この素子搭載孔１０ｂが形成された部分では配線基板は実質的に薄く形成されたこととなり、半導体チップ７２と回路部品７４とを接続する配線長を短くすることができ、高周波特性の優れた半導体装置として提供することが可能になる。   FIG. 5 shows an example of a semiconductor device in which a semiconductor chip 72 is mounted on a wiring board 70 formed by the above-described method. This semiconductor device uses the core substrate 22 provided with the element mounting hole 10b in accordance with the mounting position of the semiconductor chip 72, so that the circuit component 74 can be mounted immediately under the semiconductor chip 72 mounted. If such an element mounting hole 10b is formed in the core substrate 22, the circuit component 74 such as a capacitor is electrically connected to the semiconductor chip 72 only through the buildup layer 60. In the portion where the hole 10b is formed, the wiring board is formed substantially thin, the wiring length connecting the semiconductor chip 72 and the circuit component 74 can be shortened, and provided as a semiconductor device having excellent high frequency characteristics. It becomes possible to do.

（実施形態２）
本実施形態は、図１２に示す方法によってコア基板１０を形成した後、低熱膨張係数を有する金属箔をビルドアップ層に組み込むことによって、半導体チップの熱膨張係数に近づけた配線基板を製造する方法に関するものである。 (Embodiment 2)
In the present embodiment, after the core substrate 10 is formed by the method shown in FIG. 12, a metal substrate having a low thermal expansion coefficient is incorporated into the build-up layer, thereby manufacturing a wiring board close to the thermal expansion coefficient of the semiconductor chip. It is about.

図６（ａ）は、コア基板２２の両面にビルドアップ層６０を形成した状態を示す。４４が配線パターン、４６が絶縁層、４８がビアである。   FIG. 6A shows a state in which build-up layers 60 are formed on both surfaces of the core substrate 22. Reference numeral 44 denotes a wiring pattern, 46 denotes an insulating layer, and 48 denotes a via.

図６（ｂ）は、４２合金等の銅よりも小さな熱膨張係数を有する金属箔８０の片面に接着剤層８２が被着された接着剤付金属箔８４に、ドリル加工、レーザ加工、エッチング加工等により孔８４ａを形成した状態を示す。孔８４ａは接着剤付金属箔８４をビルドアップ層６０に接着した際に、ビルドアップ層６０に形成されている配線パターン４４と干渉しないように設ける。   FIG. 6B shows drilling, laser processing, etching on a metal foil with adhesive 84 in which an adhesive layer 82 is attached to one side of a metal foil 80 having a smaller thermal expansion coefficient than copper such as 42 alloy. A state in which the hole 84a is formed by processing or the like is shown. The holes 84 a are provided so as not to interfere with the wiring pattern 44 formed in the buildup layer 60 when the adhesive-attached metal foil 84 is bonded to the buildup layer 60.

図６（ｃ）は、コア基板２２に接着剤付金属箔８４を位置合わせした状態、図６（ｄ）は、コア基板２２に接着剤付金属箔８４を熱圧着して貼り付けた状態を示す。   6C shows a state in which the metal foil 84 with an adhesive is aligned with the core substrate 22, and FIG. 6D shows a state in which the metal foil 84 with an adhesive is bonded to the core substrate 22 by thermocompression bonding. Show.

図７（ａ）は、ビルドアップ層６０の表面に感光性のソルダーレジスト５４を塗布し、露光および現像してランド部５６を露出させた状態を示す。金属箔８０はソルダーレジスト５４に被覆されてビルドアップ層６０に組み込まれる。図７（ｂ）は、ランド部５６およびコア基板２２の下面の配線パターン４４の露出面を保護めっき５８によって被覆した状態を示す。図７（ｃ）は、ランド部５６にはんだを印刷し、はんだリフローによってはんだバンプ５９を形成して配線基板とした状態を示す。   FIG. 7A shows a state in which a photosensitive solder resist 54 is applied to the surface of the buildup layer 60, and the land portion 56 is exposed by exposure and development. The metal foil 80 is covered with the solder resist 54 and incorporated into the buildup layer 60. FIG. 7B shows a state in which the exposed surface of the wiring pattern 44 on the lower surface of the land portion 56 and the core substrate 22 is covered with the protective plating 58. FIG. 7C shows a state in which solder is printed on the land portion 56 and solder bumps 59 are formed by solder reflow to form a wiring board.

本実施形態の配線基板は、コア基板２２の両面に形成されたビルドアップ層６０に低熱膨張係数を有する金属箔８０が組み込まれていることによって、ビルドアップ層６０の熱膨張係数を引き下げるとともに、配線基板全体としての熱膨張係数を半導体チップの熱膨張係数に近づけたものである。本実施形態ではビルドアップ層６０の最外層に、低熱膨張係数を有する金属箔８０を配置する構成としている。金属箔８０を１層のみビルドアップ層６０に組み込む場合は、このようにビルドアップ層６０の最外層に組み込む方法が効果的である。   The wiring board according to the present embodiment reduces the thermal expansion coefficient of the buildup layer 60 by incorporating the metal foil 80 having a low thermal expansion coefficient into the buildup layer 60 formed on both surfaces of the core substrate 22. The thermal expansion coefficient of the entire wiring board is close to the thermal expansion coefficient of the semiconductor chip. In the present embodiment, the metal foil 80 having a low thermal expansion coefficient is disposed in the outermost layer of the buildup layer 60. When only one metal foil 80 is incorporated in the buildup layer 60, a method of incorporating the metal foil 80 in the outermost layer of the buildup layer 60 in this way is effective.

図８〜１０は、ビルドアップ層６０の中間層に低熱膨張係数を有する金属箔８０を組み込んだ配線基板を製造する方法を示す。   8 to 10 show a method of manufacturing a wiring board in which a metal foil 80 having a low thermal expansion coefficient is incorporated in an intermediate layer of the buildup layer 60. FIG.

図８（ａ）は、コア基板２２の両面にビルドアップ層６０を中途層まで形成した状態を示す。低熱膨張係数を有する金属箔８０を備えた接着剤付金属箔８４を、ビルドアップ層６０を形成したコア基板２２の両面に位置合わせし（図８（ｂ））、コア基板２２の両面に接着剤付金属箔８４を貼り付ける（図８（ｃ））。接着剤付金属箔８４を貼り付ける際に、接着剤層８２を既設のビルドアップ層６０に向けて貼り付けることによって、接着剤層８２を介して金属箔８０が接着される。   FIG. 8A shows a state in which build-up layers 60 are formed on both surfaces of the core substrate 22 up to the mid layer. The adhesive-attached metal foil 84 provided with the metal foil 80 having a low thermal expansion coefficient is aligned with both surfaces of the core substrate 22 on which the build-up layer 60 is formed (FIG. 8B) and adhered to both surfaces of the core substrate 22. The metal foil 84 with an agent is affixed (FIG. 8C). When the metal foil with adhesive 84 is attached, the metal foil 80 is bonded via the adhesive layer 82 by attaching the adhesive layer 82 toward the existing buildup layer 60.

図９（ａ）は、フォトリソグラフィー法によって最外面の金属箔８０をエッチングして所定のパターンに形成した状態を示す。８０ａがパターニングされた金属箔である。図９（ｂ）は、金属箔８０ａが形成されている層の表面を絶縁樹脂によって被覆して絶縁層４６を形成した状態を示す。金属箔８０ａと絶縁層４６ａとの密着性を良好にするため、金属箔８０ａの表面に粗化処理を施してもよい。図９（ｃ）は、ビルドアップ法により下層の配線パターン４４と電気的に接続するように上層の配線パターン４４を形成した状態を示す。この工程では、接着剤層８２と絶縁層４６ａが配線層間に設けられた絶縁層になる。金属箔８０ａは層間で配線パターン４４を電気的に接続するビア４８の配置を妨げないようなパターンに形成されている。   FIG. 9A shows a state in which the outermost metal foil 80 is etched into a predetermined pattern by photolithography. 80a is a patterned metal foil. FIG. 9B shows a state in which the insulating layer 46 is formed by covering the surface of the layer on which the metal foil 80a is formed with an insulating resin. In order to improve the adhesion between the metal foil 80a and the insulating layer 46a, the surface of the metal foil 80a may be roughened. FIG. 9C shows a state in which the upper wiring pattern 44 is formed so as to be electrically connected to the lower wiring pattern 44 by the build-up method. In this step, the adhesive layer 82 and the insulating layer 46a become an insulating layer provided between the wiring layers. The metal foil 80a is formed in a pattern that does not hinder the arrangement of the vias 48 that electrically connect the wiring patterns 44 between the layers.

図１０（ａ）は、ビルドアップ層６０の表面に感光性のソルダーレジスト５４を塗布し、露光および現像してランド部５６を露出させた工程、図１０（ｂ）は、ランド部５６および配線パターン４４の露出部に保護めっき５８を設ける工程、図１０（ｃ）は、ランド部５６にはんだを印刷し、はんだリフローによってはんだバンプ５９を形成して配線基板を形成する工程を示す。   FIG. 10A shows a process in which a photosensitive solder resist 54 is applied to the surface of the buildup layer 60, and exposure and development are performed to expose the land portion 56. FIG. 10B shows the land portion 56 and the wiring. FIG. 10C shows a step of forming a wiring board by printing solder on the land portion 56 and forming solder bumps 59 by solder reflow.

本実施形態の配線基板の製造方法によれば、ビルドアップ層６０の中間層に低熱膨張係数を有する金属箔８０ａが組み込まれた配線基板を製造することができる。このように、ビルドアップ層６０の中間層に金属箔８０ａを組み込むことによっても、配線基板全体としての熱膨張係数を半導体チップの熱膨張係数に近づけることが可能である。なお、ビルドアップ層６０に組み込む金属箔８０は１層に限らず、複数層に設けることができる。   According to the method for manufacturing a wiring board of the present embodiment, a wiring board in which the metal foil 80 a having a low thermal expansion coefficient is incorporated in the intermediate layer of the buildup layer 60 can be manufactured. Thus, by incorporating the metal foil 80a into the intermediate layer of the buildup layer 60, the thermal expansion coefficient of the entire wiring board can be brought close to the thermal expansion coefficient of the semiconductor chip. In addition, the metal foil 80 incorporated in the buildup layer 60 is not limited to one layer, and can be provided in a plurality of layers.

これらの配線基板の製造方法では、コア基板２２の両面にビルドアップ層６０を形成する際に、ビルドアップ法と同様な方法によって低熱膨張係数を有する金属箔８０を埋設させることができ、ビルドアップによって配線パターンを形成する工程に金属箔８０を組み込む工程を組み入れて配線基板を製造することができるという利点がある。   In these wiring board manufacturing methods, when the build-up layers 60 are formed on both surfaces of the core substrate 22, the metal foil 80 having a low thermal expansion coefficient can be embedded by a method similar to the build-up method. Thus, there is an advantage that a wiring board can be manufactured by incorporating a step of incorporating the metal foil 80 into the step of forming a wiring pattern.

図１１は、低熱膨張係数を有する金属箔８０を組み込んだ配線基板に半導体チップ７２を搭載した半導体装置の例を示す。図示した配線基板はビルドアップ層６０の最外層に金属箔８０を組み込んだものである。低熱膨張係数の金属箔８０を組み込むことによって配線基板の熱膨張係数を半導体チップの熱膨張係数に近づけることができ、半導体チップと配線基板との間で生じる熱応力を抑えることができ、信頼性の高い半導体装置として提供することが可能となる。   FIG. 11 shows an example of a semiconductor device in which a semiconductor chip 72 is mounted on a wiring board incorporating a metal foil 80 having a low thermal expansion coefficient. The illustrated wiring board is obtained by incorporating a metal foil 80 into the outermost layer of the buildup layer 60. By incorporating the metal foil 80 having a low thermal expansion coefficient, the thermal expansion coefficient of the wiring board can be brought close to the thermal expansion coefficient of the semiconductor chip, and the thermal stress generated between the semiconductor chip and the wiring board can be suppressed, and the reliability is improved. Therefore, it can be provided as a high-semiconductor device.

図１（ａ）−（ｄ）は支持体の両面にビルドアップ層を形成する工程を示す説明図である。FIGS. 1A to 1D are explanatory views showing a process of forming buildup layers on both surfaces of a support. 図２（ａ）、（ｂ）は支持体とビルドアップ層との積層体とコア基板とを接合する工程を示す説明図である。FIGS. 2A and 2B are explanatory views showing a process of joining a laminated body of a support and a buildup layer and a core substrate. 図３（ａ）−（ｄ）は積層体からコア基板とビルドアップ層との接合体を分離する工程を示す説明図である。FIGS. 3A to 3D are explanatory views showing a process of separating the joined body of the core substrate and the buildup layer from the laminate. 図４（ａ）−（ｃ）はコア基板とビルドアップ層とからなる配線基板を形成する工程を示す説明図である。FIGS. 4A to 4C are explanatory views showing a process of forming a wiring board composed of a core substrate and a buildup layer. 図５は配線基板に半導体チップを搭載した半導体装置の構成を示す断面図である。FIG. 5 is a cross-sectional view showing a configuration of a semiconductor device in which a semiconductor chip is mounted on a wiring board. 図６（ａ）−（ｄ）は低熱膨張係数の金属箔をビルドアップ層に組み込む工程を示す説明図である。FIGS. 6A to 6D are explanatory views showing a process of incorporating a metal foil having a low thermal expansion coefficient into the build-up layer. 図７（ａ）−（ｃ）は金属箔を組み込んだ配線基板を形成する工程を示す説明図である。FIGS. 7A to 7C are explanatory views showing a process of forming a wiring board incorporating a metal foil. 図８（ａ）−（ｃ）はビルドアップ層に金属箔を組み込む他の方法を示す説明図である。FIGS. 8A to 8C are explanatory views showing another method for incorporating a metal foil into the buildup layer. 図９（ａ）−（ｃ）は金属箔を組み込んでビルドアップ層を形成する工程を示す説明図である。FIGS. 9A to 9C are explanatory views showing a process of forming a build-up layer by incorporating a metal foil. 図１０（ａ）−（ｃ）は金属箔を組み込んだ配線基板を形成する工程を示す説明図である。FIGS. 10A to 10C are explanatory views showing a process of forming a wiring board incorporating a metal foil. 図１１は配線基板に半導体チップを搭載した半導体装置の構成を示す断面図である。FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device in which a semiconductor chip is mounted on a wiring board. 図１２（ａ）−（ｆ）はコア基板を形成する従来方法を示す説明図である。12A to 12F are explanatory views showing a conventional method for forming a core substrate. 図１３（ａ）−（ｄ）はコア基板の両面にビルドアップ層を形成した配線基板の製造工程を示す説明図である。FIGS. 13A to 13D are explanatory views showing a manufacturing process of a wiring board in which build-up layers are formed on both surfaces of the core board.

Claims (3)

コア基板の両面にビルドアップ層を形成してなる配線基板の製造方法において、
前記ビルドアップ層を形成する際に、銅よりも小さな熱膨張係数を有する金属箔を、ビルドアップ層の中間層に形成される配線パターンと干渉しない配置で該ビルドアップ層の中間層に組み込むことを特徴とする配線基板の製造方法。 In the manufacturing method of the wiring board formed by forming build-up layers on both sides of the core board,
When forming the buildup layer, a metal foil having a smaller thermal expansion coefficient than copper, be incorporated into the intermediate layer of the buildup layer in an arrangement that does not interfere with the wiring patterns formed on the intermediate layer of the buildup layer A method of manufacturing a wiring board characterized by the above. 金属箔の片面に接着剤層が被着された接着剤付金属箔を前記ビルドアップ層の中間層に積層することにより、該ビルドアップ層の中間層に金属箔を組み込むことを特徴とする請求項１記載の配線基板の製造方法。 By laminating the adhesive coated metal foil on which the adhesive layer has been deposited on one surface of the metal foil to the intermediate layer of the buildup layer, wherein, wherein the incorporation of metal foil in the middle layer of the buildup layer Item 4. A method for manufacturing a wiring board according to Item 1. 前記ビルドアップ層の中間層は、複数の中間層であることを特徴とする請求項１または請求項２記載の配線基板の製造方法。The method of manufacturing a wiring board according to claim 1, wherein the intermediate layer of the buildup layer is a plurality of intermediate layers.
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