JP4608284B2 - Power factor correction equipment - Google Patents

Power factor correction equipment Download PDF

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JP4608284B2
JP4608284B2 JP2004319122A JP2004319122A JP4608284B2 JP 4608284 B2 JP4608284 B2 JP 4608284B2 JP 2004319122 A JP2004319122 A JP 2004319122A JP 2004319122 A JP2004319122 A JP 2004319122A JP 4608284 B2 JP4608284 B2 JP 4608284B2
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boost chopper
chopper circuits
power factor
factor correction
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JP2006136046A (en
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毅 鐘ヶ江
幸輔 伊藤
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Foster Electric Co Ltd
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Description

本発明は、昇圧チョッパ回路を用いる力率改善装置に関する。   The present invention relates to a power factor correction apparatus using a boost chopper circuit.

この種の力率改善装置として、図９に示すようなものが知られている。同図に示すように、力率改善装置は、インダクタＬ１とスイッチング素子Ｑ１とダイオードＤ１をＴ型接続してなる昇圧チョッパ回路を有し、整流回路１で商用電源の交流を整流して得られる脈流を昇圧チョッパ回路で昇圧チョッピングし、その出力をキャパシタＣ１で平滑して負荷に供給するようになっている。昇圧チョッパ回路のスイッチング素子Ｑ１は制御部２によって制御される（例えば、特許文献１参照）。   As this type of power factor correction apparatus, one shown in FIG. 9 is known. As shown in the figure, the power factor correction apparatus has a step-up chopper circuit formed by connecting an inductor L1, a switching element Q1, and a diode D1 in a T-shape, and is obtained by rectifying AC of a commercial power supply by the rectifier circuit 1. The pulsating flow is boosted and chopped by a boosting chopper circuit, and the output is smoothed by a capacitor C1 and supplied to a load. The switching element Q1 of the step-up chopper circuit is controlled by the control unit 2 (see, for example, Patent Document 1).

制御部２は、分圧抵抗Ｒ１，Ｒ２によって得られる昇圧チョッパ回路の入力電圧の検出値ｅａ、電流検出抵抗Ｒｏによって得られる昇圧チョッパ回路の入力電流の検出値ｅｃおよび分圧抵抗Ｒ３，Ｒ４によって得られるキャパシタＣ１の出力電圧の検出値ｅｂに基づく制御信号Ｇ１で、スイッチング素子Ｑ１を制御する。   The control unit 2 uses the detected value ea of the input voltage of the boost chopper circuit obtained by the voltage dividing resistors R1 and R2, the detected value ec of the input current of the boost chopper circuit obtained by the current detecting resistor Ro, and the voltage dividing resistors R3 and R4. The switching element Q1 is controlled by the control signal G1 based on the detected output value eb of the output voltage of the capacitor C1.

制御部２は、誤差増幅器２０１で基準値Ｖｒｅｆと出力電圧検出値ｅｂとの差を増幅し、乗算器２０２で入力電圧検出値ｅａと誤差増幅出力Ｖｃとを乗算し、増幅器２０３で乗算器２０２の出力信号Ｖｍと入力電流検出値ｅｃとの差を増幅し、この増幅出力を比較器２０４で鋸歯状波発生器２０５の出力と比較することにより、パルス幅変調された制御信号Ｇ１を得ている。   The control unit 2 amplifies the difference between the reference value Vref and the output voltage detection value eb by the error amplifier 201, multiplies the input voltage detection value ea and the error amplification output Vc by the multiplier 202, and multiplies the multiplier 202 by the amplifier 203. The difference between the output signal Vm and the input current detection value ec is amplified, and the amplified output is compared with the output of the sawtooth wave generator 205 by the comparator 204 to obtain a pulse width modulated control signal G1. Yes.

この力率改善回路の各部の電圧・電流波形は図１０に示すようになる。すなわち、商用電源の電圧ｅ１は正弦波の交流であり、昇圧チョッパ回路の入力電圧│ｅ１│は正弦波を全波整流した脈流波形となる。   The voltage / current waveform of each part of the power factor correction circuit is as shown in FIG. That is, the voltage e1 of the commercial power supply is a sine wave AC, and the input voltage | e1 | of the boost chopper circuit is a pulsating waveform obtained by full-wave rectifying the sine wave.

昇圧チョッパ回路の入力電流ｉｏは、正弦波を全波整流した脈流波形にリップルが重畳したものとなる。リップルが重畳しているものの、入力電流ｉｏは入力電圧│ｅ１│と位相が一致したものとなるので力率が改善される。   The input current io of the step-up chopper circuit is a ripple superimposed on a pulsating waveform obtained by full-wave rectification of a sine wave. Although the ripple is superimposed, the input current io is in phase with the input voltage | e1 |, so that the power factor is improved.

リップルはスイッチング素子Ｑ１のスイッチング周波数に対応した高周波成分であり、商用電源につながる他の機器に対してノイズとなるので、それを許容範囲まで低減するために商用電源側にラインフィルタ３が設けられる。   The ripple is a high-frequency component corresponding to the switching frequency of the switching element Q1, and becomes a noise for other devices connected to the commercial power supply. Therefore, the line filter 3 is provided on the commercial power supply side in order to reduce it to an allowable range. .

リップルを含む入力電流ｉｏを微視的に見れば、図１１に示すようになる。同図においてΔＩがリップルの振幅である。このリップルは、パルス幅変調信号Ｇ１によるスイッチング素子Ｑ１のオン・オフに伴い、オン時にスイッチング素子Ｑ１に流れる上昇電流ｉQ1と、オフ時にダイオードＤ１に流れる下降電流ｉD1によって生じる。
特開２０００−３４１９５７号公報（第２−３頁、図４） A microscopic view of the input current io including ripples is as shown in FIG. In the figure, ΔI is the ripple amplitude. This ripple is caused by the rising current i Q1 flowing through the switching element Q1 when the switching element Q1 is turned on and the falling current i D1 flowing through the diode D1 when the switching element Q1 is turned off, as the switching element Q1 is turned on / off by the pulse width modulation signal G1.
JP 2000-341957 A (page 2-3, FIG. 4)

力率改善回路では、リップルまたはそれに起因するノイズをできるだけ小さくすることが求められる。リップル低減にはインダクタＬ１のインダクタンスを高めるのが効果的であり、ノイズ低減にはラインフィルタ３を強化すればよいが、いずれも部品寸法が大きくなるという問題がある。スイッチング素子Ｑ１のスイッチング周波数を高めてリップルの周波数を高めればラインフィルタ３の効きがよくなるが、反面でスイッチング素子Ｑ１のスイッチング損失が増加する。   In the power factor correction circuit, it is required to reduce the ripple or noise caused by the ripple as much as possible. Increasing the inductance of the inductor L1 is effective for reducing the ripple, and the line filter 3 may be strengthened for reducing the noise. If the switching frequency of the switching element Q1 is increased to increase the ripple frequency, the effect of the line filter 3 is improved, but on the other hand, the switching loss of the switching element Q1 increases.

また、電流のリップルは出力を平滑するキャパシタ素子の寿命に影響するので、複数のキャパシタ素子を並列に接続し、１個当たりの電流リップルが許容範囲に納まるようにしているが、大電力になるほど電流が増加するので対策の困難性が増す。   Also, since current ripple affects the life of capacitor elements that smooth the output, a plurality of capacitor elements are connected in parallel so that the current ripple per unit falls within an allowable range. Since current increases, the difficulty of countermeasures increases.

そこで、本発明の課題は、電流リップルが小さい力率改善装置を実現することである。   Therefore, an object of the present invention is to realize a power factor correction apparatus with a small current ripple.

上記の課題を解決するための請求項１に係る発明は、商用電源の交流を整流する整流回路と、互いに並列に接続され前記整流回路の出力をそれぞれ昇圧チョッピングする複数の昇圧チョッパ回路と、前記複数の昇圧チョッパ回路の出力を平滑して負荷に供給するキャパシタと、前記複数の昇圧チョッパ回路の入力電圧と入力電流および前記キャパシタの出力電圧に基づいて前記複数の昇圧チョッパ回路を互いに異なる位相で動作するように制御する制御部であって、誤差増幅器で前記出力電圧の検出値と基準値との差を増幅し、乗算器で前記入力電圧の検出値と前記誤差増幅の出力とを乗算し、増幅器で前記乗算器の出力と前記入力電流の検出値との差を増幅し、この増幅出力を、複数の比較器で、複数の鋸歯状波発生器のうちの一つ鋸歯状波発生器の出力の予め定められた位相において他の鋸歯状波発生器の出力をリセットする遅延回路により複数の出力の相互間に位相差が持たされた複数の鋸歯状波発生器の出力とそれぞれ比較することによって、パルス幅変調された複数の制御信号をそれぞれ得る制御部と、を具備することを特徴とする力率改善装置である。 The invention according to claim 1 for solving the above-described problems includes a rectifier circuit that rectifies an alternating current of a commercial power supply, a plurality of boost chopper circuits that are connected in parallel to each other and boost chopping the output of the rectifier circuit, and Capacitors that smooth the outputs of the plurality of boost chopper circuits and supply them to the load, and the plurality of boost chopper circuits in different phases based on the input voltage and input current of the plurality of boost chopper circuits and the output voltage of the capacitors. A control unit that controls the operation so that an error amplifier amplifies a difference between the detected value of the output voltage and a reference value, and a multiplier multiplies the detected value of the input voltage by the error amplification output; The amplifier amplifies the difference between the output of the multiplier and the detected value of the input current, and amplifies the amplified output by a plurality of comparators, one of the plurality of sawtooth wave generators. The outputs of the plurality of sawtooth wave generators having a phase difference between the plurality of outputs by a delay circuit that resets the outputs of the other sawtooth wave generators at a predetermined phase of the generator output, respectively. And a control unit that obtains a plurality of pulse-width-modulated control signals by comparison, respectively .

上記の課題を解決するための請求項２に係る発明は、前記複数の昇圧チョッパ回路の入力電流が個々の昇圧チョッパ回路ごとの入力電流である、ことを特徴とする請求項１に記載の力率改善装置である。   The invention according to claim 2 for solving the above problem is characterized in that the input current of the plurality of boost chopper circuits is an input current for each boost chopper circuit. It is a rate improvement device.

上記の課題を解決するための請求項３に係る発明は、前記複数の昇圧チョッパ回路の個数が２である、ことを特徴とする請求項１または請求項２に記載の力率改善装置である。
上記の課題を解決するための請求項４に係る発明は、前記制御部が前記２つの昇圧チョッパ回路を１／２周期の位相差で動作するように制御する、ことを特徴とする請求項３に記載の力率改善装置である。 The invention according to claim 3 for solving the above-mentioned problem is the power factor correction apparatus according to claim 1, wherein the number of the plurality of step-up chopper circuits is two. .
The invention according to claim 4 for solving the above-described problem is characterized in that the control unit controls the two boost chopper circuits so as to operate with a phase difference of ½ period. It is a power factor improvement apparatus as described in above.

請求項１に係る発明によれば、力率改善装置が、商用電源の交流を整流する整流回路と、互いに並列に接続され前記整流回路の出力をそれぞれ昇圧チョッピングする複数の昇圧チョッパ回路と、前記複数の昇圧チョッパ回路の出力を平滑して負荷に供給するキャパシタと、前記複数の昇圧チョッパ回路の入力電圧と入力電流および前記キャパシタの出力電圧に基づいて前記複数の昇圧チョッパ回路を互いに異なる位相で動作するように制御する制御部であって、誤差増幅器で前記出力電圧の検出値と基準値との差を増幅し、乗算器で前記入力電圧の検出値と前記誤差増幅の出力とを乗算し、増幅器で前記乗算器の出力と前記入力電流の検出値との差を増幅し、この増幅出力を、複数の比較器で、複数の鋸歯状波発生器のうちの一つ鋸歯状波発生器の出力の予め定められた位相において他の鋸歯状波発生器の出力をリセットする遅延回路により複数の出力の相互間に位相差が持たされた複数の鋸歯状波発生器の出力とそれぞれ比較することによって、パルス幅変調された複数の制御信号をそれぞれ得る制御部とを具備するので、電流リップルが小さい力率改善装置を実現することができる。 According to the first aspect of the present invention, a power factor correction apparatus includes: a rectifier circuit that rectifies an alternating current of a commercial power supply; a plurality of boost chopper circuits that are connected in parallel to each other and perform boost chopping on the output of the rectifier circuit; A capacitor that smoothes the outputs of the plurality of boost chopper circuits and supplies them to the load, and the plurality of boost chopper circuits in different phases based on the input voltage and input current of the plurality of boost chopper circuits and the output voltage of the capacitor. A control unit that controls the operation so that an error amplifier amplifies a difference between the detected value of the output voltage and a reference value, and a multiplier multiplies the detected value of the input voltage by the error amplification output; The amplifier amplifies the difference between the output of the multiplier and the detected value of the input current, and the amplified output is generated by a plurality of comparators to generate a sawtooth wave from one of the plurality of sawtooth generators. Each of the outputs of a plurality of sawtooth wave generators having a phase difference between them by a delay circuit that resets the output of another sawtooth wave generator at a predetermined phase of the output of the generator. Thus, a control unit that obtains each of the plurality of pulse width modulated control signals is provided, so that a power factor improvement device with a small current ripple can be realized.

また、リップル周波数の上昇によりラインフィルタによる抑制が容易になる。また、キャパシタについてのリップル条件が緩和され、大電力化あるいは超寿命化への対応が容易になる。また、昇圧チョッパ回路の並列化も、回路素子の発熱の分散により大電力化および高信頼化に効果がある。   Moreover, suppression by a line filter is facilitated by an increase in the ripple frequency. Further, the ripple condition for the capacitor is relaxed, and it becomes easy to cope with the increase in power or the extension of life. Further, paralleling the boost chopper circuit is also effective in increasing the power and the reliability due to the dispersion of the heat generated by the circuit elements.

請求項２に係る発明によれば、前記複数の昇圧チョッパ回路の入力電流が個々の昇圧チョッパ回路ごとの入力電流であるので、個々の昇圧チョッパ回路単位で力率改善を行うことができる。   According to the second aspect of the present invention, since the input current of the plurality of boost chopper circuits is the input current for each boost chopper circuit, the power factor can be improved for each boost chopper circuit.

請求項３に係る発明によれば、前記複数の昇圧チョッパ回路の個数が２であるので、最小の並列数で電流リップルを小さくすることができる。
請求項４に係る発明によれば、前記制御部が前記２つの昇圧チョッパ回路を１／２周期の位相差で動作するように制御するので、２つの昇圧チョッパ回路における電流リップルの位相差が１／２周期となって合成の電流リップルが最小化される。 According to the invention of claim 3, since the number of the plurality of step-up chopper circuits is 2, the current ripple can be reduced with the minimum number of parallel circuits.
According to the invention of claim 4, since the control unit controls the two boost chopper circuits to operate with a phase difference of ½ cycle, the phase difference between the current ripples in the two boost chopper circuits is 1. / 2 cycles to minimize the combined current ripple.

以下、図面を参照して発明を実施するための最良の形態を詳細に説明する。なお、本発明は発明を実施するための最良の形態に限定されるものではない。図１に力率改善装置の一例の電気的構成を示す。本装置は発明を実施するための最良の形態の一例である。本装置の構成によって、力率改善装置に関する発明を実施するための最良の形態の一例が示される。   The best mode for carrying out the invention will be described below in detail with reference to the drawings. The present invention is not limited to the best mode for carrying out the invention. FIG. 1 shows an electrical configuration of an example of the power factor correction apparatus. This apparatus is an example of the best mode for carrying out the invention. An example of the best mode for carrying out the invention relating to the power factor correction apparatus is shown by the configuration of the apparatus.

同図に示すように、本装置は、並列接続された２つの昇圧チョッパ回路１０１および１０２を有する。昇圧チョッパ回路１０１は、インダクタＬ１とスイッチング素子Ｑ１とダイオードＤ１をＴ型接続してなる。昇圧チョッパ回路１０２は、インダクタＬ２とスイッチング素子Ｑ２とダイオードＤ２をＴ型接続してなる。   As shown in the figure, this apparatus has two boost chopper circuits 101 and 102 connected in parallel. The step-up chopper circuit 101 is formed by connecting an inductor L1, a switching element Q1, and a diode D1 in a T shape. The step-up chopper circuit 102 has a T-type connection of an inductor L2, a switching element Q2, and a diode D2.

本装置は、商用電源の交流を整流回路１０で整流して得られる脈流を、制御部２０による制御の下で、昇圧チョッパ回路１０１，１０２によりそれぞれ昇圧チョッピングし、それらの出力をキャパシタＣ１で平滑して負荷に供給するようになっている。商用電源の交流はラインフィルタ３０を通じて供給される。   In this apparatus, the pulsating current obtained by rectifying the AC of the commercial power source with the rectifier circuit 10 is boosted and chopped by the boost chopper circuits 101 and 102 under the control of the control unit 20, and the output thereof is output by the capacitor C1. Smoothly supplied to the load. AC of the commercial power is supplied through the line filter 30.

整流回路１０は、本発明における整流回路の一例である。昇圧チョッパ回路１０１および１０２は、本発明における昇圧チョッパ回路の一例である。キャパシタＣ１は、本発明におけるキャパシタの一例である。制御部２０は、本発明における制御部の一例である。   The rectifier circuit 10 is an example of a rectifier circuit in the present invention. The step-up chopper circuits 101 and 102 are examples of the step-up chopper circuit in the present invention. The capacitor C1 is an example of a capacitor in the present invention. The control unit 20 is an example of a control unit in the present invention.

制御部２０は、分圧抵抗Ｒ１，Ｒ２によって得られる昇圧チョッパ回路１０１，１０２の入力電圧の検出値ｅａ、電流検出抵抗Ｒｏによって得られる昇圧チョッパ回路１０１，１０２の入力電流の検出値ｅｃおよび分圧抵抗Ｒ３，Ｒ４によって得られるキャパシタＣ１の出力電圧の検出値ｅｂに基づく制御信号Ｇ１，Ｇ２で、スイッチング素子Ｑ１，Ｑ２をそれぞれ制御する。   The control unit 20 detects the input voltage detection value ea of the boost chopper circuits 101 and 102 obtained by the voltage dividing resistors R1 and R2, the detection value ec of the input current of the boost chopper circuits 101 and 102 obtained by the current detection resistor Ro, The switching elements Q1 and Q2 are respectively controlled by control signals G1 and G2 based on the detected value eb of the output voltage of the capacitor C1 obtained by the resistors R3 and R4.

制御部２０は、図２に示すように、誤差増幅器２０１で基準値Ｖｒｅｆと出力電圧検出値ｅｂとの差を増幅し、乗算器２０２で入力電圧検出値ｅａと誤差増幅出力Ｖｃとを乗算し、増幅器２０３で乗算器２０２の出力信号Ｖｍと入力電流検出値ｅｃとの差を増幅し、この増幅出力を、比較器２１４，２２４で鋸歯状波発生器２１５，２２５の出力とそれぞれ比較することにより、パルス幅変調された制御信号Ｇ１，Ｇ２をそれぞれ得るようになっている。鋸歯状波発生器２１５，２２５の間には遅延回路２３０が設けられ、鋸歯状波発生器２１５，２２５の出力に位相差を生じさせるようになっている。   As shown in FIG. 2, the control unit 20 amplifies the difference between the reference value Vref and the output voltage detection value eb by the error amplifier 201, and multiplies the input voltage detection value ea and the error amplification output Vc by the multiplier 202. The amplifier 203 amplifies the difference between the output signal Vm of the multiplier 202 and the input current detection value ec, and the amplified outputs are compared with the outputs of the sawtooth wave generators 215 and 225 by the comparators 214 and 224, respectively. Thus, control signals G1 and G2 subjected to pulse width modulation are obtained. A delay circuit 230 is provided between the sawtooth wave generators 215 and 225 so as to cause a phase difference between the outputs of the sawtooth wave generators 215 and 225.

遅延回路２３０は、例えば図３に示すように、比較器２３２で、鋸歯状波発生器２１５の鋸歯状波を基準電圧Ｖｒの分圧抵抗Ｒ５，Ｒ６による分圧値Ｖｓと比較し、比較出力信号をキャパシタＣ２と抵抗Ｒ７にからなる微分回路で微分し、この微分出力信号で、鋸歯状波発生器２２５出力端に接続されたトランジスタＱ３を駆動するようになっている。   For example, as shown in FIG. 3, the delay circuit 230 compares the sawtooth wave of the sawtooth wave generator 215 with the divided voltage value Vs of the reference voltage Vr by the voltage dividing resistors R5 and R6 by the comparator 232, and outputs the comparison output. The signal is differentiated by a differentiation circuit composed of a capacitor C2 and a resistor R7, and the transistor Q3 connected to the output terminal of the sawtooth wave generator 225 is driven by this differential output signal.

この遅延回路２３０の働きにより、図４に示すように、鋸歯状波発生器２１５の出力電圧（鋸歯状波１）が電圧Ｖｓを超えるタイミングＳごとに、鋸歯状波発生器２２５の出力電圧（鋸歯状波２）がリセットされる。これによって、鋸歯状波２の周期が鋸歯状波１と同一化されるとともに、位相が鋸歯状波１に対して遅延される。遅延量は電圧Ｖｓに対応する。電圧Ｖｓは遅延量が１／２周期となるように設定される。鋸歯状波１，２が１／２周期の位相差を持つことにより、制御部２０の制御信号Ｇ１，Ｇ２は、図５に示すように、１／２周期の位相差を持つパルス幅変調信号となる。   Due to the action of the delay circuit 230, as shown in FIG. 4, at every timing S when the output voltage (sawtooth wave 1) of the sawtooth wave generator 215 exceeds the voltage Vs, the output voltage of the sawtooth wave generator 225 ( The sawtooth wave 2) is reset. As a result, the period of the sawtooth wave 2 is made the same as that of the sawtooth wave 1 and the phase is delayed with respect to the sawtooth wave 1. The delay amount corresponds to the voltage Vs. The voltage Vs is set so that the delay amount is ½ period. Since the sawtooth waves 1 and 2 have a phase difference of 1/2 cycle, the control signals G1 and G2 of the control unit 20 are pulse width modulation signals having a phase difference of 1/2 cycle as shown in FIG. It becomes.

このような制御信号Ｇ１，Ｇ２によってそれぞれ制御される昇圧チョッパ回路１０１，１０２では、それらの入力電流ｉL1，ｉL2が、図６に示すように、１／２周期の位相差のリップルを持つものとなる。 In the step-up chopper circuits 101 and 102 controlled by the control signals G1 and G2, respectively, their input currents i L1 and i L2 have a half-phase phase ripple as shown in FIG. It will be a thing.

これらリップルは、制御信号Ｇ１，Ｇ２によるスイッチング素子Ｑ１，Ｑ２のオン・オフに伴い、オン時にスイッチング素子Ｑ１，Ｑ２に流れる上昇電流と、オフ時にダイオードＤ１，Ｄ２に流れる下降電流によって生じる。   These ripples are caused by rising currents flowing through the switching elements Q1, Q2 when the switching elements Q1, Q2 are turned on and off by the control signals G1, G2, and falling currents flowing through the diodes D1, D2 when the switching elements are off.

入力電流ｉL1，ｉL2の和ｉｏが、昇圧チョッパ回路１０１，１０２全体としての入力電流となる。全入力電流ｉｏは、同図に示すように、個々の入力電流ｉL1，ｉL2に比べてリップルに振幅が小さくなり、かつ、周波数が２倍になる。これは、入力電流ｉL1，ｉL2のリップルが１／２周期の位相差を持つことにより、一方のリップルがリップル振幅の１／２より大きくなるとき、他方は必ずリップル振幅の１／２より小さくなるからである。 The sum io of the input currents i L1 and i L2 becomes the input current of the boost chopper circuits 101 and 102 as a whole. As shown in the figure, the total input current io has a smaller amplitude in ripple and doubles the frequency than the individual input currents i L1 and i L2 . This is because when the ripple of the input currents i L1 and i L2 has a phase difference of ½ period, when one of the ripples is larger than ½ of the ripple amplitude, the other is always more than ½ of the ripple amplitude. This is because it becomes smaller.

この力率改善回路の各部の電圧・電流波形は図１０に示したものと同じになる。すなわち、商用電源の電圧ｅ１は正弦波の交流であり、昇圧チョッパ回路の入力電圧│ｅ１│は正弦波を全波整流した脈流波形となる。昇圧チョッパ回路の入力電流ｉｏは、正弦波を全波整流した脈流波形にリップルが重畳したものとなる。リップルが重畳しているものの、入力電流ｉｏは入力電圧│ｅ１│と位相が一致したものとなるので力率が改善される。   The voltage / current waveform of each part of the power factor correction circuit is the same as that shown in FIG. That is, the voltage e1 of the commercial power supply is a sine wave AC, and the input voltage | e1 | of the boost chopper circuit is a pulsating waveform obtained by full-wave rectifying the sine wave. The input current io of the step-up chopper circuit is a ripple superimposed on a pulsating waveform obtained by full-wave rectification of a sine wave. Although the ripple is superimposed, the input current io is in phase with the input voltage | e1 |, so that the power factor is improved.

本装置は、図９の従来例に比べてリップルが約１／２に減少した力率改善装置となる。したがって、昇圧チョッパ回路１０１，１０２のインダクタＬ１，Ｌ２のインダクタンスをそれほど大きくしなくても十分なノイズ低減が可能である。また、リップルの振幅が低減しかつ周波数が２倍になるので、ラインフィルタ３０をそれほど強力なものにしなくても、十分なノイズ低減が可能である。なお、スイッチング周波数は変えないので、リップル周波数が２倍になるといってもスイッチング素子Ｑ１，Ｑ２のスイッチング損失が増加することはない。   This apparatus is a power factor correction apparatus in which the ripple is reduced to about ½ compared to the conventional example of FIG. Therefore, noise can be sufficiently reduced without increasing the inductances of the inductors L1 and L2 of the boost chopper circuits 101 and 102 so much. Further, since the amplitude of the ripple is reduced and the frequency is doubled, sufficient noise reduction is possible without making the line filter 30 so strong. Since the switching frequency is not changed, the switching loss of the switching elements Q1 and Q2 does not increase even if the ripple frequency is doubled.

また、制御信号Ｇ１，Ｇ２の位相差が１／２周期であるので、キャパシタＣ１の充電は、図６に示すように、１周期につき２度ずつ行われる。このため、１回当たりの充電電流が図９の従来例の半分になる。したがって、キャパシタＣ１についてのリップル条件が緩和され、大電力化あるいは超寿命化への対応が容易になる。また、昇圧チョッパ回路１０１，１０２の並列化も、回路素子の発熱の分散により大電力化および高信頼化に効果がある。   Further, since the phase difference between the control signals G1 and G2 is ½ cycle, the capacitor C1 is charged twice per cycle as shown in FIG. For this reason, the charging current per time is half that of the conventional example of FIG. Therefore, the ripple condition for the capacitor C1 is relaxed, and it becomes easy to cope with a high power or a long life. Further, the paralleling of the step-up chopper circuits 101 and 102 is effective in increasing the power and the reliability due to the dispersion of the heat generated by the circuit elements.

昇圧チョッパ回路の並列数は２つに限らず、それ以上としてもよい。昇圧チョッパ回路の並列数を一般的にｎ（２以上の整数）とした場合は、複数の昇圧チョッパ回路間の動作の位相差を１／ｎ周期ずつとする。これによって、リップルの周波数は昇圧チョッパ回路が１つのときのｎ倍に高まる。   The number of boost chopper circuits in parallel is not limited to two and may be more than that. When the parallel number of boost chopper circuits is generally n (an integer of 2 or more), the phase difference of the operation between the plurality of boost chopper circuits is set to 1 / n period. As a result, the frequency of the ripple is increased to n times that when there is one step-up chopper circuit.

なお、複数の昇圧チョッパ回路間の動作の位相差は、１／ｎ周期に限らず適宜の位相差としてよい。したがって、ｎ＝２のときでも位相差は１／２周期に限らずそれ以外の位相差としてもよい。ただし、ｎ＝２のときの１／２周期の位相差はリップルを最小化する点で好ましい。また、ｎ＝２とすることにより最小の並列数でリップル低減が可能である。   Note that the phase difference of the operation between the plurality of boost chopper circuits is not limited to the 1 / n cycle, and may be an appropriate phase difference. Therefore, even when n = 2, the phase difference is not limited to ½ period, but may be other phase differences. However, a half-cycle phase difference when n = 2 is preferable in terms of minimizing ripple. Further, by setting n = 2, it is possible to reduce the ripple with the minimum number of parallel.

図７に力率改善装置の他の例の電気的構成を示す。本装置は発明を実施するための最良の形態の一例である。本装置の構成によって、力率改善装置に関する発明を実施するための最良の形態の一例が示される。   FIG. 7 shows an electrical configuration of another example of the power factor correction apparatus. This apparatus is an example of the best mode for carrying out the invention. An example of the best mode for carrying out the invention relating to the power factor correction apparatus is shown by the configuration of the apparatus.

図７では、図１に示したものと同様な部分は同一の符号を付して説明を省略する。この例では、２つの昇圧チョッパ回路１０１’，１０２’が電流検出回路４１，４２をそれぞれ有し、これら電流検出回路４１，４２による電流検出値ｅc1，ｅc2が制御部２０’への入力となっている。制御部２０’には、また、分圧抵抗Ｒ１，Ｒ２による入力電圧検出値ｅａおよび分圧抵抗Ｒ３，Ｒ４による出力電圧検出値ｅｂも入力される。 In FIG. 7, the same parts as those shown in FIG. In this example, two boost chopper circuits 101 ′ and 102 ′ have current detection circuits 41 and 42, respectively, and current detection values e c1 and e c2 by the current detection circuits 41 and 42 are input to the control unit 20 ′. It has become. The control unit 20 ′ also receives an input voltage detection value ea by the voltage dividing resistors R1 and R2 and an output voltage detection value eb by the voltage dividing resistors R3 and R4.

制御部２０’の構成を図８に示す。図８では図２に示したものと同様な部分は同一の符号を付して説明を省略する。制御部２０’では、乗算器２０２の出力信号Ｖｍと電流検出値ｅc1との差が増幅器２１３で増幅され、その出力信号が比較器２１４で鋸歯状波発生器２１５の出力信号と比較されて制御信号Ｇ１が形成される。また、乗算器２０２の出力信号Ｖｍと電流検出値ｅc2との差が増幅器２２３で増幅され、その出力信号が比較器２２４で鋸歯状波発生器２２５の出力信号と比較されて制御信号Ｇ２が形成される。 The configuration of the control unit 20 ′ is shown in FIG. In FIG. 8, parts similar to those shown in FIG. In the control unit 20 ′, the difference between the output signal Vm of the multiplier 202 and the detected current value e c1 is amplified by the amplifier 213, and the output signal is compared with the output signal of the sawtooth wave generator 215 by the comparator 214. A control signal G1 is formed. Further, the difference between the output signal Vm of the multiplier 202 and the detected current value ec2 is amplified by the amplifier 223, and the output signal is compared with the output signal of the sawtooth generator 225 by the comparator 224, so that the control signal G2 is obtained. It is formed.

これによって、昇圧チョッパ回路１０１’，１０２’は、それぞれの回路における入力電流に基づいて個々に制御される。このため、本装置は、昇圧チョッパ回路１０１’，１０２’間での回路素子の特性のバラツキ等に影響されることなく、両回路間のバランスがとれた動作を行うことができる。この例でも昇圧チョッパ回路は２つに限らずそれ以上としてもよいのはいうまでもない。   Thus, the boost chopper circuits 101 'and 102' are individually controlled based on the input current in each circuit. Therefore, this apparatus can perform a balanced operation between both circuits without being affected by variations in circuit element characteristics between the boost chopper circuits 101 ′ and 102 ′. In this example as well, it goes without saying that the number of boost chopper circuits is not limited to two and may be more.

本発明を実施するための最良の形態の一例の力率改善装置の電気的構成を示す図である。It is a figure which shows the electric constitution of the power factor improvement apparatus of an example of the best form for implementing this invention. 制御部の電気的構成を示す図である。It is a figure which shows the electric constitution of a control part. 遅延回路の電気的構成を示す図である。It is a figure which shows the electrical structure of a delay circuit. 鋸歯状波発生器の出力信号を示す図である。It is a figure which shows the output signal of a sawtooth wave generator. 鋸歯状波と制御信号の関係を示す図である。It is a figure which shows the relationship between a sawtooth wave and a control signal. 制御信号と電流のリップルの関係を示す図である。It is a figure which shows the relationship between a control signal and the ripple of an electric current. 本発明を実施するための最良の形態の他の例の力率改善装置の電気的構成Electric configuration of power factor correction apparatus of another example of the best mode for carrying out the present invention 制御部の電気的構成を示す図である。It is a figure which shows the electric constitution of a control part. 力率改善装置の従来例の電気的構成を示す図である。It is a figure which shows the electrical structure of the prior art example of a power factor improvement apparatus. 力率改善装置の電圧波形および電流波形を示す図である。It is a figure which shows the voltage waveform and current waveform of a power factor improvement apparatus. 制御信号と電流のリップルの関係を示す図である。It is a figure which shows the relationship between a control signal and the ripple of an electric current.

符号の説明Explanation of symbols

１０ 整流回路
２０ 制御部
３０ ラインフィルタ
１０１，１０２ 昇圧チョッパ回路
Ｌ１，Ｌ２ インダクタ
Ｑ１，Ｑ２ スイッチング素子
Ｄ１，Ｄ２ ダイオード
Ｃ１ キャパシタ
Ｒ１，Ｒ２ 分圧抵抗
Ｒ３，Ｒ４ 分圧抵抗
Ｒ０ 電流検出抵抗
２０１ 誤差増幅器
２０２ 乗算器
２０３ 増幅器
２１４，２２４ 比較器
２１５，２２５ 鋸歯状波発生器
２４０ 遅延回路 DESCRIPTION OF SYMBOLS 10 Rectifier circuit 20 Control part 30 Line filter 101,102 Boost chopper circuit L1, L2 Inductor Q1, Q2 Switching element D1, D2 Diode C1 Capacitor R1, R2 Voltage dividing resistor R3, R4 Voltage dividing resistor R0 Current detection resistor 201 Error amplifier 202 Multiplier 203 Amplifier 214, 224 Comparator 215, 225 Sawtooth wave generator 240 Delay circuit

Claims (4)

商用電源の交流を整流する整流回路と、
互いに並列に接続され前記整流回路の出力をそれぞれ昇圧チョッピングする複数の昇圧チョッパ回路と、
前記複数の昇圧チョッパ回路の出力を平滑して負荷に供給するキャパシタと、
前記複数の昇圧チョッパ回路の入力電圧と入力電流および前記キャパシタの出力電圧に基づいて前記複数の昇圧チョッパ回路を互いに異なる位相で動作するように制御する制御部であって、誤差増幅器で前記出力電圧の検出値と基準値との差を増幅し、乗算器で前記入力電圧の検出値と前記誤差増幅の出力とを乗算し、増幅器で前記乗算器の出力と前記入力電流の検出値との差を増幅し、この増幅出力を、複数の比較器で、複数の鋸歯状波発生器のうちの一つ鋸歯状波発生器の出力の予め定められた位相において他の鋸歯状波発生器の出力をリセットする遅延回路により複数の出力の相互間に位相差が持たされた複数の鋸歯状波発生器の出力とそれぞれ比較することによって、パルス幅変調された複数の制御信号をそれぞれ得る制御部と、
を具備することを特徴とする力率改善装置。 A rectifier circuit for rectifying the AC of the commercial power supply;
A plurality of step-up chopper circuits connected in parallel to each other and step-up chopping the output of the rectifier circuit;
A capacitor for smoothing the outputs of the plurality of boost chopper circuits and supplying the load to a load;
A control unit that controls the plurality of boost chopper circuits to operate in different phases based on an input voltage and an input current of the plurality of boost chopper circuits and an output voltage of the capacitor , the error amplifier using the output voltage; The difference between the detected value and the reference value is amplified by a multiplier, the detected value of the input voltage is multiplied by the output of the error amplification by a multiplier, and the difference between the output of the multiplier and the detected value of the input current is multiplied by an amplifier. The output of the other sawtooth wave generator is output at a predetermined phase of the output of one sawtooth wave generator of the plurality of sawtooth wave generators by a plurality of comparators. A control unit for obtaining a plurality of pulse-width-modulated control signals respectively by comparing with outputs of a plurality of sawtooth wave generators having a phase difference between the plurality of outputs by a delay circuit for resetting ,
A power factor correction apparatus comprising: 前記複数の昇圧チョッパ回路の入力電流が個々の昇圧チョッパ回路ごとの入力電流である、
ことを特徴とする請求項１に記載の力率改善装置。 The input current of the plurality of boost chopper circuits is an input current for each boost chopper circuit,
The power factor correction apparatus according to claim 1. 前記複数の昇圧チョッパ回路の個数が２である、
ことを特徴とする請求項１または請求項２に記載の力率改善装置。 The number of the plurality of boost chopper circuits is two.
The power factor correction apparatus according to claim 1 or 2, characterized by the above. 前記制御部が前記２つの昇圧チョッパ回路を１／２周期の位相差で動作するように制御する、
ことを特徴とする請求項３に記載の力率改善装置。 The control unit controls the two boost chopper circuits to operate with a phase difference of ½ period;
The power factor correction apparatus according to claim 3.
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