JP4567410B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP4567410B2
JP4567410B2 JP2004304569A JP2004304569A JP4567410B2 JP 4567410 B2 JP4567410 B2 JP 4567410B2 JP 2004304569 A JP2004304569 A JP 2004304569A JP 2004304569 A JP2004304569 A JP 2004304569A JP 4567410 B2 JP4567410 B2 JP 4567410B2
Authority
JP
Japan
Prior art keywords
semiconductor device
post
electrode pad
particles
resin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2004304569A
Other languages
Japanese (ja)
Other versions
JP2006120716A (en
Inventor
修 宮田
正樹 葛西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2004304569A priority Critical patent/JP4567410B2/en
Publication of JP2006120716A publication Critical patent/JP2006120716A/en
Application granted granted Critical
Publication of JP4567410B2 publication Critical patent/JP4567410B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Description

本発明は、いわゆるウエハレベルＣＳＰなどのポストを有する半導体装置に関する。   The present invention relates to a semiconductor device having a post such as a so-called wafer level CSP.

ウエハレベルＣＳＰ(Chip Size Package)は、半導体チップにおいて回路が形成された活性面上に再配置配線、および封止用の樹脂膜が順に形成されてなる。再配置配線は、電極パッドを含んでおり、この電極パッド上に、樹脂膜を厚さ方向に貫通する銅（Ｃｕ）からなるポスト（柱状電極）が接続されている。ポストの長さは、樹脂膜の厚さとほぼ同じにされており、ポストの側面のほぼ全体が樹脂膜に覆われるようにされている。   In a wafer level CSP (Chip Size Package), a rearrangement wiring and a sealing resin film are sequentially formed on an active surface on which a circuit is formed in a semiconductor chip. The rearrangement wiring includes an electrode pad, and a post (columnar electrode) made of copper (Cu) penetrating the resin film in the thickness direction is connected to the electrode pad. The length of the post is substantially the same as the thickness of the resin film, and almost the entire side surface of the post is covered with the resin film.

ポストの先端には、半田ボールなどの接続材料が接続されており、この接続材料を介して、ポストを実装基板上の電極パッドに接続できるようになっている。
特開２０００−１８３０８９号公報 特開２０００−１８３０９０号公報 A connecting material such as a solder ball is connected to the tip of the post, and the post can be connected to the electrode pad on the mounting substrate via this connecting material.
JP 2000-183089 A JP 2000-183090 A

ところが、従来のウエハレベルＣＳＰは、ポストの長さを、たとえば、５０μｍ〜９０μｍ程度にしなければ、ポストに与えられる応力を緩和することができず、これよりポストを短くすると、ポストと半田ボールとの接続部やポストと半導体チップの電極パッドとの接続部が破断することがあった。
したがって、樹脂膜の厚さも５０μｍ〜９０μｍ程度にする必要があり、このため、ウエハレベルＣＳＰの厚さ（半導体チップと樹脂膜との積層方向の長さ）を低減することができなかった。 However, in the conventional wafer level CSP, unless the post length is set to about 50 μm to 90 μm, for example, the stress applied to the post cannot be relaxed. In some cases, the connection portion between the post and the connection portion between the post and the electrode pad of the semiconductor chip was broken.
Therefore, the thickness of the resin film needs to be about 50 μm to 90 μm. For this reason, the thickness of the wafer level CSP (the length in the stacking direction of the semiconductor chip and the resin film) cannot be reduced.

そこで、この発明の目的は、厚さを低減できる半導体装置を提供することである。   Accordingly, an object of the present invention is to provide a semiconductor device capable of reducing the thickness.

上記の目的を達成するための請求項１記載の発明は、半導体チップ（２）と、この半導体チップの表面を覆う樹脂膜（６）と、上記半導体チップに接続され、上記樹脂膜を厚さ方向に貫通するように設けられ、銅粒子（７）、および当該銅粒子よりも平均粒径の小さく、かつ、１０ｎｍ〜１００ｎｍの平均粒径を有する金属粒子（８）を含むポスト（５）とを含むことを特徴とする半導体装置（１）である。 The invention of claim 1, wherein for achieving the above object, a semiconductor chip (2), and cormorants covering the surface of the semiconductor chip tree Aburamaku (6), connected to the semiconductor chip, the resin film provided so as to penetrate in the thickness direction, the post including copper particles (7), and rather small average particle diameter than the copper particles, and metal particles having an average particle size of 10nm~100nm (8) ( And 5) a semiconductor device (1).

なお、括弧内の数字は、後述の実施形態における対応構成要素等を表す。以下、この項において同じ。
この発明によれば、ポストは、所定の平均粒径を有する銅粒子と、この銅粒子よりも平均粒径が小さい金属粒子（以下、「微小金属粒子」という。）とを含んでいる。したがって、この半導体装置は、ポストに与えられる応力を、銅粒子間に介在している微小金属粒子で吸収することができる。 The numbers in parentheses indicate corresponding components in the embodiments described later. The same applies hereinafter.
According to the present invention, the post includes copper particles having a predetermined average particle diameter and metal particles having an average particle diameter smaller than the copper particles (hereinafter referred to as “micro metal particles”). Therefore, this semiconductor device can absorb the stress applied to the post with the fine metal particles interposed between the copper particles.

このため、この半導体装置のポストは、銅からなるポストより長さを短くしても、ポストに与えられる応力を緩和することができる。ポストの長さは、たとえば、１０μｍ程度とすることができる。したがって、ポストの側面を覆う樹脂膜の厚さも低減することができるから、半導体装置全体の厚さも低減できる。
上記金属粒子の平均粒径が１０ｎｍ〜１００ｎｍであることにより、ポストに与えられる応力を効果的に緩和することができる。 For this reason, even if the post of this semiconductor device is made shorter than the post made of copper, the stress applied to the post can be relaxed. The length of the post can be, for example, about 10 μm. Therefore, since the thickness of the resin film covering the side surface of the post can be reduced, the thickness of the entire semiconductor device can also be reduced.
When the average particle diameter of the metal particles is 10 nm to 100 nm, the stress applied to the post can be effectively relaxed.

上記金属粒子は、請求項２記載のように、銀粒子であってもよい。
請求項３記載の発明は、上記半導体チップの上記樹脂膜が形成された上記表面は、回路が形成された活性面であり、上記活性面上には、電極パッドを含む再配置配線が形成されていることを特徴とする請求項１または２記載の半導体装置である。
請求項４記載の発明は、上記電極パッドは、銅からなることを特徴とする請求項３記載の半導体装置である。
請求項５記載の発明は、上記再配置配線上には、上記電極パッドを露出させる開口が形成されたパッシベーション膜が形成されていることを特徴とする請求項３または４記載の半導体装置である。
請求項６記載の発明は、上記パッシベーション膜上には、上記樹脂膜が形成されていることを特徴とする請求項５記載の半導体装置である。
請求項７記載の発明は、上記電極パッドには、上記ポストがほぼ垂直に接続されていることを特徴とする請求項３〜６のいずれか一項に記載の半導体装置である。
請求項８記載の発明は、上記ポストは、上記パッシベーション膜の上記開口を通り、上記樹脂膜をその厚さ方向に貫通していることを特徴とする請求項５または６記載の半導体装置である。
請求項９記載の発明は、上記銅粒子の平均粒径は、１μｍ〜２０μｍであることを特徴とする請求項１〜８のいずれか一項に記載の半導体装置である。
請求項１０記載の発明は、上記銅粒子と上記銀粒子とが、焼結していることを特徴とする請求項２記載の半導体装置である。
請求項１１記載の発明は、上記ポストの先端には、外部接続材料としての半田ボールが接続されていることを特徴とする請求項１〜１０のいずれか一項に記載の半導体装置である。
請求項１２記載の発明は、上記ポストは、熱硬化性の樹脂を含んでいることを特徴とする請求項１〜１１のいずれか一項に記載の半導体装置である。
請求項１３記載の発明は、当該半導体装置は、ウエハレベルＣＳＰであることを特徴とする請求項１〜１２のいずれか一項に記載の半導体装置である。
請求項１４記載の発明は、当該半導体装置は、フェースダウンで実装基板に実装可能であることを特徴とする請求項１〜１３のいずれか一項に記載の半導体装置である。 The metal particles may be silver particles as described in claim 2 .
According to a third aspect of the present invention, the surface of the semiconductor chip on which the resin film is formed is an active surface on which a circuit is formed, and a relocation wiring including an electrode pad is formed on the active surface. 3. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the electrode pad is made of copper.
According to a fifth aspect of the present invention, in the semiconductor device according to the third or fourth aspect, a passivation film having an opening for exposing the electrode pad is formed on the rearrangement wiring. .
A sixth aspect of the present invention is the semiconductor device according to the fifth aspect, wherein the resin film is formed on the passivation film.
A seventh aspect of the present invention is the semiconductor device according to any one of the third to sixth aspects, wherein the post is connected to the electrode pad substantially vertically.
The invention according to claim 8 is the semiconductor device according to claim 5 or 6, wherein the post passes through the opening of the passivation film and penetrates the resin film in a thickness direction thereof. .
The invention according to claim 9 is the semiconductor device according to claim 1, wherein the copper particles have an average particle diameter of 1 μm to 20 μm.
The invention according to claim 10 is the semiconductor device according to claim 2, wherein the copper particles and the silver particles are sintered.
An eleventh aspect of the invention is the semiconductor device according to any one of the first to tenth aspects, wherein a solder ball as an external connection material is connected to a tip of the post.
According to a twelfth aspect of the present invention, in the semiconductor device according to any one of the first to eleventh aspects, the post includes a thermosetting resin.
A thirteenth aspect of the present invention is the semiconductor device according to any one of the first to twelfth aspects, wherein the semiconductor device is a wafer level CSP.
The invention described in claim 14 is the semiconductor device according to any one of claims 1 to 13, wherein the semiconductor device can be mounted face-down on a mounting substrate.

以下では、この発明の実施の形態を、図面を参照して詳細に説明する。
図１は、本発明の一実施形態に係る半導体装置の構造を示す図解的な断面図である。
この半導体装置１は、いわゆる、ウエハレベルＣＳＰであり、半導体チップ２を備えている。半導体チップ２において、回路が形成された活性面２ａ上には、電極パッド３を含む再配置配線が形成されている。電極パッド３は、たとえば、銅（Ｃｕ）からなる。再配置配線上には電極パッド３を露出させる開口４ａが形成されたパッシベーション膜４が形成されている。パッシベーション膜４上には、樹脂膜６が形成されている。 Embodiments of the present invention will be described below in detail with reference to the drawings.
FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.
The semiconductor device 1 is a so-called wafer level CSP and includes a semiconductor chip 2. In the semiconductor chip 2, a rearrangement wiring including the electrode pad 3 is formed on the active surface 2 a on which a circuit is formed. The electrode pad 3 is made of, for example, copper (Cu). A passivation film 4 having an opening 4a for exposing the electrode pad 3 is formed on the rearrangement wiring. A resin film 6 is formed on the passivation film 4.

電極パッド３には、ポスト（たとえば、円柱状の柱状電極）５がほぼ垂直に接続されている。ポスト５は、パッシベーション膜４の開口４ａを通り、樹脂膜６をその厚さ方向に貫通している。ポスト５は、図２に示すように、所定の平均粒径を有する銅粒子７およびこの銅粒子７よりも平均粒径が小さい銀（Ａｇ）粒子８を含んでいる。顕微鏡等により測定した銅粒子７の平均粒径は、たとえば、１μｍ〜２０μｍ程度であり、電子顕微鏡等により測定した銀粒子８の平均粒径は、たとえば、１０ｎｍ〜１００ｎｍ程度である。銅粒子７や銀粒子８は、焼結していてもよい。   A post (for example, a columnar columnar electrode) 5 is connected to the electrode pad 3 substantially vertically. The post 5 passes through the opening 4a of the passivation film 4 and penetrates the resin film 6 in the thickness direction. As shown in FIG. 2, the post 5 includes copper particles 7 having a predetermined average particle diameter and silver (Ag) particles 8 having an average particle diameter smaller than that of the copper particles 7. The average particle diameter of the copper particles 7 measured with a microscope or the like is, for example, about 1 μm to 20 μm, and the average particle diameter of the silver particles 8 measured with an electron microscope or the like is, for example, about 10 nm to 100 nm. The copper particles 7 and the silver particles 8 may be sintered.

ポスト５は、樹脂膜６をその厚さ方向に貫通するように設けられている。ポスト５の先端（電極パッド３との接続部側と反対側）には、外部接続材料としての半田ボール９が接続されている。
この半導体装置１は、活性面２ａを実装基板に対向させたフェースダウン姿勢で実装基板に接続することができる。この際、半田ボール９を溶融および固化させて、ポスト５と実装基板の電極パッドとを接続することが可能である。 The post 5 is provided so as to penetrate the resin film 6 in the thickness direction. A solder ball 9 as an external connection material is connected to the tip of the post 5 (on the side opposite to the side connected to the electrode pad 3).
The semiconductor device 1 can be connected to the mounting board in a face-down posture with the active surface 2a facing the mounting board. At this time, the solder ball 9 can be melted and solidified to connect the post 5 and the electrode pad of the mounting substrate.

この半導体装置１は、ポスト５に与えられる応力を、ポスト５において銅粒子７間に介在している銀粒子８で吸収することができる。すなわち、ポスト５に応力が与えられると、銀粒子８を挟んで隣接する銅粒子７は、容易に相対的に移動することができる。このため、ポスト５と電極パッド３や半田ボール９との接続部には、大きな剪断応力がかからないので、ポスト５と電極パッド３や半田ボール９との接続部は破断されにくい。   The semiconductor device 1 can absorb the stress applied to the post 5 by the silver particles 8 interposed between the copper particles 7 in the post 5. That is, when stress is applied to the post 5, the adjacent copper particles 7 with the silver particles 8 interposed therebetween can easily move relatively. For this reason, since a large shear stress is not applied to the connection portion between the post 5 and the electrode pad 3 or the solder ball 9, the connection portion between the post 5 and the electrode pad 3 or the solder ball 9 is not easily broken.

このため、ポスト５の長さを長くして、ポスト５にかかる応力を分散させる必要はない。この半導体装置１は、ポスト５の長さを、たとえば、１０μｍ程度に短くしても、ポスト５と電極パッド３や半田ボール９との接続部が破断しないようにすることができる。したがって、ポスト５の側面を覆う樹脂膜６の厚さも低減することができるから、半導体装置１全体の厚さも低減できる。   For this reason, it is not necessary to lengthen the length of the post 5 and disperse the stress applied to the post 5. In the semiconductor device 1, even if the length of the post 5 is reduced to, for example, about 10 μm, the connection portion between the post 5 and the electrode pad 3 or the solder ball 9 can be prevented from breaking. Therefore, since the thickness of the resin film 6 covering the side surface of the post 5 can also be reduced, the thickness of the entire semiconductor device 1 can also be reduced.

この半導体装置１は、いわゆるウエハレベルＣＳＰ(Chip Size Package)であり、半導体チップ２に相当する領域を多数含む半導体ウエハ上で、回路の形成から半田ボール９の接続に至るまでのすべての工程が行われて製造される。
図３は、半導体装置１の製造方法を説明するための図解的な断面図である。
複数の半導体チップ２が作り込まれた半導体ウエハ（以下、単に「ウエハ」という。）Ｗの表面に、電極パッド３を露出させる開口４ａが形成されたパッシベーション膜４が形成され、さらに、開口４ａとほぼ同じ位置に開口４ａと連通する開口６ａが形成された樹脂膜６が形成される。図３において、隣接する半導体チップ３の境界Ｂを一点鎖線で示している。 This semiconductor device 1 is a so-called wafer level CSP (Chip Size Package), and all processes from formation of a circuit to connection of solder balls 9 are performed on a semiconductor wafer including many regions corresponding to the semiconductor chip 2. Made and manufactured.
FIG. 3 is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor device 1.
A passivation film 4 having an opening 4a for exposing the electrode pad 3 is formed on the surface of a semiconductor wafer (hereinafter simply referred to as “wafer”) W in which a plurality of semiconductor chips 2 are formed, and further, the opening 4a. The resin film 6 in which the opening 6a communicating with the opening 4a is formed at substantially the same position is formed. In FIG. 3, a boundary B between adjacent semiconductor chips 3 is indicated by a one-dot chain line.

次に、銅粉末、この銅粉末よりも平均粒径が小さい銀粉末、および樹脂や溶剤などの有機物を含むペースト１０が、たとえば、図３に示すようにスキージ１１を用いた印刷法により開口４ａ，６ａに埋め込まれる。
ペースト１０において、顕微鏡等により測定した銅粉末の平均粒径は、たとえば、１μｍ〜２０μｍ程度であり、電子顕微鏡等により測定した銀粉末の平均粒径は、たとえば、１０ｎｍ〜１００ｎｍ程度である。このようなペースト１０は、上記の平均粒径を有する銀粉末を含む銀ペーストに、銅粉末と、必要により樹脂や溶剤などの有機物を加えて混練することにより得られる。 Next, a paste 10 containing copper powder, a silver powder having an average particle size smaller than the copper powder, and an organic substance such as a resin or a solvent is formed into an opening 4a by a printing method using a squeegee 11 as shown in FIG. , 6a.
In paste 10, the average particle diameter of the copper powder measured with a microscope or the like is, for example, about 1 μm to 20 μm, and the average particle diameter of the silver powder measured with an electron microscope or the like is, for example, about 10 nm to 100 nm. Such a paste 10 is obtained by adding and kneading copper powder and, if necessary, organic substances such as a resin and a solvent to the silver paste containing the silver powder having the above average particle diameter.

その後、開口４ａ，６ａにペーストが埋め込まれたウエハＷが、適当な温度に加熱され、ペースト中の有機物が飛散されて、銅粒子７および銀粒子８を含むポスト５が形成される。上記平均粒径を有する銀粉末は、たとえば、１５０℃程度の低い温度でも容易に焼結する。
以上の工程を経たウエハＷから、半導体チップ２の個片を切り出すことにより、半導体装置１が得られる。このため、半導体装置１（パッケージ）の大きさは、半導体チップ２の大きさにほぼ等しい小さなものとなる。 After that, the wafer W in which the paste is embedded in the openings 4a and 6a is heated to an appropriate temperature, and the organic matter in the paste is scattered to form the post 5 including the copper particles 7 and the silver particles 8. The silver powder having the above average particle diameter is easily sintered even at a low temperature of about 150 ° C., for example.
The semiconductor device 1 is obtained by cutting out individual pieces of the semiconductor chip 2 from the wafer W that has undergone the above steps. For this reason, the size of the semiconductor device 1 (package) is small, which is substantially equal to the size of the semiconductor chip 2.

本発明の実施形態の説明は以上の通りであるが、本発明は他の形態でも実施できる。たとえば、ポスト５は、所定の平均粒径を有する銅粉末およびこの銅粉末よりも平均粒径が小さい銀粉末を含む熱硬化型のペーストが硬化されてなるものであってもよい。すなわち、ポスト５は、熱硬化性の樹脂を含んでいてもよい。このような半導体装置は、上記と同様の製造方法において、上記熱硬化型のペーストを開口４ａ，６ａに埋め込んだ後、ウエハＷを適当な温度に加熱して、当該ペーストを硬化させることにより得られる。   Although the embodiments of the present invention have been described above, the present invention can be implemented in other forms. For example, the post 5 may be formed by curing a thermosetting paste containing a copper powder having a predetermined average particle diameter and a silver powder having an average particle diameter smaller than the copper powder. That is, the post 5 may contain a thermosetting resin. Such a semiconductor device is obtained by embedding the thermosetting paste in the openings 4a and 6a in the same manufacturing method as described above, and then heating the wafer W to an appropriate temperature to cure the paste. It is done.

その他、特許請求の範囲に記載された事項の範囲で種々の変更を施すことが可能である。   In addition, various modifications can be made within the scope of the matters described in the claims.

本発明の一実施形態に係る半導体装置の構造を示す図解的な断面図である。1 is a schematic cross-sectional view showing a structure of a semiconductor device according to an embodiment of the present invention. ポストの組織を示す模式図である。It is a schematic diagram which shows the structure | tissue of a post. 図１に示す半導体装置の製造方法を説明するための図解的な断面図である。FIG. 3 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 1.

符号の説明Explanation of symbols

１ 半導体装置
２ 半導体チップ
５ ポスト
６ 樹脂膜
７ 銅粒子
８ 銀粒子 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor chip 5 Post 6 Resin film 7 Copper particle 8 Silver particle

Claims (14)

半導体チップと、
この半導体チップの表面を覆う樹脂膜と、
上記半導体チップに接続され、上記樹脂膜を厚さ方向に貫通するように設けられ、銅粒子、および当該銅粒子よりも平均粒径が小さく、かつ、１０ｎｍ〜１００ｎｍの平均粒径を有する金属粒子を含むポストとを含むことを特徴とする半導体装置。 A semiconductor chip;
The surface of the semiconductor chip and covering the Hare tree lipid membrane,
Connected to said semiconductor chip, provided to penetrate through the resin film in the thickness direction, rather small average particle diameter than the copper particles, and the copper particles, and a metal having an average particle size of 10nm~100nm A semiconductor device comprising a post containing particles. 上記金属粒子は、銀粒子であることを特徴とする請求項１記載の半導体装置。 The metal particles, semiconductor device according to claim 1 Symbol mounting characterized in that it is a silver particle. 上記半導体チップの上記樹脂膜が形成された上記表面は、回路が形成された活性面であり、  The surface on which the resin film of the semiconductor chip is formed is an active surface on which a circuit is formed,
上記活性面上には、電極パッドを含む再配置配線が形成されていることを特徴とする請求項１または２記載の半導体装置。  3. The semiconductor device according to claim 1, wherein a rearrangement wiring including an electrode pad is formed on the active surface. 上記電極パッドは、銅からなることを特徴とする請求項３記載の半導体装置。  4. The semiconductor device according to claim 3, wherein the electrode pad is made of copper. 上記再配置配線上には、上記電極パッドを露出させる開口が形成されたパッシベーション膜が形成されていることを特徴とする請求項３または４記載の半導体装置。  5. The semiconductor device according to claim 3, wherein a passivation film having an opening for exposing the electrode pad is formed on the rearrangement wiring. 6. 上記パッシベーション膜上には、上記樹脂膜が形成されていることを特徴とする請求項５記載の半導体装置。  6. The semiconductor device according to claim 5, wherein the resin film is formed on the passivation film. 上記電極パッドには、上記ポストがほぼ垂直に接続されていることを特徴とする請求項３〜６のいずれか一項に記載の半導体装置。  The semiconductor device according to claim 3, wherein the post is connected to the electrode pad substantially vertically. 上記ポストは、上記パッシベーション膜の上記開口を通り、上記樹脂膜をその厚さ方向に貫通していることを特徴とする請求項５または６記載の半導体装置。  7. The semiconductor device according to claim 5, wherein the post passes through the opening of the passivation film and penetrates the resin film in a thickness direction thereof. 上記銅粒子の平均粒径は、１μｍ〜２０μｍであることを特徴とする請求項１〜８のいずれか一項に記載の半導体装置。  The semiconductor device according to claim 1, wherein the copper particles have an average particle size of 1 μm to 20 μm. 上記銅粒子と上記銀粒子とが、焼結していることを特徴とする請求項２記載の半導体装置。  The semiconductor device according to claim 2, wherein the copper particles and the silver particles are sintered. 上記ポストの先端には、外部接続材料としての半田ボールが接続されていることを特徴とする請求項１〜１０のいずれか一項に記載の半導体装置。  The semiconductor device according to claim 1, wherein a solder ball as an external connection material is connected to a tip of the post. 上記ポストは、熱硬化性の樹脂を含んでいることを特徴とする請求項１〜１１のいずれか一項に記載の半導体装置。  The semiconductor device according to claim 1, wherein the post includes a thermosetting resin. 当該半導体装置は、ウエハレベルＣＳＰであることを特徴とする請求項１〜１２のいずれか一項に記載の半導体装置。  The semiconductor device according to claim 1, wherein the semiconductor device is a wafer level CSP. 当該半導体装置は、フェースダウンで実装基板に実装可能であることを特徴とする請求項１〜１３のいずれか一項に記載の半導体装置。  The semiconductor device according to claim 1, wherein the semiconductor device can be mounted face-down on a mounting substrate.
JP2004304569A 2004-10-19 2004-10-19 Semiconductor device Active JP4567410B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004304569A JP4567410B2 (en) 2004-10-19 2004-10-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004304569A JP4567410B2 (en) 2004-10-19 2004-10-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2006120716A JP2006120716A (en) 2006-05-11
JP4567410B2 true JP4567410B2 (en) 2010-10-20

Family

ID=36538339

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004304569A Active JP4567410B2 (en) 2004-10-19 2004-10-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4567410B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10872869B2 (en) 2018-08-20 2020-12-22 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4945329B2 (en) * 2007-06-04 2012-06-06 ローム株式会社 Organic EL display panel and manufacturing method thereof
JP2011204894A (en) * 2010-03-25 2011-10-13 Casio Computer Co Ltd Semiconductor device and method of manufacturing the same

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05320413A (en) * 1991-10-24 1993-12-03 Fujitsu Ltd Production of microencapsulated conductive filler
JPH07176846A (en) * 1993-10-29 1995-07-14 Matsushita Electric Ind Co Ltd Composition of conductor paste for filling via hole, both-sided and multilayered printed board using it, and its manufacture
JPH0922883A (en) * 1995-07-05 1997-01-21 Fujitsu Ltd Production of semiconductor device
JPH11310806A (en) * 1998-04-28 1999-11-09 Fukuda Metal Foil & Powder Co Ltd Production of copper-silver composite powder for electrically conductive paste
JP2000311969A (en) * 1999-04-27 2000-11-07 Sumitomo Electric Ind Ltd Copper circuit bonded board and manufacture of the same
JP2001135662A (en) * 1999-11-04 2001-05-18 Matsushita Electric Ind Co Ltd Semiconductor element and method for manufacturing semiconductor device
JP2001144212A (en) * 1999-11-16 2001-05-25 Ibiden Co Ltd Semiconductor chip
JP2001168232A (en) * 1999-12-14 2001-06-22 Matsushita Electric Ind Co Ltd Circuit part connection body and its manufacturing method, double-sided circuit board and its manufacturing method, circuit part packaging body, and multilayer circuit board
JP2002160090A (en) * 2000-11-27 2002-06-04 Tanaka Kikinzoku Kogyo Kk Ag-Cu-In-BASED BRAZING FILLER MATERIAL AND METHOD FOR PRODUCING THE SAME
JP2002164477A (en) * 2000-11-27 2002-06-07 Kyocera Corp Circuit board and method for manufacturing the same
JP2003027102A (en) * 2001-07-06 2003-01-29 Mitsui Mining & Smelting Co Ltd Silver-coated metal powder, method for manufacturing the same, conductive paste using the same, and printed wiring board containing conductor formed by using the conductive paste
JP2003105404A (en) * 2001-09-28 2003-04-09 Mitsui Mining & Smelting Co Ltd Producing method for silver coated copper powder, silver coated copper powder obtained by the producing method, conductive paste using the silver coated copper powder and printed circuit board using the conductive paste
JP2004119574A (en) * 2002-09-25 2004-04-15 Fujikura Ltd Semiconductor package and manufacturing method thereof
JP2005044798A (en) * 2003-07-08 2005-02-17 Hitachi Chem Co Ltd Conductive powder and its production method

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05320413A (en) * 1991-10-24 1993-12-03 Fujitsu Ltd Production of microencapsulated conductive filler
JPH07176846A (en) * 1993-10-29 1995-07-14 Matsushita Electric Ind Co Ltd Composition of conductor paste for filling via hole, both-sided and multilayered printed board using it, and its manufacture
JPH0922883A (en) * 1995-07-05 1997-01-21 Fujitsu Ltd Production of semiconductor device
JPH11310806A (en) * 1998-04-28 1999-11-09 Fukuda Metal Foil & Powder Co Ltd Production of copper-silver composite powder for electrically conductive paste
JP2000311969A (en) * 1999-04-27 2000-11-07 Sumitomo Electric Ind Ltd Copper circuit bonded board and manufacture of the same
JP2001135662A (en) * 1999-11-04 2001-05-18 Matsushita Electric Ind Co Ltd Semiconductor element and method for manufacturing semiconductor device
JP2001144212A (en) * 1999-11-16 2001-05-25 Ibiden Co Ltd Semiconductor chip
JP2001168232A (en) * 1999-12-14 2001-06-22 Matsushita Electric Ind Co Ltd Circuit part connection body and its manufacturing method, double-sided circuit board and its manufacturing method, circuit part packaging body, and multilayer circuit board
JP2002160090A (en) * 2000-11-27 2002-06-04 Tanaka Kikinzoku Kogyo Kk Ag-Cu-In-BASED BRAZING FILLER MATERIAL AND METHOD FOR PRODUCING THE SAME
JP2002164477A (en) * 2000-11-27 2002-06-07 Kyocera Corp Circuit board and method for manufacturing the same
JP2003027102A (en) * 2001-07-06 2003-01-29 Mitsui Mining & Smelting Co Ltd Silver-coated metal powder, method for manufacturing the same, conductive paste using the same, and printed wiring board containing conductor formed by using the conductive paste
JP2003105404A (en) * 2001-09-28 2003-04-09 Mitsui Mining & Smelting Co Ltd Producing method for silver coated copper powder, silver coated copper powder obtained by the producing method, conductive paste using the silver coated copper powder and printed circuit board using the conductive paste
JP2004119574A (en) * 2002-09-25 2004-04-15 Fujikura Ltd Semiconductor package and manufacturing method thereof
JP2005044798A (en) * 2003-07-08 2005-02-17 Hitachi Chem Co Ltd Conductive powder and its production method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10872869B2 (en) 2018-08-20 2020-12-22 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same

Also Published As

Publication number Publication date
JP2006120716A (en) 2006-05-11

Similar Documents

Publication Publication Date Title
JP5215605B2 (en) Manufacturing method of semiconductor device
US7205674B2 (en) Semiconductor package with build-up layers formed on chip and fabrication method of the semiconductor package
KR100921919B1 (en) Copper pillar tin bump on semiconductor chip and method of forming of the same
US7224073B2 (en) Substrate for solder joint
JP4131595B2 (en) Manufacturing method of semiconductor device
US9754928B2 (en) SMD, IPD, and/or wire mount in a package
US20060163749A1 (en) IC chip package structure and underfill process
US20040245608A1 (en) Semiconductor package having conductive bumps on chip and method for fabricating the same
JP2004023101A (en) Semiconductor device package and its manufacture
JP2004327855A (en) Semiconductor device and its manufacturing method
JP2008226946A (en) Semiconductor device and its manufacturing method
TWI644367B (en) Device with thermal interface and manufacturing method
TW201128721A (en) Manufacturing method of semiconductor device
US20150187722A1 (en) Semiconductor package and fabrication method thereof
JP2009194079A (en) Wiring substrate for use in semiconductor apparatus, method for fabricating the same, and semiconductor apparatus using the same
US7538022B2 (en) Method of manufacturing electronic circuit device
DE102010029550B4 (en) Process for the production of semiconductor devices
JP5337404B2 (en) Semiconductor device and manufacturing method of semiconductor device
TW200935573A (en) Insulative wiring board, semiconductor package using the same, and method for producing the insulative wiring board
JP4567410B2 (en) Semiconductor device
JP3116926B2 (en) Package structure and semiconductor device, package manufacturing method, and semiconductor device manufacturing method
JP5020051B2 (en) Semiconductor device
US20110134612A1 (en) Rebuilt wafer assembly
US9373526B2 (en) Chip package and method for forming the same
TWI508197B (en) Semiconductor package and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070607

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20071203

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100506

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100705

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100729

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100805

R150 Certificate of patent or registration of utility model

Ref document number: 4567410

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130813

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250