JP4534132B2 - 積層型半導体メモリ装置 - Google Patents
積層型半導体メモリ装置 Download PDFInfo
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- JP4534132B2 JP4534132B2 JP2004191410A JP2004191410A JP4534132B2 JP 4534132 B2 JP4534132 B2 JP 4534132B2 JP 2004191410 A JP2004191410 A JP 2004191410A JP 2004191410 A JP2004191410 A JP 2004191410A JP 4534132 B2 JP4534132 B2 JP 4534132B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 230000015654 memory Effects 0.000 claims abstract description 147
- 239000000872 buffer Substances 0.000 claims description 17
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000003491 array Methods 0.000 abstract description 4
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Description
前記メモリセルアレイチップの前記複数のバンクメモリの各々は前記複数のデータ入出力端子の其々に対応する複数のサブバンク領域を備え、前記複数のバンクメモリの其々に含まれる所定のデータ入出力端子に対応する複数の所定のサブバンク領域はまとめて配置されると共に、前記所定のデータ入出力端子は前記まとめて配置された前記複数の所定のサブバンク領域の間に挟まれて配置され、
前記半導体チップに設けられる前記複数の入出力バッファと、前記メモリセルアレイチップに設けられる前記複数のデータ入出力端子とを其々互いに接続する複数のチップ間配線であって、前記まとめて配置された前記複数の所定のサブバンク領域の中心に配置されたチップ間配線を更に備えたことを特徴とする。
この場合、前記複数のバンクメモリは、4つのバンクに分割されたバンクメモリから構成されていることとしてもよい。
また、前記まとめて配置された前記複数のサブバンク領域を複数備えることとしてもよい。
また、前記メモリセルアレイチップは、各々が前記チップ間配線によって接続された複数のメモリセルアレイチップを積層して形成されていることとしてもよい。
また、前記複数のメモリセルアレイチップの各々は、特定のメモリセルアレイチップがアクセス状態にあるとき、他のメモリセルアレイチップを前記チップ間配線から電気的に切り離す絶縁手段を供えることとしてもよい。
また、前記複数のメモリセルアレイチップの各々が備える複数のバンクメモリは、他のメモリセルアレイチップとは異なるバンク番号を割り振られたバンクによって構成されることとしてもよい。
図2は本発明による積層型半導体メモリ装置の第1の実施例の構成を示す図である。
次に、本発明の第2の実施例について図4を参照して説明する。図4は、本発明の第2実施例である3次元半導体DRAM装置の構成を示す図である。本実施例は、外部とのインターフェース回路が集積されたインターフェースチップ50の上部にメモリ容量512MbのDRAMのメモリセルアレイチップ51が4枚積層されている。
次に、本発明の第3の実施例について図5を参照して説明する。図5は、本発明の第3実施例である3次元半導体DRAM装置の構成を示す図である。本実施例は、外部とのインターフェース回路を集積したインターフェースチップ60の上部に、メモリ容量512MbのDRAMのメモリセルアレイチップ61が4枚積層されている。メモリセルアレイチップ61は入出力4ビット、4バンクのメモリセルアレイにより構成されている。
次に、本発明の第4の実施例について図6を参照して説明する。図6は、本発明の第4実施例である3次元半導体DRAM装置の構成を示す図である。
11 DQ線
12 列デコーダ
13 行デコーダ
20 バンク
21 サブバンク
22 入出力1ビットのメモリ領域
30 インターフェースチップ
31 メモリセルアレイチップ
32 チップ間配線
33 入出力バッファ
50 インターフェースチップ
51 メモリセルアレイチップ
52 チップ間配線
53 入出力バッファ
60 インターフェースチップ
61 メモリセルアレイチップ
62 チップ間配線
63 入出力バッファ
70 インターフェースチップ
71 メモリセルアレイチップ
72 チップ間配線
73 入出力バッファ
Claims (8)
- 複数のバンクメモリ及び前記複数のバンクメモリにデータを送受信するための複数のデータ入出力端子を含んだメモリセルアレイチップと、前記複数のデータ入出力端子を介して前記複数のバンクメモリと其々データの送受信を行う複数の入出力バッファを含んだ半導体チップとが互いに積層されて構成された積層型半導体メモリ装置であって、
前記メモリセルアレイチップの前記複数のバンクメモリの各々は前記複数のデータ入出力端子の其々に対応する複数のサブバンク領域を備え、前記複数のバンクメモリの其々に含まれる所定のデータ入出力端子に対応する複数の所定のサブバンク領域はまとめて配置されると共に、前記所定のデータ入出力端子は前記まとめて配置された前記複数の所定のサブバンク領域の間に挟まれて配置され、
前記半導体チップに設けられる前記複数の入出力バッファと、前記メモリセルアレイチップに設けられる前記複数のデータ入出力端子とを其々互いに接続する複数のチップ間配線であって、前記まとめて配置された前記複数の所定のサブバンク領域の中心に配置されたチップ間配線を更に備えたことを特徴とする積層型半導体メモリ装置。 - 前記複数のバンクメモリは、4つのバンクに分割されたバンクメモリから構成されていることを特徴とする請求項1記載の積層型半導体メモリ装置。
- 前記まとめて配置された前記複数のサブバンク領域を複数備えることを特徴とする請求項1記載の積層型半導体メモリ装置。
- 前記メモリセルアレイチップは、各々が前記チップ間配線によって接続された複数のメモリセルアレイチップを積層して形成されていることを特長とする請求項1記載の積層型半導体メモリ装置。
- 前記複数のメモリセルアレイチップの各々は、特定のメモリセルアレイチップがアクセス状態にあるとき、他のメモリセルアレイチップを前記チップ間配線から電気的に切り離す絶縁手段を供えることを特徴とする請求項4記載の積層型半導体メモリ装置。
- 前記複数のメモリセルアレイチップの各々が備える複数のバンクメモリは、他のメモリセルアレイチップとは異なるバンク番号を割り振られたバンクによって構成されることを特徴とする請求項4記載の積層型半導体メモリ装置。
- 前記半導体チップは外部とのインターフェース回路を有するインターフェースチップであることを特徴とする請求項1に記載の積層型半導体メモリ装置。
- 前記半導体チップはマイクロプロセッサー回路を有するプロセッサーチップであることを特徴とする請求項1に記載の積層型半導体メモリ装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004191410A JP4534132B2 (ja) | 2004-06-29 | 2004-06-29 | 積層型半導体メモリ装置 |
US11/151,213 US7209376B2 (en) | 2004-06-29 | 2005-06-14 | Stacked semiconductor memory device |
TW094121477A TWI293505B (en) | 2004-06-29 | 2005-06-27 | Stacked semiconductor memory device |
CNB2005100814890A CN100383968C (zh) | 2004-06-29 | 2005-06-29 | 层迭式半导体存储器件 |
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JP2004191410A JP4534132B2 (ja) | 2004-06-29 | 2004-06-29 | 積層型半導体メモリ装置 |
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JP2006012358A JP2006012358A (ja) | 2006-01-12 |
JP4534132B2 true JP4534132B2 (ja) | 2010-09-01 |
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US (1) | US7209376B2 (ja) |
JP (1) | JP4534132B2 (ja) |
CN (1) | CN100383968C (ja) |
TW (1) | TWI293505B (ja) |
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JPH04196263A (ja) * | 1990-11-27 | 1992-07-16 | Mitsubishi Electric Corp | 半導体集積回路 |
JPH06291250A (ja) * | 1993-04-06 | 1994-10-18 | Nec Corp | 半導体集積回路およびその形成方法 |
JPH08255479A (ja) * | 1995-03-20 | 1996-10-01 | Fujitsu Ltd | 半導体記憶装置 |
JPH1069767A (ja) * | 1996-06-29 | 1998-03-10 | Hyundai Electron Ind Co Ltd | 半導体メモリ素子のバンク分散方法 |
JP2002026283A (ja) * | 2000-06-30 | 2002-01-25 | Seiko Epson Corp | 多層構造のメモリ装置及びその製造方法 |
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CN100383968C (zh) | 2008-04-23 |
US20050286334A1 (en) | 2005-12-29 |
US7209376B2 (en) | 2007-04-24 |
JP2006012358A (ja) | 2006-01-12 |
TWI293505B (en) | 2008-02-11 |
TW200623395A (en) | 2006-07-01 |
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