JP4531615B2 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
- Publication number
- JP4531615B2 JP4531615B2 JP2005108252A JP2005108252A JP4531615B2 JP 4531615 B2 JP4531615 B2 JP 4531615B2 JP 2005108252 A JP2005108252 A JP 2005108252A JP 2005108252 A JP2005108252 A JP 2005108252A JP 4531615 B2 JP4531615 B2 JP 4531615B2
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- wiring
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- 239000004065 semiconductor Substances 0.000 title claims description 37
- 239000010410 layer Substances 0.000 claims description 140
- 239000003990 capacitor Substances 0.000 claims description 122
- 239000011229 interlayer Substances 0.000 claims description 24
- 239000000725 suspension Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 12
- 230000001681 protective effect Effects 0.000 claims description 9
- 230000015556 catabolic process Effects 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 238000000034 method Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000003491 array Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000005260 alpha ray Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/18—Peripheral circuit regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
101 フィールド絶縁膜
103 N型拡散層
104 P型拡散層
106 ゲート電極
111 第1層間絶縁膜
121 第2層間絶縁膜
131 容量絶縁膜
132 上部容量電極
141 第3層間絶縁膜
MC メモリセル
TU 吊り部
HO 保護部
Q1,Q2 負荷トランジスタ
Q3,Q4 駆動トランジスタ
Q5,Q6 転送トランジスタ
Q11 保護トランジスタ
N1,N2 ノード配線
C1〜C4 キャパシタ
DL1,DL2 デジット線
WL ワード線
VDDL 電源線
GNDL 接地線
UVDDL 下層電源線
UGNDL 下層接地線
H1 第1配線層
H2 第2配線層
H3 第3配線層
V1 第1ビア
V2 第2ビア
T11,T12,T13 中継電極(第1配線層)
T3 中継電極(第3配線層)
Claims (11)
- 半導体基板上に回路素子とキャパシタとを備える半導体集積回路装置であって、前記回路素子に接続される下層配線で構成される下部容量電極と、前記下層配線の上面及び側面を覆うように形成される容量絶縁膜と、前記容量絶縁膜上に形成される上部容量電極とでキャパシタを構成し、前記回路素子はSRAMのメモリセルであり、当該メモリセルは少なくともゲートとドレインとを一対のノード配線によって交差接続した一対の駆動トランジスタを備え、前記キャパシタは前記一対のノード配線にそれぞれ接続される一対のキャパシタであり、前記キャパシタの前記下部容量電極は前記各ノード配線と下層接地配線又は下層電源配線の少なくとも一方で構成され、前記SRAMは、少なくとも1つ以上のメモリセルと、前記メモリセルを上層配線で構成された電源配線及び接地配線に電気接続するための吊り部とを配列した構成とされ、前記下層電源配線及び前記下層接地配線は前記吊り部の領域にまで延長され、この延長領域において前記上層の電源配線又は接地配線に電気接続され、前記上部容量電極には前記電源配線又は前記接地配線との間に静電破壊防止の保護素子が接続されていることを特徴とする半導体集積回路装置。
- 前記下部容量電極は半導体基板上に形成された層間絶縁膜に形成された溝内に埋め込まれるとともにその上面及び側面の少なくとも一部が前記層間絶縁膜の表面上に露出され、前記容量絶縁膜は前記層間絶縁膜上に露出された前記下部容量電極の露出面を覆うように形成され、前記上部容量電極は少なくとも一部が前記下部容量電極の露出面に対向されていることを特徴とする請求項1に記載の半導体集積回路装置。
- 前記メモリセルは、前記一対のノード配線と当該メモリセルにデータを入出力する配線としての一対のデジット線との間にそれぞれ接続される一対の転送トランジスタと、前記一対の駆動トランジスタにそれぞれ接続される一対の負荷トランジスタとを備える6トランジスタ構成のメモリセルとして構成されていることを特徴とする請求項1又は2に記載の半導体集積回路装置。
- 前記上部容量電極は、前記ノード配線と、前記下層接地配線又は下層電源配線の少なくとも一方を覆う領域に形成されていることを特徴とする請求項1ないし3のいずれかに記載の半導体集積回路装置。
- 前記上部容量電極はメモリセルの領域のうち、上層配線との電気接続を行う領域以外の領域にわたって形成されていることを特徴とする請求項1ないし3のいずれかに記載の半導体集積回路装置。
- 前記SRAMは複数のメモリセルが半導体基板上に配列されており、前記上部容量電極は隣接するメモリセルの領域にわたって延長されていることを特徴とする請求項1ないし5のいずれかに記載の半導体集積回路装置。
- 前記保護素子は前記転送トランジスタ、駆動トランジスタ、負荷トランジスタと同時に形成されたMOSトランジスタ、バイポーラトランジスタ、ダイオードのいずれかで構成されていることを特徴とする請求項1ないし6のいずれかに記載の半導体集積回路装置。
- 前記保護素子は前記メモリセルと前記吊り部とを一方向に配列したメモリセル列の片側又は両側の領域に配設されていることを特徴とする請求項7に記載の半導体集積回路装置。
- 前記保護素子は1つのメモリセル列に対して1つの保護素子が接続されていることを特徴とする請求項8に記載の半導体集積回路装置。
- 前記保護素子は複数のメモリセル列に共通に接続されていることを特徴とする請求項8に記載の半導体集積回路装置。
- 前記メモリセルを構成するトランジスタ上に順次第1配線層、第2配線層、第3配線層が多層に形成され、前記第1配線層で前記ノード配線、下層電源配線、下層接地配線が構成され、前記第2配線層で前記上部容量電極が構成され、前記第3配線層で前記上層配線が構成されていることを特徴とする請求項1ないし10のいずれかに記載の半導体集積回路装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005108252A JP4531615B2 (ja) | 2005-02-03 | 2005-04-05 | 半導体集積回路装置 |
US11/345,311 US7777263B2 (en) | 2005-02-03 | 2006-02-02 | Semiconductor integrated circuit device comprising SRAM and capacitors |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005027230 | 2005-02-03 | ||
JP2005108252A JP4531615B2 (ja) | 2005-02-03 | 2005-04-05 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006245521A JP2006245521A (ja) | 2006-09-14 |
JP4531615B2 true JP4531615B2 (ja) | 2010-08-25 |
Family
ID=36755602
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005108252A Expired - Fee Related JP4531615B2 (ja) | 2005-02-03 | 2005-04-05 | 半導体集積回路装置 |
Country Status (2)
Country | Link |
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US (1) | US7777263B2 (ja) |
JP (1) | JP4531615B2 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008016490A (ja) * | 2006-07-03 | 2008-01-24 | Nec Electronics Corp | 半導体装置 |
JP2008227344A (ja) * | 2007-03-15 | 2008-09-25 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP5386819B2 (ja) | 2007-12-14 | 2014-01-15 | 富士通セミコンダクター株式会社 | 半導体記憶装置 |
US8580675B2 (en) | 2011-03-02 | 2013-11-12 | Texas Instruments Incorporated | Two-track cross-connect in double-patterned structure using rectangular via |
US20120280133A1 (en) * | 2011-05-03 | 2012-11-08 | Trusted Semiconductor Solutions, Inc. | Neutron detector having plurality of sensing elements |
TWI541978B (zh) * | 2011-05-11 | 2016-07-11 | 半導體能源研究所股份有限公司 | 半導體裝置及半導體裝置之驅動方法 |
US8982607B2 (en) | 2011-09-30 | 2015-03-17 | Semiconductor Energy Laboratory Co., Ltd. | Memory element and signal processing circuit |
KR101844058B1 (ko) * | 2012-02-01 | 2018-03-30 | 에스케이하이닉스 주식회사 | 복층 금속 콘택을 포함하는 반도체 소자 |
KR20160136715A (ko) * | 2015-05-20 | 2016-11-30 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US10128253B2 (en) * | 2016-01-29 | 2018-11-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Two-port SRAM structure |
KR20210128560A (ko) * | 2020-04-16 | 2021-10-27 | 삼성디스플레이 주식회사 | 표시 장치 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05167037A (ja) * | 1991-12-17 | 1993-07-02 | Sony Corp | 半導体メモリ装置及びその製法 |
JPH09181267A (ja) * | 1995-10-31 | 1997-07-11 | Texas Instr Inc <Ti> | Esd保護回路 |
JPH10163440A (ja) * | 1996-11-27 | 1998-06-19 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JPH11163166A (ja) * | 1997-11-28 | 1999-06-18 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
JP2002324855A (ja) * | 2001-04-26 | 2002-11-08 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体集積回路装置 |
JP2003007978A (ja) * | 2001-06-18 | 2003-01-10 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6271131B1 (en) * | 1998-08-26 | 2001-08-07 | Micron Technology, Inc. | Methods for forming rhodium-containing layers such as platinum-rhodium barrier layers |
US6100155A (en) * | 1998-09-10 | 2000-08-08 | Chartered Semiconductor Manufacturing, Ltd. | Metal-oxide-metal capacitor for analog devices |
JP2002050183A (ja) * | 2000-07-31 | 2002-02-15 | Mitsubishi Electric Corp | 半導体記憶装置 |
US20020072172A1 (en) * | 2000-12-08 | 2002-06-13 | Chi-Horn Pai | Method of fabricating a storage node |
JP2004186501A (ja) * | 2002-12-04 | 2004-07-02 | Renesas Technology Corp | 半導体装置 |
US6730950B1 (en) * | 2003-01-07 | 2004-05-04 | Texas Instruments Incorporated | Local interconnect using the electrode of a ferroelectric |
-
2005
- 2005-04-05 JP JP2005108252A patent/JP4531615B2/ja not_active Expired - Fee Related
-
2006
- 2006-02-02 US US11/345,311 patent/US7777263B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05167037A (ja) * | 1991-12-17 | 1993-07-02 | Sony Corp | 半導体メモリ装置及びその製法 |
JPH09181267A (ja) * | 1995-10-31 | 1997-07-11 | Texas Instr Inc <Ti> | Esd保護回路 |
JPH10163440A (ja) * | 1996-11-27 | 1998-06-19 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JPH11163166A (ja) * | 1997-11-28 | 1999-06-18 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
JP2002324855A (ja) * | 2001-04-26 | 2002-11-08 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体集積回路装置 |
JP2003007978A (ja) * | 2001-06-18 | 2003-01-10 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2006245521A (ja) | 2006-09-14 |
US20060170023A1 (en) | 2006-08-03 |
US7777263B2 (en) | 2010-08-17 |
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